Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8390993 |
1 |
|
|
T33 |
1496 |
|
T34 |
232 |
|
T1 |
110 |
| auto[1] |
6398725 |
1 |
|
|
T1 |
37 |
|
T11 |
31853 |
|
T12 |
291 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12158414 |
1 |
|
|
T33 |
1496 |
|
T34 |
232 |
|
T1 |
130 |
| auto[1] |
2631304 |
1 |
|
|
T1 |
17 |
|
T11 |
14365 |
|
T12 |
256 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8445737 |
1 |
|
|
T33 |
1496 |
|
T34 |
232 |
|
T1 |
103 |
| auto[1] |
6343981 |
1 |
|
|
T1 |
44 |
|
T11 |
32340 |
|
T12 |
499 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1835671 |
1 |
|
|
T1 |
17 |
|
T11 |
8882 |
|
T12 |
151 |
| auto[1] |
auto[0] |
auto[1] |
1306543 |
1 |
|
|
T1 |
13 |
|
T11 |
7244 |
|
T12 |
161 |
| auto[1] |
auto[1] |
auto[0] |
1877006 |
1 |
|
|
T1 |
10 |
|
T11 |
9093 |
|
T12 |
92 |
| auto[1] |
auto[1] |
auto[1] |
1324761 |
1 |
|
|
T1 |
4 |
|
T11 |
7121 |
|
T12 |
95 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |