Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8437148 |
1 |
|
|
T33 |
1496 |
|
T34 |
232 |
|
T1 |
95 |
| auto[1] |
6352570 |
1 |
|
|
T1 |
52 |
|
T11 |
31280 |
|
T12 |
401 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12171031 |
1 |
|
|
T33 |
1496 |
|
T34 |
232 |
|
T1 |
134 |
| auto[1] |
2618687 |
1 |
|
|
T1 |
13 |
|
T11 |
14325 |
|
T12 |
280 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8475435 |
1 |
|
|
T33 |
1496 |
|
T34 |
232 |
|
T1 |
109 |
| auto[1] |
6314283 |
1 |
|
|
T1 |
38 |
|
T11 |
32033 |
|
T12 |
592 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1845476 |
1 |
|
|
T1 |
14 |
|
T11 |
9089 |
|
T12 |
145 |
| auto[1] |
auto[0] |
auto[1] |
1307740 |
1 |
|
|
T1 |
13 |
|
T11 |
7285 |
|
T12 |
146 |
| auto[1] |
auto[1] |
auto[0] |
1850120 |
1 |
|
|
T1 |
11 |
|
T11 |
8619 |
|
T12 |
167 |
| auto[1] |
auto[1] |
auto[1] |
1310947 |
1 |
|
|
T11 |
7040 |
|
T12 |
134 |
|
T2 |
9 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |