Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8446792 |
1 |
|
|
T33 |
1496 |
|
T34 |
232 |
|
T1 |
87 |
| auto[1] |
6342926 |
1 |
|
|
T1 |
60 |
|
T11 |
31169 |
|
T12 |
341 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12166122 |
1 |
|
|
T33 |
1496 |
|
T34 |
232 |
|
T1 |
144 |
| auto[1] |
2623596 |
1 |
|
|
T1 |
3 |
|
T11 |
14088 |
|
T12 |
252 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8455999 |
1 |
|
|
T33 |
1496 |
|
T34 |
232 |
|
T1 |
127 |
| auto[1] |
6333719 |
1 |
|
|
T1 |
20 |
|
T11 |
31638 |
|
T12 |
510 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1855548 |
1 |
|
|
T1 |
3 |
|
T11 |
9172 |
|
T12 |
146 |
| auto[1] |
auto[0] |
auto[1] |
1318331 |
1 |
|
|
T1 |
3 |
|
T11 |
7310 |
|
T12 |
154 |
| auto[1] |
auto[1] |
auto[0] |
1854575 |
1 |
|
|
T1 |
14 |
|
T11 |
8378 |
|
T12 |
112 |
| auto[1] |
auto[1] |
auto[1] |
1305265 |
1 |
|
|
T11 |
6778 |
|
T12 |
98 |
|
T2 |
6 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |