Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8435222 |
1 |
|
|
T33 |
1496 |
|
T34 |
232 |
|
T1 |
108 |
| auto[1] |
6354496 |
1 |
|
|
T1 |
39 |
|
T11 |
31276 |
|
T12 |
502 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12157782 |
1 |
|
|
T33 |
1496 |
|
T34 |
232 |
|
T1 |
138 |
| auto[1] |
2631936 |
1 |
|
|
T1 |
9 |
|
T11 |
13414 |
|
T12 |
172 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8450273 |
1 |
|
|
T33 |
1496 |
|
T34 |
232 |
|
T1 |
113 |
| auto[1] |
6339445 |
1 |
|
|
T1 |
34 |
|
T11 |
30664 |
|
T12 |
370 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1855094 |
1 |
|
|
T1 |
23 |
|
T11 |
8828 |
|
T12 |
43 |
| auto[1] |
auto[0] |
auto[1] |
1314125 |
1 |
|
|
T1 |
4 |
|
T11 |
6747 |
|
T12 |
20 |
| auto[1] |
auto[1] |
auto[0] |
1852415 |
1 |
|
|
T1 |
2 |
|
T11 |
8422 |
|
T12 |
155 |
| auto[1] |
auto[1] |
auto[1] |
1317811 |
1 |
|
|
T1 |
5 |
|
T11 |
6667 |
|
T12 |
152 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |