Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8435731 |
1 |
|
|
T33 |
1496 |
|
T34 |
232 |
|
T1 |
104 |
| auto[1] |
6353987 |
1 |
|
|
T1 |
43 |
|
T11 |
32389 |
|
T12 |
192 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12153498 |
1 |
|
|
T33 |
1496 |
|
T34 |
232 |
|
T1 |
140 |
| auto[1] |
2636220 |
1 |
|
|
T1 |
7 |
|
T11 |
13494 |
|
T12 |
336 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8429317 |
1 |
|
|
T33 |
1496 |
|
T34 |
232 |
|
T1 |
119 |
| auto[1] |
6360401 |
1 |
|
|
T1 |
28 |
|
T11 |
30437 |
|
T12 |
658 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1869139 |
1 |
|
|
T1 |
14 |
|
T11 |
8530 |
|
T12 |
229 |
| auto[1] |
auto[0] |
auto[1] |
1323454 |
1 |
|
|
T1 |
7 |
|
T11 |
6888 |
|
T12 |
246 |
| auto[1] |
auto[1] |
auto[0] |
1855042 |
1 |
|
|
T1 |
7 |
|
T11 |
8413 |
|
T12 |
93 |
| auto[1] |
auto[1] |
auto[1] |
1312766 |
1 |
|
|
T11 |
6606 |
|
T12 |
90 |
|
T2 |
5 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |