Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8476223 |
1 |
|
|
T33 |
1496 |
|
T34 |
232 |
|
T1 |
93 |
| auto[1] |
6313495 |
1 |
|
|
T1 |
54 |
|
T11 |
31538 |
|
T12 |
243 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12163804 |
1 |
|
|
T33 |
1496 |
|
T34 |
232 |
|
T1 |
129 |
| auto[1] |
2625914 |
1 |
|
|
T1 |
18 |
|
T11 |
13891 |
|
T12 |
206 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8447824 |
1 |
|
|
T33 |
1496 |
|
T34 |
232 |
|
T1 |
113 |
| auto[1] |
6341894 |
1 |
|
|
T1 |
34 |
|
T11 |
30703 |
|
T12 |
447 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1866425 |
1 |
|
|
T1 |
16 |
|
T11 |
8870 |
|
T12 |
206 |
| auto[1] |
auto[0] |
auto[1] |
1316732 |
1 |
|
|
T1 |
6 |
|
T11 |
7223 |
|
T12 |
173 |
| auto[1] |
auto[1] |
auto[0] |
1849555 |
1 |
|
|
T11 |
7942 |
|
T12 |
35 |
|
T2 |
1 |
| auto[1] |
auto[1] |
auto[1] |
1309182 |
1 |
|
|
T1 |
12 |
|
T11 |
6668 |
|
T12 |
33 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |