Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8461830 |
1 |
|
|
T33 |
1496 |
|
T34 |
232 |
|
T1 |
105 |
| auto[1] |
6327888 |
1 |
|
|
T1 |
42 |
|
T11 |
30084 |
|
T12 |
161 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13974597 |
1 |
|
|
T33 |
1496 |
|
T34 |
232 |
|
T1 |
147 |
| auto[1] |
815121 |
1 |
|
|
T11 |
5006 |
|
T12 |
61 |
|
T2 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8449881 |
1 |
|
|
T33 |
1496 |
|
T34 |
232 |
|
T1 |
85 |
| auto[1] |
6339837 |
1 |
|
|
T1 |
62 |
|
T11 |
31617 |
|
T12 |
315 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2774529 |
1 |
|
|
T1 |
38 |
|
T11 |
13721 |
|
T12 |
227 |
| auto[1] |
auto[0] |
auto[1] |
410344 |
1 |
|
|
T11 |
2604 |
|
T12 |
55 |
|
T2 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2750187 |
1 |
|
|
T1 |
24 |
|
T11 |
12890 |
|
T12 |
27 |
| auto[1] |
auto[1] |
auto[1] |
404777 |
1 |
|
|
T11 |
2402 |
|
T12 |
6 |
|
T17 |
3371 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |