Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8430025 |
1 |
|
|
T33 |
1496 |
|
T34 |
232 |
|
T1 |
112 |
| auto[1] |
6359693 |
1 |
|
|
T1 |
35 |
|
T11 |
31131 |
|
T12 |
505 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12175307 |
1 |
|
|
T33 |
1496 |
|
T34 |
232 |
|
T1 |
125 |
| auto[1] |
2614411 |
1 |
|
|
T1 |
22 |
|
T11 |
13809 |
|
T12 |
241 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8478936 |
1 |
|
|
T33 |
1496 |
|
T34 |
232 |
|
T1 |
101 |
| auto[1] |
6310782 |
1 |
|
|
T1 |
46 |
|
T11 |
31298 |
|
T12 |
437 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1843019 |
1 |
|
|
T1 |
20 |
|
T11 |
8763 |
|
T12 |
57 |
| auto[1] |
auto[0] |
auto[1] |
1305697 |
1 |
|
|
T1 |
16 |
|
T11 |
6673 |
|
T12 |
63 |
| auto[1] |
auto[1] |
auto[0] |
1853352 |
1 |
|
|
T1 |
4 |
|
T11 |
8726 |
|
T12 |
139 |
| auto[1] |
auto[1] |
auto[1] |
1308714 |
1 |
|
|
T1 |
6 |
|
T11 |
7136 |
|
T12 |
178 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |