Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8450960 |
1 |
|
|
T33 |
1496 |
|
T34 |
232 |
|
T1 |
109 |
| auto[1] |
6338758 |
1 |
|
|
T1 |
38 |
|
T11 |
31402 |
|
T12 |
554 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12172504 |
1 |
|
|
T33 |
1496 |
|
T34 |
232 |
|
T1 |
126 |
| auto[1] |
2617214 |
1 |
|
|
T1 |
21 |
|
T11 |
13086 |
|
T12 |
217 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8461419 |
1 |
|
|
T33 |
1496 |
|
T34 |
232 |
|
T1 |
117 |
| auto[1] |
6328299 |
1 |
|
|
T1 |
30 |
|
T11 |
29435 |
|
T12 |
431 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1856623 |
1 |
|
|
T1 |
7 |
|
T11 |
7692 |
|
T12 |
66 |
| auto[1] |
auto[0] |
auto[1] |
1310613 |
1 |
|
|
T1 |
13 |
|
T11 |
6510 |
|
T12 |
66 |
| auto[1] |
auto[1] |
auto[0] |
1854462 |
1 |
|
|
T1 |
2 |
|
T11 |
8657 |
|
T12 |
148 |
| auto[1] |
auto[1] |
auto[1] |
1306601 |
1 |
|
|
T1 |
8 |
|
T11 |
6576 |
|
T12 |
151 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |