Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8460785 |
1 |
|
|
T33 |
1496 |
|
T34 |
232 |
|
T1 |
107 |
| auto[1] |
6328933 |
1 |
|
|
T1 |
40 |
|
T11 |
31999 |
|
T12 |
578 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12153764 |
1 |
|
|
T33 |
1496 |
|
T34 |
232 |
|
T1 |
140 |
| auto[1] |
2635954 |
1 |
|
|
T1 |
7 |
|
T11 |
13999 |
|
T12 |
180 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8424500 |
1 |
|
|
T33 |
1496 |
|
T34 |
232 |
|
T1 |
121 |
| auto[1] |
6365218 |
1 |
|
|
T1 |
26 |
|
T11 |
30736 |
|
T12 |
387 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1870894 |
1 |
|
|
T1 |
16 |
|
T11 |
8264 |
|
T12 |
97 |
| auto[1] |
auto[0] |
auto[1] |
1318973 |
1 |
|
|
T1 |
2 |
|
T11 |
7092 |
|
T12 |
71 |
| auto[1] |
auto[1] |
auto[0] |
1858370 |
1 |
|
|
T1 |
3 |
|
T11 |
8473 |
|
T12 |
110 |
| auto[1] |
auto[1] |
auto[1] |
1316981 |
1 |
|
|
T1 |
5 |
|
T11 |
6907 |
|
T12 |
109 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |