Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8443776 |
1 |
|
|
T33 |
1496 |
|
T34 |
232 |
|
T1 |
82 |
| auto[1] |
6345942 |
1 |
|
|
T1 |
65 |
|
T11 |
31205 |
|
T12 |
218 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13975746 |
1 |
|
|
T33 |
1496 |
|
T34 |
232 |
|
T1 |
146 |
| auto[1] |
813972 |
1 |
|
|
T1 |
1 |
|
T11 |
4813 |
|
T12 |
67 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8443379 |
1 |
|
|
T33 |
1496 |
|
T34 |
232 |
|
T1 |
113 |
| auto[1] |
6346339 |
1 |
|
|
T1 |
34 |
|
T11 |
30958 |
|
T12 |
333 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2780695 |
1 |
|
|
T1 |
9 |
|
T11 |
12856 |
|
T12 |
205 |
| auto[1] |
auto[0] |
auto[1] |
410898 |
1 |
|
|
T1 |
1 |
|
T11 |
2415 |
|
T12 |
52 |
| auto[1] |
auto[1] |
auto[0] |
2751672 |
1 |
|
|
T1 |
24 |
|
T11 |
13289 |
|
T12 |
61 |
| auto[1] |
auto[1] |
auto[1] |
403074 |
1 |
|
|
T11 |
2398 |
|
T12 |
15 |
|
T2 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |