Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8473288 |
1 |
|
|
T33 |
1496 |
|
T34 |
232 |
|
T1 |
104 |
| auto[1] |
6316430 |
1 |
|
|
T1 |
43 |
|
T11 |
32354 |
|
T12 |
545 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13981954 |
1 |
|
|
T33 |
1496 |
|
T34 |
232 |
|
T1 |
147 |
| auto[1] |
807764 |
1 |
|
|
T11 |
4910 |
|
T12 |
85 |
|
T17 |
7202 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8473380 |
1 |
|
|
T33 |
1496 |
|
T34 |
232 |
|
T1 |
118 |
| auto[1] |
6316338 |
1 |
|
|
T1 |
29 |
|
T11 |
30978 |
|
T12 |
441 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2765236 |
1 |
|
|
T1 |
7 |
|
T11 |
12321 |
|
T12 |
84 |
| auto[1] |
auto[0] |
auto[1] |
406630 |
1 |
|
|
T11 |
2368 |
|
T12 |
22 |
|
T17 |
3683 |
| auto[1] |
auto[1] |
auto[0] |
2743338 |
1 |
|
|
T1 |
22 |
|
T11 |
13747 |
|
T12 |
272 |
| auto[1] |
auto[1] |
auto[1] |
401134 |
1 |
|
|
T11 |
2542 |
|
T12 |
63 |
|
T17 |
3519 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |