Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8466556 |
1 |
|
|
T33 |
1496 |
|
T34 |
232 |
|
T1 |
87 |
| auto[1] |
6323162 |
1 |
|
|
T1 |
60 |
|
T11 |
32192 |
|
T12 |
532 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13981719 |
1 |
|
|
T33 |
1496 |
|
T34 |
232 |
|
T1 |
144 |
| auto[1] |
807999 |
1 |
|
|
T1 |
3 |
|
T11 |
5028 |
|
T12 |
70 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8479649 |
1 |
|
|
T33 |
1496 |
|
T34 |
232 |
|
T1 |
93 |
| auto[1] |
6310069 |
1 |
|
|
T1 |
54 |
|
T11 |
32141 |
|
T12 |
420 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2756709 |
1 |
|
|
T1 |
25 |
|
T11 |
12803 |
|
T12 |
133 |
| auto[1] |
auto[0] |
auto[1] |
405185 |
1 |
|
|
T1 |
2 |
|
T11 |
2300 |
|
T12 |
27 |
| auto[1] |
auto[1] |
auto[0] |
2745361 |
1 |
|
|
T1 |
26 |
|
T11 |
14310 |
|
T12 |
217 |
| auto[1] |
auto[1] |
auto[1] |
402814 |
1 |
|
|
T1 |
1 |
|
T11 |
2728 |
|
T12 |
43 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |