Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8438811 |
1 |
|
|
T33 |
1496 |
|
T34 |
232 |
|
T1 |
106 |
| auto[1] |
6350907 |
1 |
|
|
T1 |
41 |
|
T11 |
31426 |
|
T12 |
357 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13981312 |
1 |
|
|
T33 |
1496 |
|
T34 |
232 |
|
T1 |
146 |
| auto[1] |
808406 |
1 |
|
|
T1 |
1 |
|
T11 |
4753 |
|
T12 |
86 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8480187 |
1 |
|
|
T33 |
1496 |
|
T34 |
232 |
|
T1 |
115 |
| auto[1] |
6309531 |
1 |
|
|
T1 |
32 |
|
T11 |
30569 |
|
T12 |
469 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2749717 |
1 |
|
|
T1 |
20 |
|
T11 |
13115 |
|
T12 |
219 |
| auto[1] |
auto[0] |
auto[1] |
404727 |
1 |
|
|
T1 |
1 |
|
T11 |
2367 |
|
T12 |
46 |
| auto[1] |
auto[1] |
auto[0] |
2751408 |
1 |
|
|
T1 |
11 |
|
T11 |
12701 |
|
T12 |
164 |
| auto[1] |
auto[1] |
auto[1] |
403679 |
1 |
|
|
T11 |
2386 |
|
T12 |
40 |
|
T17 |
3389 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |