Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8413270 |
1 |
|
|
T33 |
1496 |
|
T34 |
232 |
|
T1 |
100 |
| auto[1] |
6376448 |
1 |
|
|
T1 |
47 |
|
T11 |
31867 |
|
T12 |
256 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13974201 |
1 |
|
|
T33 |
1496 |
|
T34 |
232 |
|
T1 |
146 |
| auto[1] |
815517 |
1 |
|
|
T1 |
1 |
|
T11 |
5000 |
|
T12 |
89 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8438595 |
1 |
|
|
T33 |
1496 |
|
T34 |
232 |
|
T1 |
133 |
| auto[1] |
6351123 |
1 |
|
|
T1 |
14 |
|
T11 |
32162 |
|
T12 |
471 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2749806 |
1 |
|
|
T1 |
10 |
|
T11 |
12326 |
|
T12 |
276 |
| auto[1] |
auto[0] |
auto[1] |
404306 |
1 |
|
|
T11 |
2357 |
|
T12 |
66 |
|
T17 |
3953 |
| auto[1] |
auto[1] |
auto[0] |
2785800 |
1 |
|
|
T1 |
3 |
|
T11 |
14836 |
|
T12 |
106 |
| auto[1] |
auto[1] |
auto[1] |
411211 |
1 |
|
|
T1 |
1 |
|
T11 |
2643 |
|
T12 |
23 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |