Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8453632 |
1 |
|
|
T33 |
1496 |
|
T34 |
232 |
|
T1 |
83 |
| auto[1] |
6336086 |
1 |
|
|
T1 |
64 |
|
T11 |
31214 |
|
T12 |
376 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13982339 |
1 |
|
|
T33 |
1496 |
|
T34 |
232 |
|
T1 |
143 |
| auto[1] |
807379 |
1 |
|
|
T1 |
4 |
|
T11 |
4748 |
|
T12 |
98 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8486007 |
1 |
|
|
T33 |
1496 |
|
T34 |
232 |
|
T1 |
76 |
| auto[1] |
6303711 |
1 |
|
|
T1 |
71 |
|
T11 |
30250 |
|
T12 |
514 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2760123 |
1 |
|
|
T1 |
41 |
|
T11 |
12993 |
|
T12 |
222 |
| auto[1] |
auto[0] |
auto[1] |
405578 |
1 |
|
|
T1 |
3 |
|
T11 |
2440 |
|
T12 |
50 |
| auto[1] |
auto[1] |
auto[0] |
2736209 |
1 |
|
|
T1 |
26 |
|
T11 |
12509 |
|
T12 |
194 |
| auto[1] |
auto[1] |
auto[1] |
401801 |
1 |
|
|
T1 |
1 |
|
T11 |
2308 |
|
T12 |
48 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |