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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.63 99.06 99.24 100.00 99.80 99.68 99.99


Total test records in report: 946
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T763 /workspace/coverage/cover_reg_top/32.gpio_intr_test.2201505610 Jul 29 04:33:09 PM PDT 24 Jul 29 04:33:09 PM PDT 24 35018529 ps
T764 /workspace/coverage/cover_reg_top/15.gpio_intr_test.3267331894 Jul 29 04:33:04 PM PDT 24 Jul 29 04:33:05 PM PDT 24 52234415 ps
T765 /workspace/coverage/cover_reg_top/11.gpio_csr_mem_rw_with_rand_reset.689712354 Jul 29 04:33:01 PM PDT 24 Jul 29 04:33:02 PM PDT 24 21286335 ps
T766 /workspace/coverage/cover_reg_top/39.gpio_intr_test.560717181 Jul 29 04:33:08 PM PDT 24 Jul 29 04:33:09 PM PDT 24 15930572 ps
T767 /workspace/coverage/cover_reg_top/20.gpio_intr_test.999327268 Jul 29 04:33:03 PM PDT 24 Jul 29 04:33:04 PM PDT 24 18318097 ps
T768 /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.1012505562 Jul 29 04:32:56 PM PDT 24 Jul 29 04:32:57 PM PDT 24 24308414 ps
T89 /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.2428990691 Jul 29 04:33:03 PM PDT 24 Jul 29 04:33:04 PM PDT 24 39823361 ps
T769 /workspace/coverage/cover_reg_top/14.gpio_tl_errors.3832506498 Jul 29 04:33:12 PM PDT 24 Jul 29 04:33:14 PM PDT 24 635345205 ps
T79 /workspace/coverage/cover_reg_top/2.gpio_csr_hw_reset.1950351765 Jul 29 04:32:47 PM PDT 24 Jul 29 04:32:48 PM PDT 24 71883617 ps
T770 /workspace/coverage/cover_reg_top/1.gpio_tl_errors.3221256363 Jul 29 04:32:49 PM PDT 24 Jul 29 04:32:51 PM PDT 24 47226873 ps
T771 /workspace/coverage/cover_reg_top/3.gpio_intr_test.1467182811 Jul 29 04:32:52 PM PDT 24 Jul 29 04:32:53 PM PDT 24 40402546 ps
T80 /workspace/coverage/cover_reg_top/3.gpio_csr_rw.3958494673 Jul 29 04:32:48 PM PDT 24 Jul 29 04:32:48 PM PDT 24 24617498 ps
T772 /workspace/coverage/cover_reg_top/29.gpio_intr_test.373355932 Jul 29 04:33:12 PM PDT 24 Jul 29 04:33:13 PM PDT 24 24911285 ps
T81 /workspace/coverage/cover_reg_top/1.gpio_csr_hw_reset.759013420 Jul 29 04:32:45 PM PDT 24 Jul 29 04:32:46 PM PDT 24 57325197 ps
T773 /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.53177567 Jul 29 04:33:04 PM PDT 24 Jul 29 04:33:05 PM PDT 24 27055957 ps
T90 /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.1306587905 Jul 29 04:23:23 PM PDT 24 Jul 29 04:23:24 PM PDT 24 12846848 ps
T774 /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.2462782865 Jul 29 04:32:46 PM PDT 24 Jul 29 04:32:47 PM PDT 24 43709302 ps
T91 /workspace/coverage/cover_reg_top/14.gpio_same_csr_outstanding.3539219099 Jul 29 04:33:06 PM PDT 24 Jul 29 04:33:07 PM PDT 24 19508418 ps
T775 /workspace/coverage/cover_reg_top/41.gpio_intr_test.3380739183 Jul 29 04:33:08 PM PDT 24 Jul 29 04:33:09 PM PDT 24 42154320 ps
T776 /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.1937751072 Jul 29 04:32:47 PM PDT 24 Jul 29 04:32:50 PM PDT 24 56942407 ps
T92 /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.3421599419 Jul 29 04:33:01 PM PDT 24 Jul 29 04:33:02 PM PDT 24 22246847 ps
T777 /workspace/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.519220208 Jul 29 04:32:47 PM PDT 24 Jul 29 04:32:48 PM PDT 24 352597733 ps
T778 /workspace/coverage/cover_reg_top/30.gpio_intr_test.26136552 Jul 29 04:33:08 PM PDT 24 Jul 29 04:33:09 PM PDT 24 53162727 ps
T779 /workspace/coverage/cover_reg_top/35.gpio_intr_test.2536047425 Jul 29 04:33:10 PM PDT 24 Jul 29 04:33:11 PM PDT 24 306318383 ps
T780 /workspace/coverage/cover_reg_top/24.gpio_intr_test.2823365482 Jul 29 04:33:09 PM PDT 24 Jul 29 04:33:10 PM PDT 24 56557218 ps
T48 /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.3015429018 Jul 29 04:33:01 PM PDT 24 Jul 29 04:33:03 PM PDT 24 203875439 ps
T781 /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.2431767632 Jul 29 04:33:10 PM PDT 24 Jul 29 04:33:11 PM PDT 24 58785732 ps
T782 /workspace/coverage/cover_reg_top/4.gpio_csr_bit_bash.2965062494 Jul 29 04:32:58 PM PDT 24 Jul 29 04:33:01 PM PDT 24 1006825380 ps
T783 /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.3014871465 Jul 29 04:32:59 PM PDT 24 Jul 29 04:33:00 PM PDT 24 556025146 ps
T784 /workspace/coverage/cover_reg_top/22.gpio_intr_test.3812172391 Jul 29 04:33:06 PM PDT 24 Jul 29 04:33:07 PM PDT 24 33948452 ps
T785 /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.3522125425 Jul 29 04:33:04 PM PDT 24 Jul 29 04:33:05 PM PDT 24 59760715 ps
T786 /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.2373953571 Jul 29 04:32:54 PM PDT 24 Jul 29 04:32:55 PM PDT 24 92899296 ps
T787 /workspace/coverage/cover_reg_top/12.gpio_intr_test.188092590 Jul 29 04:33:12 PM PDT 24 Jul 29 04:33:13 PM PDT 24 38243096 ps
T788 /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.1995997858 Jul 29 04:32:50 PM PDT 24 Jul 29 04:32:52 PM PDT 24 715445227 ps
T789 /workspace/coverage/cover_reg_top/47.gpio_intr_test.414136970 Jul 29 04:33:10 PM PDT 24 Jul 29 04:33:11 PM PDT 24 42489810 ps
T790 /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.3717631559 Jul 29 04:33:05 PM PDT 24 Jul 29 04:33:06 PM PDT 24 34647198 ps
T791 /workspace/coverage/cover_reg_top/19.gpio_tl_errors.804020997 Jul 29 04:33:08 PM PDT 24 Jul 29 04:33:10 PM PDT 24 28173643 ps
T792 /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.48873687 Jul 29 04:32:43 PM PDT 24 Jul 29 04:32:44 PM PDT 24 19218466 ps
T793 /workspace/coverage/cover_reg_top/12.gpio_csr_rw.2970174621 Jul 29 04:33:00 PM PDT 24 Jul 29 04:33:01 PM PDT 24 17169618 ps
T794 /workspace/coverage/cover_reg_top/13.gpio_tl_intg_err.1301103901 Jul 29 04:33:03 PM PDT 24 Jul 29 04:33:04 PM PDT 24 81608530 ps
T795 /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.3017081518 Jul 29 04:32:53 PM PDT 24 Jul 29 04:32:55 PM PDT 24 208902257 ps
T796 /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.3144589009 Jul 29 04:32:48 PM PDT 24 Jul 29 04:32:50 PM PDT 24 394716826 ps
T797 /workspace/coverage/cover_reg_top/49.gpio_intr_test.4180958745 Jul 29 04:33:09 PM PDT 24 Jul 29 04:33:10 PM PDT 24 13138742 ps
T798 /workspace/coverage/cover_reg_top/45.gpio_intr_test.1016649542 Jul 29 04:33:12 PM PDT 24 Jul 29 04:33:13 PM PDT 24 13696690 ps
T799 /workspace/coverage/cover_reg_top/16.gpio_csr_rw.1928816783 Jul 29 04:33:04 PM PDT 24 Jul 29 04:33:05 PM PDT 24 41808148 ps
T800 /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.563174277 Jul 29 04:33:01 PM PDT 24 Jul 29 04:33:02 PM PDT 24 30515157 ps
T801 /workspace/coverage/cover_reg_top/7.gpio_tl_errors.3235865579 Jul 29 04:32:57 PM PDT 24 Jul 29 04:33:00 PM PDT 24 56184446 ps
T802 /workspace/coverage/cover_reg_top/2.gpio_csr_rw.3667516907 Jul 29 04:32:47 PM PDT 24 Jul 29 04:32:47 PM PDT 24 18334196 ps
T803 /workspace/coverage/cover_reg_top/37.gpio_intr_test.2212159882 Jul 29 04:33:10 PM PDT 24 Jul 29 04:33:11 PM PDT 24 12693559 ps
T84 /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.830793433 Jul 29 04:25:24 PM PDT 24 Jul 29 04:25:27 PM PDT 24 306797487 ps
T804 /workspace/coverage/cover_reg_top/17.gpio_tl_errors.2969287452 Jul 29 04:33:04 PM PDT 24 Jul 29 04:33:06 PM PDT 24 144126261 ps
T805 /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.2996071243 Jul 29 04:32:56 PM PDT 24 Jul 29 04:32:58 PM PDT 24 924411688 ps
T806 /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.3309800123 Jul 29 04:24:47 PM PDT 24 Jul 29 04:24:48 PM PDT 24 17743813 ps
T807 /workspace/coverage/cover_reg_top/25.gpio_intr_test.1512937141 Jul 29 04:33:07 PM PDT 24 Jul 29 04:33:08 PM PDT 24 10914094 ps
T808 /workspace/coverage/cover_reg_top/0.gpio_tl_errors.3499210654 Jul 29 04:23:49 PM PDT 24 Jul 29 04:23:51 PM PDT 24 34539062 ps
T809 /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.415746610 Jul 29 04:33:07 PM PDT 24 Jul 29 04:33:08 PM PDT 24 254530461 ps
T82 /workspace/coverage/cover_reg_top/10.gpio_csr_rw.3517604440 Jul 29 04:32:59 PM PDT 24 Jul 29 04:33:00 PM PDT 24 129220825 ps
T810 /workspace/coverage/cover_reg_top/8.gpio_tl_errors.1937382429 Jul 29 04:33:12 PM PDT 24 Jul 29 04:33:14 PM PDT 24 71640561 ps
T811 /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.2742426167 Jul 29 04:33:08 PM PDT 24 Jul 29 04:33:08 PM PDT 24 151172581 ps
T812 /workspace/coverage/cover_reg_top/6.gpio_tl_errors.2322716465 Jul 29 04:32:52 PM PDT 24 Jul 29 04:32:55 PM PDT 24 126468966 ps
T813 /workspace/coverage/cover_reg_top/17.gpio_csr_rw.143881308 Jul 29 04:33:09 PM PDT 24 Jul 29 04:33:10 PM PDT 24 12102745 ps
T814 /workspace/coverage/cover_reg_top/1.gpio_tl_intg_err.2077948976 Jul 29 04:32:48 PM PDT 24 Jul 29 04:32:49 PM PDT 24 922508011 ps
T815 /workspace/coverage/cover_reg_top/0.gpio_csr_rw.987625665 Jul 29 04:23:34 PM PDT 24 Jul 29 04:23:34 PM PDT 24 13596329 ps
T816 /workspace/coverage/cover_reg_top/1.gpio_csr_rw.4133309772 Jul 29 04:25:56 PM PDT 24 Jul 29 04:25:57 PM PDT 24 45417024 ps
T817 /workspace/coverage/cover_reg_top/7.gpio_intr_test.2970404222 Jul 29 04:33:01 PM PDT 24 Jul 29 04:33:01 PM PDT 24 24427280 ps
T818 /workspace/coverage/cover_reg_top/0.gpio_intr_test.1124504385 Jul 29 04:25:17 PM PDT 24 Jul 29 04:25:18 PM PDT 24 59846557 ps
T819 /workspace/coverage/cover_reg_top/2.gpio_intr_test.1486069038 Jul 29 04:32:47 PM PDT 24 Jul 29 04:32:47 PM PDT 24 10725068 ps
T820 /workspace/coverage/cover_reg_top/5.gpio_tl_errors.3400805308 Jul 29 04:32:56 PM PDT 24 Jul 29 04:32:59 PM PDT 24 544652723 ps
T821 /workspace/coverage/cover_reg_top/2.gpio_same_csr_outstanding.2178408320 Jul 29 04:32:47 PM PDT 24 Jul 29 04:32:48 PM PDT 24 61551166 ps
T83 /workspace/coverage/cover_reg_top/19.gpio_csr_rw.2619615918 Jul 29 04:33:07 PM PDT 24 Jul 29 04:33:07 PM PDT 24 15081957 ps
T822 /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.2785716021 Jul 29 04:33:02 PM PDT 24 Jul 29 04:33:03 PM PDT 24 20165483 ps
T823 /workspace/coverage/cover_reg_top/10.gpio_intr_test.2171550227 Jul 29 04:33:09 PM PDT 24 Jul 29 04:33:10 PM PDT 24 14131476 ps
T824 /workspace/coverage/cover_reg_top/14.gpio_csr_rw.239229187 Jul 29 04:33:03 PM PDT 24 Jul 29 04:33:03 PM PDT 24 15222773 ps
T825 /workspace/coverage/cover_reg_top/8.gpio_same_csr_outstanding.581084841 Jul 29 04:33:09 PM PDT 24 Jul 29 04:33:14 PM PDT 24 30679583 ps
T826 /workspace/coverage/cover_reg_top/21.gpio_intr_test.1588265966 Jul 29 04:33:07 PM PDT 24 Jul 29 04:33:08 PM PDT 24 11827403 ps
T827 /workspace/coverage/cover_reg_top/40.gpio_intr_test.2400504799 Jul 29 04:33:09 PM PDT 24 Jul 29 04:33:09 PM PDT 24 12680949 ps
T828 /workspace/coverage/cover_reg_top/5.gpio_csr_rw.317928346 Jul 29 04:32:52 PM PDT 24 Jul 29 04:32:52 PM PDT 24 64748532 ps
T829 /workspace/coverage/cover_reg_top/14.gpio_tl_intg_err.1435791783 Jul 29 04:33:13 PM PDT 24 Jul 29 04:33:14 PM PDT 24 219040011 ps
T830 /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.1146991743 Jul 29 04:33:00 PM PDT 24 Jul 29 04:33:01 PM PDT 24 69278349 ps
T831 /workspace/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.3584250975 Jul 29 04:25:18 PM PDT 24 Jul 29 04:25:19 PM PDT 24 412742621 ps
T832 /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.1984967515 Jul 29 04:33:08 PM PDT 24 Jul 29 04:33:18 PM PDT 24 383074912 ps
T833 /workspace/coverage/cover_reg_top/4.gpio_intr_test.4157807458 Jul 29 04:32:52 PM PDT 24 Jul 29 04:32:53 PM PDT 24 49970305 ps
T834 /workspace/coverage/cover_reg_top/7.gpio_csr_rw.2693000785 Jul 29 04:32:53 PM PDT 24 Jul 29 04:32:54 PM PDT 24 39800563 ps
T835 /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.4292492603 Jul 29 04:33:05 PM PDT 24 Jul 29 04:33:06 PM PDT 24 150768276 ps
T836 /workspace/coverage/cover_reg_top/8.gpio_tl_intg_err.3275495676 Jul 29 04:32:57 PM PDT 24 Jul 29 04:32:59 PM PDT 24 97527129 ps
T837 /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.118185652 Jul 29 04:33:08 PM PDT 24 Jul 29 04:33:09 PM PDT 24 22252500 ps
T838 /workspace/coverage/cover_reg_top/11.gpio_same_csr_outstanding.3178569302 Jul 29 04:33:01 PM PDT 24 Jul 29 04:33:02 PM PDT 24 76668562 ps
T839 /workspace/coverage/cover_reg_top/11.gpio_tl_errors.3812406030 Jul 29 04:32:58 PM PDT 24 Jul 29 04:33:01 PM PDT 24 299168019 ps
T840 /workspace/coverage/cover_reg_top/36.gpio_intr_test.2636640581 Jul 29 04:33:11 PM PDT 24 Jul 29 04:33:11 PM PDT 24 40068418 ps
T841 /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.4199139638 Jul 29 04:32:52 PM PDT 24 Jul 29 04:32:53 PM PDT 24 72272749 ps
T842 /workspace/coverage/cover_reg_top/16.gpio_tl_errors.1970350777 Jul 29 04:33:07 PM PDT 24 Jul 29 04:33:10 PM PDT 24 35907995 ps
T843 /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.3770160539 Jul 29 04:32:47 PM PDT 24 Jul 29 04:32:48 PM PDT 24 103283834 ps
T844 /workspace/coverage/cover_reg_top/1.gpio_intr_test.2869621601 Jul 29 04:32:49 PM PDT 24 Jul 29 04:32:50 PM PDT 24 15056803 ps
T85 /workspace/coverage/cover_reg_top/9.gpio_csr_rw.2801603996 Jul 29 04:32:58 PM PDT 24 Jul 29 04:32:59 PM PDT 24 45764966 ps
T845 /workspace/coverage/cover_reg_top/31.gpio_intr_test.4098669716 Jul 29 04:33:12 PM PDT 24 Jul 29 04:33:12 PM PDT 24 56676039 ps
T846 /workspace/coverage/cover_reg_top/15.gpio_tl_errors.2428528292 Jul 29 04:33:08 PM PDT 24 Jul 29 04:33:10 PM PDT 24 185447880 ps
T847 /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.3552241449 Jul 29 04:33:14 PM PDT 24 Jul 29 04:33:16 PM PDT 24 66163433 ps
T848 /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2628470839 Jul 29 04:33:14 PM PDT 24 Jul 29 04:33:15 PM PDT 24 129516605 ps
T849 /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2649346838 Jul 29 04:33:22 PM PDT 24 Jul 29 04:33:23 PM PDT 24 204319513 ps
T850 /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.2520414834 Jul 29 04:33:33 PM PDT 24 Jul 29 04:33:35 PM PDT 24 115556394 ps
T851 /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.71837661 Jul 29 04:25:34 PM PDT 24 Jul 29 04:25:36 PM PDT 24 1360701007 ps
T852 /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.3751678067 Jul 29 04:33:27 PM PDT 24 Jul 29 04:33:28 PM PDT 24 50331377 ps
T853 /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4165262328 Jul 29 04:33:20 PM PDT 24 Jul 29 04:33:22 PM PDT 24 167552307 ps
T854 /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.946161574 Jul 29 04:33:20 PM PDT 24 Jul 29 04:33:21 PM PDT 24 71602265 ps
T855 /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.605211145 Jul 29 04:33:15 PM PDT 24 Jul 29 04:33:16 PM PDT 24 31414163 ps
T856 /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1920506061 Jul 29 04:33:32 PM PDT 24 Jul 29 04:33:33 PM PDT 24 47359575 ps
T857 /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3541813096 Jul 29 04:33:15 PM PDT 24 Jul 29 04:33:16 PM PDT 24 60840833 ps
T858 /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.714410832 Jul 29 04:33:31 PM PDT 24 Jul 29 04:33:32 PM PDT 24 142629385 ps
T859 /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3872046403 Jul 29 04:21:25 PM PDT 24 Jul 29 04:21:26 PM PDT 24 115267134 ps
T860 /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.654858183 Jul 29 04:33:28 PM PDT 24 Jul 29 04:33:29 PM PDT 24 51746921 ps
T861 /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.1000886659 Jul 29 04:33:16 PM PDT 24 Jul 29 04:33:17 PM PDT 24 137322085 ps
T862 /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.3278623067 Jul 29 04:33:31 PM PDT 24 Jul 29 04:33:32 PM PDT 24 27510804 ps
T863 /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.1187231920 Jul 29 04:33:15 PM PDT 24 Jul 29 04:33:17 PM PDT 24 75167234 ps
T864 /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2913957834 Jul 29 04:33:20 PM PDT 24 Jul 29 04:33:21 PM PDT 24 184233690 ps
T865 /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.2650301195 Jul 29 04:24:46 PM PDT 24 Jul 29 04:24:48 PM PDT 24 59149489 ps
T866 /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.2708037786 Jul 29 04:33:21 PM PDT 24 Jul 29 04:33:22 PM PDT 24 53133867 ps
T867 /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.2209033287 Jul 29 04:33:15 PM PDT 24 Jul 29 04:33:17 PM PDT 24 30745823 ps
T868 /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1385090371 Jul 29 04:33:23 PM PDT 24 Jul 29 04:33:24 PM PDT 24 328692057 ps
T869 /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.288723811 Jul 29 04:33:26 PM PDT 24 Jul 29 04:33:27 PM PDT 24 131513404 ps
T870 /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.1293340119 Jul 29 04:33:28 PM PDT 24 Jul 29 04:33:29 PM PDT 24 313889212 ps
T871 /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3612813980 Jul 29 04:33:15 PM PDT 24 Jul 29 04:33:17 PM PDT 24 293227167 ps
T872 /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.768497516 Jul 29 04:33:15 PM PDT 24 Jul 29 04:33:16 PM PDT 24 211597386 ps
T873 /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3694211817 Jul 29 04:33:17 PM PDT 24 Jul 29 04:33:18 PM PDT 24 198998504 ps
T874 /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.1312647888 Jul 29 04:33:30 PM PDT 24 Jul 29 04:33:31 PM PDT 24 75373622 ps
T875 /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3975634778 Jul 29 04:33:08 PM PDT 24 Jul 29 04:33:09 PM PDT 24 262889924 ps
T876 /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2554822204 Jul 29 04:33:26 PM PDT 24 Jul 29 04:33:27 PM PDT 24 42955090 ps
T877 /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3072345881 Jul 29 04:33:31 PM PDT 24 Jul 29 04:33:32 PM PDT 24 50754770 ps
T878 /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.542335116 Jul 29 04:33:26 PM PDT 24 Jul 29 04:33:27 PM PDT 24 67409573 ps
T879 /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2509343731 Jul 29 04:33:15 PM PDT 24 Jul 29 04:33:16 PM PDT 24 33642496 ps
T880 /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.512227859 Jul 29 04:33:27 PM PDT 24 Jul 29 04:33:28 PM PDT 24 402648522 ps
T881 /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.646118837 Jul 29 04:20:51 PM PDT 24 Jul 29 04:20:52 PM PDT 24 178933761 ps
T882 /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2703899327 Jul 29 04:33:19 PM PDT 24 Jul 29 04:33:20 PM PDT 24 302436095 ps
T883 /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.3077112703 Jul 29 04:33:12 PM PDT 24 Jul 29 04:33:14 PM PDT 24 50019389 ps
T884 /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.64290465 Jul 29 04:33:17 PM PDT 24 Jul 29 04:33:18 PM PDT 24 68192614 ps
T885 /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.66971512 Jul 29 04:33:31 PM PDT 24 Jul 29 04:33:33 PM PDT 24 226593072 ps
T886 /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.2879826461 Jul 29 04:33:16 PM PDT 24 Jul 29 04:33:17 PM PDT 24 175662042 ps
T887 /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.423674802 Jul 29 04:33:25 PM PDT 24 Jul 29 04:33:26 PM PDT 24 166894792 ps
T888 /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2999906385 Jul 29 04:33:22 PM PDT 24 Jul 29 04:33:24 PM PDT 24 191693959 ps
T889 /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2398460424 Jul 29 04:33:30 PM PDT 24 Jul 29 04:33:32 PM PDT 24 62915608 ps
T890 /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.3968884737 Jul 29 04:33:21 PM PDT 24 Jul 29 04:33:22 PM PDT 24 409715564 ps
T891 /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.1468599234 Jul 29 04:33:25 PM PDT 24 Jul 29 04:33:26 PM PDT 24 40165998 ps
T892 /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2297632914 Jul 29 04:33:21 PM PDT 24 Jul 29 04:33:22 PM PDT 24 43296683 ps
T893 /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.3825821656 Jul 29 04:33:31 PM PDT 24 Jul 29 04:33:32 PM PDT 24 29985960 ps
T894 /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1502385135 Jul 29 04:33:21 PM PDT 24 Jul 29 04:33:23 PM PDT 24 55632059 ps
T895 /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3192296111 Jul 29 04:21:12 PM PDT 24 Jul 29 04:21:14 PM PDT 24 47837635 ps
T896 /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2371678561 Jul 29 04:33:18 PM PDT 24 Jul 29 04:33:19 PM PDT 24 215698297 ps
T897 /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2606745128 Jul 29 04:25:25 PM PDT 24 Jul 29 04:25:27 PM PDT 24 250657542 ps
T898 /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.3795018293 Jul 29 04:33:31 PM PDT 24 Jul 29 04:33:32 PM PDT 24 25915488 ps
T899 /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.3632156995 Jul 29 04:33:34 PM PDT 24 Jul 29 04:33:36 PM PDT 24 50508321 ps
T900 /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.670567006 Jul 29 04:33:28 PM PDT 24 Jul 29 04:33:30 PM PDT 24 64226374 ps
T901 /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.1479032160 Jul 29 04:33:42 PM PDT 24 Jul 29 04:33:44 PM PDT 24 68098631 ps
T902 /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.3879354581 Jul 29 04:33:19 PM PDT 24 Jul 29 04:33:20 PM PDT 24 82727757 ps
T903 /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.2392739369 Jul 29 04:33:20 PM PDT 24 Jul 29 04:33:21 PM PDT 24 80287514 ps
T904 /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.542087818 Jul 29 04:33:19 PM PDT 24 Jul 29 04:33:20 PM PDT 24 496612028 ps
T905 /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.2524822602 Jul 29 04:33:21 PM PDT 24 Jul 29 04:33:22 PM PDT 24 41775544 ps
T906 /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.3803420157 Jul 29 04:33:27 PM PDT 24 Jul 29 04:33:28 PM PDT 24 38054997 ps
T907 /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1286474282 Jul 29 04:33:19 PM PDT 24 Jul 29 04:33:20 PM PDT 24 50610105 ps
T908 /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.650735098 Jul 29 04:33:30 PM PDT 24 Jul 29 04:33:32 PM PDT 24 40557444 ps
T909 /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.177168295 Jul 29 04:33:14 PM PDT 24 Jul 29 04:33:15 PM PDT 24 42447700 ps
T910 /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2394274897 Jul 29 04:33:29 PM PDT 24 Jul 29 04:33:30 PM PDT 24 32693317 ps
T911 /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.1553622405 Jul 29 04:33:14 PM PDT 24 Jul 29 04:33:15 PM PDT 24 197812221 ps
T912 /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.353252986 Jul 29 04:33:19 PM PDT 24 Jul 29 04:33:21 PM PDT 24 70558184 ps
T913 /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.353054331 Jul 29 04:33:08 PM PDT 24 Jul 29 04:33:09 PM PDT 24 204403389 ps
T914 /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1703882481 Jul 29 04:33:18 PM PDT 24 Jul 29 04:33:20 PM PDT 24 42439324 ps
T915 /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.2514855771 Jul 29 04:33:21 PM PDT 24 Jul 29 04:33:23 PM PDT 24 382187424 ps
T916 /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3352196553 Jul 29 04:33:11 PM PDT 24 Jul 29 04:33:12 PM PDT 24 19083987 ps
T917 /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.1886070900 Jul 29 04:33:20 PM PDT 24 Jul 29 04:33:21 PM PDT 24 27466495 ps
T918 /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.2200643987 Jul 29 04:33:27 PM PDT 24 Jul 29 04:33:28 PM PDT 24 100208749 ps
T919 /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4277067116 Jul 29 04:33:29 PM PDT 24 Jul 29 04:33:30 PM PDT 24 61655642 ps
T920 /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1664050944 Jul 29 04:33:28 PM PDT 24 Jul 29 04:33:30 PM PDT 24 375154909 ps
T921 /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.943147781 Jul 29 04:33:10 PM PDT 24 Jul 29 04:33:11 PM PDT 24 89063737 ps
T922 /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4241840431 Jul 29 04:33:20 PM PDT 24 Jul 29 04:33:21 PM PDT 24 128915643 ps
T923 /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.775198370 Jul 29 04:33:20 PM PDT 24 Jul 29 04:33:21 PM PDT 24 28240789 ps
T924 /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.591310245 Jul 29 04:33:15 PM PDT 24 Jul 29 04:33:16 PM PDT 24 279536638 ps
T925 /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.35929646 Jul 29 04:21:07 PM PDT 24 Jul 29 04:21:08 PM PDT 24 61902524 ps
T926 /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1611558786 Jul 29 04:33:34 PM PDT 24 Jul 29 04:33:35 PM PDT 24 200480143 ps
T927 /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3682189690 Jul 29 04:33:33 PM PDT 24 Jul 29 04:33:34 PM PDT 24 14613881 ps
T928 /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.1608819182 Jul 29 04:22:33 PM PDT 24 Jul 29 04:22:34 PM PDT 24 24170280 ps
T929 /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.660753602 Jul 29 04:33:19 PM PDT 24 Jul 29 04:33:21 PM PDT 24 38241613 ps
T930 /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.3053439834 Jul 29 04:33:09 PM PDT 24 Jul 29 04:33:10 PM PDT 24 131787180 ps
T931 /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.263078096 Jul 29 04:33:46 PM PDT 24 Jul 29 04:33:47 PM PDT 24 686576245 ps
T932 /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.2048130226 Jul 29 04:33:20 PM PDT 24 Jul 29 04:33:22 PM PDT 24 90644050 ps
T933 /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.623261817 Jul 29 04:33:15 PM PDT 24 Jul 29 04:33:16 PM PDT 24 231750405 ps
T934 /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3355009375 Jul 29 04:21:15 PM PDT 24 Jul 29 04:21:17 PM PDT 24 74172976 ps
T935 /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2712483671 Jul 29 04:33:19 PM PDT 24 Jul 29 04:33:21 PM PDT 24 352655684 ps
T936 /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2301544516 Jul 29 04:33:20 PM PDT 24 Jul 29 04:33:21 PM PDT 24 225848729 ps
T937 /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3356578399 Jul 29 04:33:28 PM PDT 24 Jul 29 04:33:29 PM PDT 24 149035439 ps
T938 /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.2410410488 Jul 29 04:33:18 PM PDT 24 Jul 29 04:33:19 PM PDT 24 108596722 ps
T939 /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.3371821004 Jul 29 04:33:21 PM PDT 24 Jul 29 04:33:22 PM PDT 24 262902040 ps
T940 /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1288930393 Jul 29 04:33:19 PM PDT 24 Jul 29 04:33:20 PM PDT 24 63483189 ps
T941 /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.3743227770 Jul 29 04:33:28 PM PDT 24 Jul 29 04:33:29 PM PDT 24 46366354 ps
T942 /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.1103385985 Jul 29 04:33:14 PM PDT 24 Jul 29 04:33:15 PM PDT 24 158693638 ps
T943 /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.4196255130 Jul 29 04:21:25 PM PDT 24 Jul 29 04:21:26 PM PDT 24 536002383 ps
T944 /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1035621308 Jul 29 04:33:43 PM PDT 24 Jul 29 04:33:44 PM PDT 24 184363247 ps
T945 /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.1163450658 Jul 29 04:33:17 PM PDT 24 Jul 29 04:33:18 PM PDT 24 90926053 ps
T946 /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.3081437334 Jul 29 04:33:18 PM PDT 24 Jul 29 04:33:19 PM PDT 24 126361763 ps

Test location /workspace/coverage/default/15.gpio_full_random.3810678860
Short name T2
Test name
Test status
Simulation time 313939771 ps
CPU time 0.96 seconds
Started Jul 29 04:33:57 PM PDT 24
Finished Jul 29 04:33:58 PM PDT 24
Peak memory 198136 kb
Host smart-459164de-558c-4747-a633-88ab2459b128
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810678860 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_full_random.3810678860
Directory /workspace/15.gpio_full_random/latest

Test location /workspace/coverage/default/26.gpio_intr_with_filter_rand_intr_event.3983637438
Short name T33
Test name
Test status
Simulation time 1100826794 ps
CPU time 2.94 seconds
Started Jul 29 04:34:26 PM PDT 24
Finished Jul 29 04:34:29 PM PDT 24
Peak memory 198288 kb
Host smart-71724a24-9810-4da5-a88e-adeea81b5f1b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983637438 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 26.gpio_intr_with_filter_rand_intr_event.3983637438
Directory /workspace/26.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/40.gpio_stress_all_with_rand_reset.2742977308
Short name T35
Test name
Test status
Simulation time 30009589627 ps
CPU time 871.29 seconds
Started Jul 29 04:34:56 PM PDT 24
Finished Jul 29 04:49:27 PM PDT 24
Peak memory 198656 kb
Host smart-3578a267-b1ae-4e00-8176-bed232e5e12a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2742977308 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_stress_all_with_rand_reset.2742977308
Directory /workspace/40.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.gpio_sec_cm.3325286565
Short name T43
Test name
Test status
Simulation time 291661489 ps
CPU time 1.02 seconds
Started Jul 29 04:33:42 PM PDT 24
Finished Jul 29 04:33:43 PM PDT 24
Peak memory 215288 kb
Host smart-40cd2aff-fef4-4e5e-aa3e-912f4f4cd114
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325286565 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_sec_cm.3325286565
Directory /workspace/3.gpio_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_aliasing.1133558367
Short name T74
Test name
Test status
Simulation time 30919786 ps
CPU time 0.83 seconds
Started Jul 29 04:32:42 PM PDT 24
Finished Jul 29 04:32:43 PM PDT 24
Peak memory 196212 kb
Host smart-2b139d8e-9335-470c-9c5b-dce81721f949
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133558367 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
1.gpio_csr_aliasing.1133558367
Directory /workspace/1.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.3015429018
Short name T48
Test name
Test status
Simulation time 203875439 ps
CPU time 1.46 seconds
Started Jul 29 04:33:01 PM PDT 24
Finished Jul 29 04:33:03 PM PDT 24
Peak memory 198572 kb
Host smart-d7e36f6a-e098-4d8a-9336-78170bdb0ee2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015429018 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 11.gpio_tl_intg_err.3015429018
Directory /workspace/11.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/0.gpio_stress_all.2761258487
Short name T9
Test name
Test status
Simulation time 21833120582 ps
CPU time 118.95 seconds
Started Jul 29 04:33:26 PM PDT 24
Finished Jul 29 04:35:25 PM PDT 24
Peak memory 198492 kb
Host smart-d8513c8e-a2b9-4450-914e-0da179f4a876
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761258487 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.g
pio_stress_all.2761258487
Directory /workspace/0.gpio_stress_all/latest

Test location /workspace/coverage/default/14.gpio_alert_test.1289570508
Short name T221
Test name
Test status
Simulation time 20073549 ps
CPU time 0.59 seconds
Started Jul 29 04:34:03 PM PDT 24
Finished Jul 29 04:34:03 PM PDT 24
Peak memory 194300 kb
Host smart-31dd4800-b64f-4a61-a627-7da7d64b80a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289570508 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_alert_test.1289570508
Directory /workspace/14.gpio_alert_test/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_same_csr_outstanding.2064889232
Short name T87
Test name
Test status
Simulation time 584677729 ps
CPU time 0.81 seconds
Started Jul 29 04:32:59 PM PDT 24
Finished Jul 29 04:33:00 PM PDT 24
Peak memory 196712 kb
Host smart-0ac3d73e-d929-4323-bae8-6df15374c527
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064889232 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 12.gpio_same_csr_outstanding.2064889232
Directory /workspace/12.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.1249898123
Short name T41
Test name
Test status
Simulation time 464646645 ps
CPU time 1.45 seconds
Started Jul 29 04:32:49 PM PDT 24
Finished Jul 29 04:32:50 PM PDT 24
Peak memory 198512 kb
Host smart-1d3effe3-3467-4c04-bb0a-49940687da49
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249898123 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 3.gpio_tl_intg_err.1249898123
Directory /workspace/3.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.3309800123
Short name T806
Test name
Test status
Simulation time 17743813 ps
CPU time 0.68 seconds
Started Jul 29 04:24:47 PM PDT 24
Finished Jul 29 04:24:48 PM PDT 24
Peak memory 193832 kb
Host smart-f8588507-b022-4595-a4bc-8ae9121c1676
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309800123 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
0.gpio_csr_aliasing.3309800123
Directory /workspace/0.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.830793433
Short name T84
Test name
Test status
Simulation time 306797487 ps
CPU time 2.92 seconds
Started Jul 29 04:25:24 PM PDT 24
Finished Jul 29 04:25:27 PM PDT 24
Peak memory 196944 kb
Host smart-c46433d9-f877-43cc-80b7-fe7461c9b2b5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830793433 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_bit_bash.830793433
Directory /workspace/0.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.1402906955
Short name T75
Test name
Test status
Simulation time 24159168 ps
CPU time 0.69 seconds
Started Jul 29 04:25:02 PM PDT 24
Finished Jul 29 04:25:03 PM PDT 24
Peak memory 195540 kb
Host smart-fc95f713-0301-4ea1-b63d-5e1d7814cd55
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402906955 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_hw_reset.1402906955
Directory /workspace/0.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.3584250975
Short name T831
Test name
Test status
Simulation time 412742621 ps
CPU time 0.94 seconds
Started Jul 29 04:25:18 PM PDT 24
Finished Jul 29 04:25:19 PM PDT 24
Peak memory 198448 kb
Host smart-b618f3bd-63fd-4454-a1d5-4007e68b26c7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584250975 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_mem_rw_with_rand_reset.3584250975
Directory /workspace/0.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_rw.987625665
Short name T815
Test name
Test status
Simulation time 13596329 ps
CPU time 0.58 seconds
Started Jul 29 04:23:34 PM PDT 24
Finished Jul 29 04:23:34 PM PDT 24
Peak memory 194828 kb
Host smart-3a73f650-2b00-49fb-876c-76b97129e3fa
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987625665 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_
csr_rw.987625665
Directory /workspace/0.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_intr_test.1124504385
Short name T818
Test name
Test status
Simulation time 59846557 ps
CPU time 0.6 seconds
Started Jul 29 04:25:17 PM PDT 24
Finished Jul 29 04:25:18 PM PDT 24
Peak memory 194992 kb
Host smart-36526a24-28a8-4289-874c-b288567da7a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124504385 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_intr_test.1124504385
Directory /workspace/0.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.1306587905
Short name T90
Test name
Test status
Simulation time 12846848 ps
CPU time 0.66 seconds
Started Jul 29 04:23:23 PM PDT 24
Finished Jul 29 04:23:24 PM PDT 24
Peak memory 195760 kb
Host smart-64e236d4-8ff8-4a68-964f-6ab0984f4998
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306587905 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 0.gpio_same_csr_outstanding.1306587905
Directory /workspace/0.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_errors.3499210654
Short name T808
Test name
Test status
Simulation time 34539062 ps
CPU time 1.64 seconds
Started Jul 29 04:23:49 PM PDT 24
Finished Jul 29 04:23:51 PM PDT 24
Peak memory 198580 kb
Host smart-3d353482-e0b0-4a49-a5b3-4aefec08e97a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499210654 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_tl_errors.3499210654
Directory /workspace/0.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.2024241234
Short name T38
Test name
Test status
Simulation time 62989750 ps
CPU time 0.89 seconds
Started Jul 29 04:22:00 PM PDT 24
Finished Jul 29 04:22:01 PM PDT 24
Peak memory 197612 kb
Host smart-0d3d4ed2-e2aa-4007-8337-45f393e01625
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024241234 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 0.gpio_tl_intg_err.2024241234
Directory /workspace/0.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.1937751072
Short name T776
Test name
Test status
Simulation time 56942407 ps
CPU time 2.11 seconds
Started Jul 29 04:32:47 PM PDT 24
Finished Jul 29 04:32:50 PM PDT 24
Peak memory 198492 kb
Host smart-9e8e3648-d956-46ba-a24f-40bdda8d3c59
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937751072 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_bit_bash.1937751072
Directory /workspace/1.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_hw_reset.759013420
Short name T81
Test name
Test status
Simulation time 57325197 ps
CPU time 0.64 seconds
Started Jul 29 04:32:45 PM PDT 24
Finished Jul 29 04:32:46 PM PDT 24
Peak memory 195844 kb
Host smart-6b2d98c1-9130-47bc-9b7a-f3263f37900e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759013420 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_hw_reset.759013420
Directory /workspace/1.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.2462782865
Short name T774
Test name
Test status
Simulation time 43709302 ps
CPU time 1.1 seconds
Started Jul 29 04:32:46 PM PDT 24
Finished Jul 29 04:32:47 PM PDT 24
Peak memory 198632 kb
Host smart-213b260c-108a-4bdf-aaac-98abe5d71dfe
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462782865 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_mem_rw_with_rand_reset.2462782865
Directory /workspace/1.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_rw.4133309772
Short name T816
Test name
Test status
Simulation time 45417024 ps
CPU time 0.56 seconds
Started Jul 29 04:25:56 PM PDT 24
Finished Jul 29 04:25:57 PM PDT 24
Peak memory 194192 kb
Host smart-6a996f98-3bbd-4d33-b2d3-6f79a7eb957a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133309772 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio
_csr_rw.4133309772
Directory /workspace/1.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_intr_test.2869621601
Short name T844
Test name
Test status
Simulation time 15056803 ps
CPU time 0.59 seconds
Started Jul 29 04:32:49 PM PDT 24
Finished Jul 29 04:32:50 PM PDT 24
Peak memory 194924 kb
Host smart-1720142c-61ab-4a5c-89ed-819367d64b72
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869621601 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_intr_test.2869621601
Directory /workspace/1.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.48873687
Short name T792
Test name
Test status
Simulation time 19218466 ps
CPU time 0.65 seconds
Started Jul 29 04:32:43 PM PDT 24
Finished Jul 29 04:32:44 PM PDT 24
Peak memory 195448 kb
Host smart-ff6f2d56-8e38-42ca-b46f-9f9706e95cc2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48873687 -assert nopostproc +UVM_TESTNAME=gpio_base
_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.gpio_same_csr_outstanding.48873687
Directory /workspace/1.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_errors.3221256363
Short name T770
Test name
Test status
Simulation time 47226873 ps
CPU time 2.12 seconds
Started Jul 29 04:32:49 PM PDT 24
Finished Jul 29 04:32:51 PM PDT 24
Peak memory 198536 kb
Host smart-fc4a982b-7902-4ddb-9dc8-066be7c36db8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221256363 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_tl_errors.3221256363
Directory /workspace/1.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_intg_err.2077948976
Short name T814
Test name
Test status
Simulation time 922508011 ps
CPU time 1.3 seconds
Started Jul 29 04:32:48 PM PDT 24
Finished Jul 29 04:32:49 PM PDT 24
Peak memory 198620 kb
Host smart-3d3627b8-ace2-42bf-bedf-6442f1ba2c25
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077948976 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 1.gpio_tl_intg_err.2077948976
Directory /workspace/1.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_mem_rw_with_rand_reset.2889969725
Short name T758
Test name
Test status
Simulation time 26077815 ps
CPU time 0.76 seconds
Started Jul 29 04:32:59 PM PDT 24
Finished Jul 29 04:33:00 PM PDT 24
Peak memory 198480 kb
Host smart-5c86379a-2ef7-46da-b5ab-3c3d61440f29
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889969725 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_csr_mem_rw_with_rand_reset.2889969725
Directory /workspace/10.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_rw.3517604440
Short name T82
Test name
Test status
Simulation time 129220825 ps
CPU time 0.6 seconds
Started Jul 29 04:32:59 PM PDT 24
Finished Jul 29 04:33:00 PM PDT 24
Peak memory 195012 kb
Host smart-6a7df449-b154-4465-a9ae-e6728f160a7d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517604440 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpi
o_csr_rw.3517604440
Directory /workspace/10.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_intr_test.2171550227
Short name T823
Test name
Test status
Simulation time 14131476 ps
CPU time 0.58 seconds
Started Jul 29 04:33:09 PM PDT 24
Finished Jul 29 04:33:10 PM PDT 24
Peak memory 194328 kb
Host smart-09631020-e573-4521-a41d-9b83360fe86b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171550227 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_intr_test.2171550227
Directory /workspace/10.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.563174277
Short name T800
Test name
Test status
Simulation time 30515157 ps
CPU time 0.76 seconds
Started Jul 29 04:33:01 PM PDT 24
Finished Jul 29 04:33:02 PM PDT 24
Peak memory 196604 kb
Host smart-a964faa2-fae8-4f28-8103-3ced4902302e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563174277 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 10.gpio_same_csr_outstanding.563174277
Directory /workspace/10.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_errors.2974687379
Short name T736
Test name
Test status
Simulation time 197789195 ps
CPU time 2.68 seconds
Started Jul 29 04:33:02 PM PDT 24
Finished Jul 29 04:33:05 PM PDT 24
Peak memory 198704 kb
Host smart-3a428a33-3cbe-4514-8775-96e4f8a6fe19
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974687379 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_tl_errors.2974687379
Directory /workspace/10.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.1146991743
Short name T830
Test name
Test status
Simulation time 69278349 ps
CPU time 1.16 seconds
Started Jul 29 04:33:00 PM PDT 24
Finished Jul 29 04:33:01 PM PDT 24
Peak memory 198644 kb
Host smart-bf8cd5b1-3ce5-431a-ad1a-f1e4ed091772
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146991743 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 10.gpio_tl_intg_err.1146991743
Directory /workspace/10.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_mem_rw_with_rand_reset.689712354
Short name T765
Test name
Test status
Simulation time 21286335 ps
CPU time 0.73 seconds
Started Jul 29 04:33:01 PM PDT 24
Finished Jul 29 04:33:02 PM PDT 24
Peak memory 197868 kb
Host smart-42ead900-f82c-40cc-bd02-ec534178c122
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689712354 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_csr_mem_rw_with_rand_reset.689712354
Directory /workspace/11.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_rw.1533627408
Short name T77
Test name
Test status
Simulation time 49339193 ps
CPU time 0.62 seconds
Started Jul 29 04:32:59 PM PDT 24
Finished Jul 29 04:33:00 PM PDT 24
Peak memory 195852 kb
Host smart-4488a169-fe1c-43ff-b8b3-dd797911247d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533627408 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpi
o_csr_rw.1533627408
Directory /workspace/11.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_intr_test.773761564
Short name T750
Test name
Test status
Simulation time 45998348 ps
CPU time 0.66 seconds
Started Jul 29 04:33:00 PM PDT 24
Finished Jul 29 04:33:01 PM PDT 24
Peak memory 194336 kb
Host smart-86d00775-266d-4886-8d59-502e74f842cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773761564 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_intr_test.773761564
Directory /workspace/11.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_same_csr_outstanding.3178569302
Short name T838
Test name
Test status
Simulation time 76668562 ps
CPU time 0.88 seconds
Started Jul 29 04:33:01 PM PDT 24
Finished Jul 29 04:33:02 PM PDT 24
Peak memory 196556 kb
Host smart-0507fc14-344a-4e68-a364-0122519ff3f6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178569302 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 11.gpio_same_csr_outstanding.3178569302
Directory /workspace/11.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_errors.3812406030
Short name T839
Test name
Test status
Simulation time 299168019 ps
CPU time 2.71 seconds
Started Jul 29 04:32:58 PM PDT 24
Finished Jul 29 04:33:01 PM PDT 24
Peak memory 198628 kb
Host smart-b3d5ad9a-7dd5-47f6-8579-a46be012e91e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812406030 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_tl_errors.3812406030
Directory /workspace/11.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.2080805327
Short name T734
Test name
Test status
Simulation time 43153800 ps
CPU time 1 seconds
Started Jul 29 04:32:59 PM PDT 24
Finished Jul 29 04:33:00 PM PDT 24
Peak memory 198404 kb
Host smart-023d605a-6cfb-4d64-924d-b239c8cc9997
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080805327 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_csr_mem_rw_with_rand_reset.2080805327
Directory /workspace/12.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_rw.2970174621
Short name T793
Test name
Test status
Simulation time 17169618 ps
CPU time 0.67 seconds
Started Jul 29 04:33:00 PM PDT 24
Finished Jul 29 04:33:01 PM PDT 24
Peak memory 196172 kb
Host smart-a338e4f8-ec83-426c-aefc-a95a05796069
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970174621 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpi
o_csr_rw.2970174621
Directory /workspace/12.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_intr_test.188092590
Short name T787
Test name
Test status
Simulation time 38243096 ps
CPU time 0.58 seconds
Started Jul 29 04:33:12 PM PDT 24
Finished Jul 29 04:33:13 PM PDT 24
Peak memory 194012 kb
Host smart-b54e2076-a7a0-4306-9f85-6965161b285b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188092590 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_intr_test.188092590
Directory /workspace/12.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_errors.1390623036
Short name T738
Test name
Test status
Simulation time 240699583 ps
CPU time 2.01 seconds
Started Jul 29 04:32:59 PM PDT 24
Finished Jul 29 04:33:01 PM PDT 24
Peak memory 198596 kb
Host smart-f2d171d5-940a-406a-90e1-d21c340a3a39
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390623036 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_tl_errors.1390623036
Directory /workspace/12.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.3014871465
Short name T783
Test name
Test status
Simulation time 556025146 ps
CPU time 1.38 seconds
Started Jul 29 04:32:59 PM PDT 24
Finished Jul 29 04:33:00 PM PDT 24
Peak memory 198556 kb
Host smart-fefb611d-7d1b-4f0e-9d80-bb08d6a2eb45
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014871465 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 12.gpio_tl_intg_err.3014871465
Directory /workspace/12.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.53177567
Short name T773
Test name
Test status
Simulation time 27055957 ps
CPU time 1.25 seconds
Started Jul 29 04:33:04 PM PDT 24
Finished Jul 29 04:33:05 PM PDT 24
Peak memory 198660 kb
Host smart-2acfa82d-eead-450e-b10f-6a27b7e641ba
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53177567 -assert
nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_csr_mem_rw_with_rand_reset.53177567
Directory /workspace/13.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_rw.194353579
Short name T104
Test name
Test status
Simulation time 56100189 ps
CPU time 0.56 seconds
Started Jul 29 04:33:05 PM PDT 24
Finished Jul 29 04:33:06 PM PDT 24
Peak memory 195092 kb
Host smart-07def5f7-9979-4125-965e-e048745cb9f6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194353579 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio
_csr_rw.194353579
Directory /workspace/13.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_intr_test.4145242119
Short name T756
Test name
Test status
Simulation time 36349953 ps
CPU time 0.56 seconds
Started Jul 29 04:33:09 PM PDT 24
Finished Jul 29 04:33:09 PM PDT 24
Peak memory 194236 kb
Host smart-782e8c4b-4aa8-4c7f-b823-600a126b284c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145242119 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_intr_test.4145242119
Directory /workspace/13.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.3421599419
Short name T92
Test name
Test status
Simulation time 22246847 ps
CPU time 0.65 seconds
Started Jul 29 04:33:01 PM PDT 24
Finished Jul 29 04:33:02 PM PDT 24
Peak memory 195416 kb
Host smart-6b181930-08b2-4bda-b039-dd937900b35c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421599419 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 13.gpio_same_csr_outstanding.3421599419
Directory /workspace/13.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_errors.456781890
Short name T759
Test name
Test status
Simulation time 328132687 ps
CPU time 1.76 seconds
Started Jul 29 04:33:05 PM PDT 24
Finished Jul 29 04:33:07 PM PDT 24
Peak memory 198832 kb
Host smart-7a7b7bd1-394c-4be1-a33f-cef8c1918b76
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456781890 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_tl_errors.456781890
Directory /workspace/13.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_intg_err.1301103901
Short name T794
Test name
Test status
Simulation time 81608530 ps
CPU time 1.2 seconds
Started Jul 29 04:33:03 PM PDT 24
Finished Jul 29 04:33:04 PM PDT 24
Peak memory 198580 kb
Host smart-7fc8e43b-5ffe-4228-bff0-152939369d88
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301103901 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 13.gpio_tl_intg_err.1301103901
Directory /workspace/13.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.4292492603
Short name T835
Test name
Test status
Simulation time 150768276 ps
CPU time 1.69 seconds
Started Jul 29 04:33:05 PM PDT 24
Finished Jul 29 04:33:06 PM PDT 24
Peak memory 198632 kb
Host smart-5db1edd8-27a6-47e3-83b0-a339a945deb0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292492603 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_csr_mem_rw_with_rand_reset.4292492603
Directory /workspace/14.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_rw.239229187
Short name T824
Test name
Test status
Simulation time 15222773 ps
CPU time 0.64 seconds
Started Jul 29 04:33:03 PM PDT 24
Finished Jul 29 04:33:03 PM PDT 24
Peak memory 195456 kb
Host smart-662e56f4-b410-48c8-a228-a6e9208a6204
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239229187 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio
_csr_rw.239229187
Directory /workspace/14.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_intr_test.1983668879
Short name T762
Test name
Test status
Simulation time 92557326 ps
CPU time 0.6 seconds
Started Jul 29 04:33:11 PM PDT 24
Finished Jul 29 04:33:12 PM PDT 24
Peak memory 194300 kb
Host smart-1074cfc9-6e58-467f-b082-411b6deb79d7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983668879 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_intr_test.1983668879
Directory /workspace/14.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_same_csr_outstanding.3539219099
Short name T91
Test name
Test status
Simulation time 19508418 ps
CPU time 0.66 seconds
Started Jul 29 04:33:06 PM PDT 24
Finished Jul 29 04:33:07 PM PDT 24
Peak memory 196236 kb
Host smart-06e10299-60f4-4d0d-bbf5-5141a586fce3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539219099 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 14.gpio_same_csr_outstanding.3539219099
Directory /workspace/14.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_errors.3832506498
Short name T769
Test name
Test status
Simulation time 635345205 ps
CPU time 2.33 seconds
Started Jul 29 04:33:12 PM PDT 24
Finished Jul 29 04:33:14 PM PDT 24
Peak memory 198568 kb
Host smart-54b560ce-b50a-4185-b1ba-c751427ae7e1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832506498 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_tl_errors.3832506498
Directory /workspace/14.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_intg_err.1435791783
Short name T829
Test name
Test status
Simulation time 219040011 ps
CPU time 0.86 seconds
Started Jul 29 04:33:13 PM PDT 24
Finished Jul 29 04:33:14 PM PDT 24
Peak memory 197528 kb
Host smart-6427c373-be67-49b4-8233-ba8bd467aa21
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435791783 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 14.gpio_tl_intg_err.1435791783
Directory /workspace/14.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.2742426167
Short name T811
Test name
Test status
Simulation time 151172581 ps
CPU time 0.78 seconds
Started Jul 29 04:33:08 PM PDT 24
Finished Jul 29 04:33:08 PM PDT 24
Peak memory 198380 kb
Host smart-a8f62ec6-db95-40a4-a55c-631ffd3ba3ee
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742426167 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_csr_mem_rw_with_rand_reset.2742426167
Directory /workspace/15.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_rw.3813897291
Short name T105
Test name
Test status
Simulation time 44270769 ps
CPU time 0.6 seconds
Started Jul 29 04:33:07 PM PDT 24
Finished Jul 29 04:33:08 PM PDT 24
Peak memory 195108 kb
Host smart-b9db6f1c-2276-4a7d-a734-4b6bb3870deb
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813897291 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpi
o_csr_rw.3813897291
Directory /workspace/15.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_intr_test.3267331894
Short name T764
Test name
Test status
Simulation time 52234415 ps
CPU time 0.61 seconds
Started Jul 29 04:33:04 PM PDT 24
Finished Jul 29 04:33:05 PM PDT 24
Peak memory 195004 kb
Host smart-86874fc6-4fde-4b1d-8ea6-ebab2cfed4d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267331894 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_intr_test.3267331894
Directory /workspace/15.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.2428990691
Short name T89
Test name
Test status
Simulation time 39823361 ps
CPU time 0.69 seconds
Started Jul 29 04:33:03 PM PDT 24
Finished Jul 29 04:33:04 PM PDT 24
Peak memory 195136 kb
Host smart-113b2509-ec44-4d37-bc81-531f22236251
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428990691 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 15.gpio_same_csr_outstanding.2428990691
Directory /workspace/15.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_errors.2428528292
Short name T846
Test name
Test status
Simulation time 185447880 ps
CPU time 2.47 seconds
Started Jul 29 04:33:08 PM PDT 24
Finished Jul 29 04:33:10 PM PDT 24
Peak memory 198592 kb
Host smart-5544ec1a-3c49-45e4-9a6c-2a40243a2fff
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428528292 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_tl_errors.2428528292
Directory /workspace/15.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.880446699
Short name T50
Test name
Test status
Simulation time 189489370 ps
CPU time 1.13 seconds
Started Jul 29 04:33:05 PM PDT 24
Finished Jul 29 04:33:06 PM PDT 24
Peak memory 198688 kb
Host smart-9b0cbcb4-8a28-4e4d-887e-a81586647c1b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880446699 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 15.gpio_tl_intg_err.880446699
Directory /workspace/15.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.2431767632
Short name T781
Test name
Test status
Simulation time 58785732 ps
CPU time 0.91 seconds
Started Jul 29 04:33:10 PM PDT 24
Finished Jul 29 04:33:11 PM PDT 24
Peak memory 198416 kb
Host smart-57e24079-d4bd-4fe1-8573-c552a4a5115d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431767632 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_csr_mem_rw_with_rand_reset.2431767632
Directory /workspace/16.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_rw.1928816783
Short name T799
Test name
Test status
Simulation time 41808148 ps
CPU time 0.6 seconds
Started Jul 29 04:33:04 PM PDT 24
Finished Jul 29 04:33:05 PM PDT 24
Peak memory 195068 kb
Host smart-cd50d011-850a-4623-9ec8-e7b645c8da14
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928816783 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpi
o_csr_rw.1928816783
Directory /workspace/16.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_intr_test.1598365725
Short name T735
Test name
Test status
Simulation time 41962200 ps
CPU time 0.59 seconds
Started Jul 29 04:33:07 PM PDT 24
Finished Jul 29 04:33:08 PM PDT 24
Peak memory 194408 kb
Host smart-315dd80e-c6ab-4656-9ad9-37e10399e132
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598365725 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_intr_test.1598365725
Directory /workspace/16.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.1984967515
Short name T832
Test name
Test status
Simulation time 383074912 ps
CPU time 0.65 seconds
Started Jul 29 04:33:08 PM PDT 24
Finished Jul 29 04:33:18 PM PDT 24
Peak memory 195432 kb
Host smart-5fc9a9c2-7532-43f9-a9f6-bec0f94067ad
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984967515 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 16.gpio_same_csr_outstanding.1984967515
Directory /workspace/16.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_errors.1970350777
Short name T842
Test name
Test status
Simulation time 35907995 ps
CPU time 2.09 seconds
Started Jul 29 04:33:07 PM PDT 24
Finished Jul 29 04:33:10 PM PDT 24
Peak memory 198568 kb
Host smart-346a9efa-e977-4664-9896-2958e8ec91e1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970350777 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_tl_errors.1970350777
Directory /workspace/16.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_intg_err.539339086
Short name T39
Test name
Test status
Simulation time 42258560 ps
CPU time 0.89 seconds
Started Jul 29 04:33:03 PM PDT 24
Finished Jul 29 04:33:04 PM PDT 24
Peak memory 198372 kb
Host smart-a212fd85-e50d-469b-8f75-e6c382d85608
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539339086 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 16.gpio_tl_intg_err.539339086
Directory /workspace/16.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.3717631559
Short name T790
Test name
Test status
Simulation time 34647198 ps
CPU time 0.95 seconds
Started Jul 29 04:33:05 PM PDT 24
Finished Jul 29 04:33:06 PM PDT 24
Peak memory 198340 kb
Host smart-428406ff-c1ac-4c18-a554-d7dd21172c56
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717631559 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_csr_mem_rw_with_rand_reset.3717631559
Directory /workspace/17.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_rw.143881308
Short name T813
Test name
Test status
Simulation time 12102745 ps
CPU time 0.58 seconds
Started Jul 29 04:33:09 PM PDT 24
Finished Jul 29 04:33:10 PM PDT 24
Peak memory 195192 kb
Host smart-5027dae5-8e00-48c5-8237-0a873928f00b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143881308 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio
_csr_rw.143881308
Directory /workspace/17.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_intr_test.4070889900
Short name T755
Test name
Test status
Simulation time 19541770 ps
CPU time 0.63 seconds
Started Jul 29 04:33:08 PM PDT 24
Finished Jul 29 04:33:09 PM PDT 24
Peak memory 194320 kb
Host smart-7f492079-3a52-4dd9-bd00-7df9bbd0f643
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070889900 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_intr_test.4070889900
Directory /workspace/17.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.2785716021
Short name T822
Test name
Test status
Simulation time 20165483 ps
CPU time 0.66 seconds
Started Jul 29 04:33:02 PM PDT 24
Finished Jul 29 04:33:03 PM PDT 24
Peak memory 195832 kb
Host smart-41b036c6-7c0c-4ac9-9494-cc8a4b14ad9e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785716021 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 17.gpio_same_csr_outstanding.2785716021
Directory /workspace/17.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_errors.2969287452
Short name T804
Test name
Test status
Simulation time 144126261 ps
CPU time 2.45 seconds
Started Jul 29 04:33:04 PM PDT 24
Finished Jul 29 04:33:06 PM PDT 24
Peak memory 198668 kb
Host smart-5b1ec655-f5a8-49e7-a5b0-65d48b7ce5ef
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969287452 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_tl_errors.2969287452
Directory /workspace/17.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.415746610
Short name T809
Test name
Test status
Simulation time 254530461 ps
CPU time 1.11 seconds
Started Jul 29 04:33:07 PM PDT 24
Finished Jul 29 04:33:08 PM PDT 24
Peak memory 198584 kb
Host smart-aca81c3b-d6f0-4164-a823-212f5d665b21
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415746610 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 17.gpio_tl_intg_err.415746610
Directory /workspace/17.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_mem_rw_with_rand_reset.1165073676
Short name T730
Test name
Test status
Simulation time 54333408 ps
CPU time 0.83 seconds
Started Jul 29 04:33:08 PM PDT 24
Finished Jul 29 04:33:09 PM PDT 24
Peak memory 198444 kb
Host smart-7c09f93b-ee19-4a51-b3a0-0d85b6a0ba41
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165073676 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_csr_mem_rw_with_rand_reset.1165073676
Directory /workspace/18.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_rw.184858228
Short name T70
Test name
Test status
Simulation time 11269841 ps
CPU time 0.59 seconds
Started Jul 29 04:33:05 PM PDT 24
Finished Jul 29 04:33:06 PM PDT 24
Peak memory 194404 kb
Host smart-2a356883-4ba0-4cac-8e50-b0a8cf957498
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184858228 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio
_csr_rw.184858228
Directory /workspace/18.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_intr_test.2579868362
Short name T723
Test name
Test status
Simulation time 31287216 ps
CPU time 0.61 seconds
Started Jul 29 04:33:11 PM PDT 24
Finished Jul 29 04:33:12 PM PDT 24
Peak memory 194372 kb
Host smart-b61dd92a-08c5-4e4b-a4fe-74df50932df4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579868362 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_intr_test.2579868362
Directory /workspace/18.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.118185652
Short name T837
Test name
Test status
Simulation time 22252500 ps
CPU time 0.83 seconds
Started Jul 29 04:33:08 PM PDT 24
Finished Jul 29 04:33:09 PM PDT 24
Peak memory 197752 kb
Host smart-0860e733-a353-4cf3-af7d-4dc95311c1a5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118185652 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 18.gpio_same_csr_outstanding.118185652
Directory /workspace/18.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_errors.1915753742
Short name T746
Test name
Test status
Simulation time 87069905 ps
CPU time 1.96 seconds
Started Jul 29 04:33:07 PM PDT 24
Finished Jul 29 04:33:09 PM PDT 24
Peak memory 198564 kb
Host smart-bd8bef89-144b-40dd-b811-a159dc53652a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915753742 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_tl_errors.1915753742
Directory /workspace/18.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.2430551388
Short name T46
Test name
Test status
Simulation time 483550290 ps
CPU time 1.37 seconds
Started Jul 29 04:33:03 PM PDT 24
Finished Jul 29 04:33:05 PM PDT 24
Peak memory 198524 kb
Host smart-a15b01f4-bf95-4a48-9692-bceaf6042c9b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430551388 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 18.gpio_tl_intg_err.2430551388
Directory /workspace/18.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.2289713964
Short name T732
Test name
Test status
Simulation time 116885853 ps
CPU time 0.69 seconds
Started Jul 29 04:33:05 PM PDT 24
Finished Jul 29 04:33:06 PM PDT 24
Peak memory 198056 kb
Host smart-18fa8839-a2a2-4c72-9791-d855603f7095
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289713964 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_csr_mem_rw_with_rand_reset.2289713964
Directory /workspace/19.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_rw.2619615918
Short name T83
Test name
Test status
Simulation time 15081957 ps
CPU time 0.63 seconds
Started Jul 29 04:33:07 PM PDT 24
Finished Jul 29 04:33:07 PM PDT 24
Peak memory 195572 kb
Host smart-e1a069f9-d638-4c59-b9bf-573332bd404c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619615918 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpi
o_csr_rw.2619615918
Directory /workspace/19.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_intr_test.1218038073
Short name T725
Test name
Test status
Simulation time 108930706 ps
CPU time 0.59 seconds
Started Jul 29 04:33:12 PM PDT 24
Finished Jul 29 04:33:12 PM PDT 24
Peak memory 194300 kb
Host smart-a0ef7adb-229b-4bb3-a6a5-14bf92142b16
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218038073 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_intr_test.1218038073
Directory /workspace/19.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.3522125425
Short name T785
Test name
Test status
Simulation time 59760715 ps
CPU time 0.74 seconds
Started Jul 29 04:33:04 PM PDT 24
Finished Jul 29 04:33:05 PM PDT 24
Peak memory 196652 kb
Host smart-589b63c2-63fb-4d93-9065-b7a6ce49a265
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522125425 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 19.gpio_same_csr_outstanding.3522125425
Directory /workspace/19.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_errors.804020997
Short name T791
Test name
Test status
Simulation time 28173643 ps
CPU time 1.43 seconds
Started Jul 29 04:33:08 PM PDT 24
Finished Jul 29 04:33:10 PM PDT 24
Peak memory 198632 kb
Host smart-f7943254-6ed7-46ca-a9c6-48f662e0c461
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804020997 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_tl_errors.804020997
Directory /workspace/19.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.1886221455
Short name T40
Test name
Test status
Simulation time 53880374 ps
CPU time 0.91 seconds
Started Jul 29 04:33:06 PM PDT 24
Finished Jul 29 04:33:07 PM PDT 24
Peak memory 198540 kb
Host smart-b51addbf-20c2-48a4-b960-0386e160ccd8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886221455 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 19.gpio_tl_intg_err.1886221455
Directory /workspace/19.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.2734170434
Short name T737
Test name
Test status
Simulation time 80264242 ps
CPU time 0.74 seconds
Started Jul 29 04:32:48 PM PDT 24
Finished Jul 29 04:32:49 PM PDT 24
Peak memory 196604 kb
Host smart-2f7c0b4c-deb7-430c-8e79-cffe6a86a671
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734170434 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
2.gpio_csr_aliasing.2734170434
Directory /workspace/2.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.1995997858
Short name T788
Test name
Test status
Simulation time 715445227 ps
CPU time 2.29 seconds
Started Jul 29 04:32:50 PM PDT 24
Finished Jul 29 04:32:52 PM PDT 24
Peak memory 197168 kb
Host smart-3e24b473-9cdc-4fae-87f3-b2ddef745290
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995997858 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_bit_bash.1995997858
Directory /workspace/2.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_hw_reset.1950351765
Short name T79
Test name
Test status
Simulation time 71883617 ps
CPU time 0.69 seconds
Started Jul 29 04:32:47 PM PDT 24
Finished Jul 29 04:32:48 PM PDT 24
Peak memory 195476 kb
Host smart-0e5aa673-5125-45c3-a4de-8df4f5b50cf6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950351765 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_hw_reset.1950351765
Directory /workspace/2.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.3770160539
Short name T843
Test name
Test status
Simulation time 103283834 ps
CPU time 1.4 seconds
Started Jul 29 04:32:47 PM PDT 24
Finished Jul 29 04:32:48 PM PDT 24
Peak memory 198620 kb
Host smart-7b8be5d9-0035-4f25-92af-3eb314af6c3d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770160539 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_mem_rw_with_rand_reset.3770160539
Directory /workspace/2.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_rw.3667516907
Short name T802
Test name
Test status
Simulation time 18334196 ps
CPU time 0.57 seconds
Started Jul 29 04:32:47 PM PDT 24
Finished Jul 29 04:32:47 PM PDT 24
Peak memory 193872 kb
Host smart-b45d0a36-a89a-42d1-b4fa-6adf7dd4cce9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667516907 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio
_csr_rw.3667516907
Directory /workspace/2.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_intr_test.1486069038
Short name T819
Test name
Test status
Simulation time 10725068 ps
CPU time 0.59 seconds
Started Jul 29 04:32:47 PM PDT 24
Finished Jul 29 04:32:47 PM PDT 24
Peak memory 194244 kb
Host smart-803002e1-515b-42b6-9bcf-5936e88d911d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486069038 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_intr_test.1486069038
Directory /workspace/2.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_same_csr_outstanding.2178408320
Short name T821
Test name
Test status
Simulation time 61551166 ps
CPU time 0.76 seconds
Started Jul 29 04:32:47 PM PDT 24
Finished Jul 29 04:32:48 PM PDT 24
Peak memory 196844 kb
Host smart-c2ad2d7b-47a3-407f-bdef-293af4c36712
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178408320 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 2.gpio_same_csr_outstanding.2178408320
Directory /workspace/2.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_errors.4194533962
Short name T747
Test name
Test status
Simulation time 437331517 ps
CPU time 2.55 seconds
Started Jul 29 04:32:50 PM PDT 24
Finished Jul 29 04:32:53 PM PDT 24
Peak memory 198596 kb
Host smart-a35823ac-1d68-499d-a0e8-acaf66b5b3a4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194533962 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_tl_errors.4194533962
Directory /workspace/2.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.3144589009
Short name T796
Test name
Test status
Simulation time 394716826 ps
CPU time 1.35 seconds
Started Jul 29 04:32:48 PM PDT 24
Finished Jul 29 04:32:50 PM PDT 24
Peak memory 198620 kb
Host smart-0bc39933-68d7-4f97-bf61-02ec9c74e2ee
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144589009 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 2.gpio_tl_intg_err.3144589009
Directory /workspace/2.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.gpio_intr_test.999327268
Short name T767
Test name
Test status
Simulation time 18318097 ps
CPU time 0.64 seconds
Started Jul 29 04:33:03 PM PDT 24
Finished Jul 29 04:33:04 PM PDT 24
Peak memory 194400 kb
Host smart-e8fe0bd7-080c-4aca-b7f4-cbc418922f67
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999327268 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.gpio_intr_test.999327268
Directory /workspace/20.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.gpio_intr_test.1588265966
Short name T826
Test name
Test status
Simulation time 11827403 ps
CPU time 0.6 seconds
Started Jul 29 04:33:07 PM PDT 24
Finished Jul 29 04:33:08 PM PDT 24
Peak memory 194284 kb
Host smart-fc722880-04d3-4dcb-9c21-bdb8a9c23659
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588265966 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.gpio_intr_test.1588265966
Directory /workspace/21.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.gpio_intr_test.3812172391
Short name T784
Test name
Test status
Simulation time 33948452 ps
CPU time 0.59 seconds
Started Jul 29 04:33:06 PM PDT 24
Finished Jul 29 04:33:07 PM PDT 24
Peak memory 194996 kb
Host smart-4c50e099-2e1c-4d29-945b-02e96677d132
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812172391 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.gpio_intr_test.3812172391
Directory /workspace/22.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.gpio_intr_test.708635123
Short name T733
Test name
Test status
Simulation time 11530843 ps
CPU time 0.67 seconds
Started Jul 29 04:33:09 PM PDT 24
Finished Jul 29 04:33:10 PM PDT 24
Peak memory 194296 kb
Host smart-d2f12a05-e096-4b61-8241-2fb6f1e13cf2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708635123 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.gpio_intr_test.708635123
Directory /workspace/23.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.gpio_intr_test.2823365482
Short name T780
Test name
Test status
Simulation time 56557218 ps
CPU time 0.61 seconds
Started Jul 29 04:33:09 PM PDT 24
Finished Jul 29 04:33:10 PM PDT 24
Peak memory 194440 kb
Host smart-f6664933-70b6-42a9-b4ec-71a07951287c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823365482 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.gpio_intr_test.2823365482
Directory /workspace/24.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.gpio_intr_test.1512937141
Short name T807
Test name
Test status
Simulation time 10914094 ps
CPU time 0.6 seconds
Started Jul 29 04:33:07 PM PDT 24
Finished Jul 29 04:33:08 PM PDT 24
Peak memory 194452 kb
Host smart-a7a40ee2-439b-4cf3-93e0-13c688a3c519
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512937141 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.gpio_intr_test.1512937141
Directory /workspace/25.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.gpio_intr_test.3455113979
Short name T731
Test name
Test status
Simulation time 22611185 ps
CPU time 0.59 seconds
Started Jul 29 04:33:12 PM PDT 24
Finished Jul 29 04:33:13 PM PDT 24
Peak memory 194384 kb
Host smart-4b604ce6-22ee-4d28-8d55-e82f7eedab4f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455113979 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.gpio_intr_test.3455113979
Directory /workspace/26.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.gpio_intr_test.2845935602
Short name T761
Test name
Test status
Simulation time 47205401 ps
CPU time 0.59 seconds
Started Jul 29 04:33:09 PM PDT 24
Finished Jul 29 04:33:09 PM PDT 24
Peak memory 194888 kb
Host smart-c23b2811-f3e9-4f5a-93cf-24840846ce4b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845935602 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.gpio_intr_test.2845935602
Directory /workspace/27.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.gpio_intr_test.1846002775
Short name T754
Test name
Test status
Simulation time 13748962 ps
CPU time 0.67 seconds
Started Jul 29 04:33:09 PM PDT 24
Finished Jul 29 04:33:10 PM PDT 24
Peak memory 194920 kb
Host smart-ba9c7722-a7e8-4b52-aa2d-9c729e405dab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846002775 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.gpio_intr_test.1846002775
Directory /workspace/28.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.gpio_intr_test.373355932
Short name T772
Test name
Test status
Simulation time 24911285 ps
CPU time 0.61 seconds
Started Jul 29 04:33:12 PM PDT 24
Finished Jul 29 04:33:13 PM PDT 24
Peak memory 194328 kb
Host smart-f0bf0b39-c8b1-448e-9a2e-887ae58be7bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373355932 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.gpio_intr_test.373355932
Directory /workspace/29.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.2374617965
Short name T76
Test name
Test status
Simulation time 46843542 ps
CPU time 0.8 seconds
Started Jul 29 04:32:46 PM PDT 24
Finished Jul 29 04:32:46 PM PDT 24
Peak memory 196308 kb
Host smart-b9dcb9b8-c348-4834-ab3d-1aec0f0d61e7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374617965 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
3.gpio_csr_aliasing.2374617965
Directory /workspace/3.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.4045728744
Short name T69
Test name
Test status
Simulation time 2443915984 ps
CPU time 3.35 seconds
Started Jul 29 04:32:51 PM PDT 24
Finished Jul 29 04:32:55 PM PDT 24
Peak memory 198088 kb
Host smart-8f0cb42d-8df1-47f0-b3bd-f9fd59ed8013
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045728744 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_bit_bash.4045728744
Directory /workspace/3.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.3135749583
Short name T740
Test name
Test status
Simulation time 27937769 ps
CPU time 0.69 seconds
Started Jul 29 04:32:55 PM PDT 24
Finished Jul 29 04:32:56 PM PDT 24
Peak memory 195132 kb
Host smart-b724c2a8-cd94-4af7-9ac3-38817a55b544
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135749583 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_hw_reset.3135749583
Directory /workspace/3.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.519220208
Short name T777
Test name
Test status
Simulation time 352597733 ps
CPU time 0.93 seconds
Started Jul 29 04:32:47 PM PDT 24
Finished Jul 29 04:32:48 PM PDT 24
Peak memory 198424 kb
Host smart-f6f7d941-7dac-428d-9c51-b2a49d6525dd
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519220208 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_mem_rw_with_rand_reset.519220208
Directory /workspace/3.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_rw.3958494673
Short name T80
Test name
Test status
Simulation time 24617498 ps
CPU time 0.61 seconds
Started Jul 29 04:32:48 PM PDT 24
Finished Jul 29 04:32:48 PM PDT 24
Peak memory 195136 kb
Host smart-b6d4fee5-62da-4e0a-8646-42beecbaa02f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958494673 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio
_csr_rw.3958494673
Directory /workspace/3.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_intr_test.1467182811
Short name T771
Test name
Test status
Simulation time 40402546 ps
CPU time 0.63 seconds
Started Jul 29 04:32:52 PM PDT 24
Finished Jul 29 04:32:53 PM PDT 24
Peak memory 194240 kb
Host smart-7297d8ad-1a4b-44c0-ba7a-df1d81b680f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467182811 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_intr_test.1467182811
Directory /workspace/3.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_same_csr_outstanding.4190862928
Short name T72
Test name
Test status
Simulation time 57684093 ps
CPU time 0.79 seconds
Started Jul 29 04:32:46 PM PDT 24
Finished Jul 29 04:32:47 PM PDT 24
Peak memory 197532 kb
Host smart-8385836d-5d34-4150-a1db-4ccd82072a95
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190862928 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 3.gpio_same_csr_outstanding.4190862928
Directory /workspace/3.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_errors.3185267487
Short name T743
Test name
Test status
Simulation time 597930781 ps
CPU time 2.51 seconds
Started Jul 29 04:32:52 PM PDT 24
Finished Jul 29 04:32:54 PM PDT 24
Peak memory 198540 kb
Host smart-25815c81-39bf-4ca1-8bd6-bd43847344b4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185267487 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_tl_errors.3185267487
Directory /workspace/3.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.gpio_intr_test.26136552
Short name T778
Test name
Test status
Simulation time 53162727 ps
CPU time 0.55 seconds
Started Jul 29 04:33:08 PM PDT 24
Finished Jul 29 04:33:09 PM PDT 24
Peak memory 194276 kb
Host smart-754201c4-a23a-48bf-a244-9da332955576
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26136552 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.gpio_intr_test.26136552
Directory /workspace/30.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.gpio_intr_test.4098669716
Short name T845
Test name
Test status
Simulation time 56676039 ps
CPU time 0.61 seconds
Started Jul 29 04:33:12 PM PDT 24
Finished Jul 29 04:33:12 PM PDT 24
Peak memory 194264 kb
Host smart-c4bf61a3-b222-4533-91a6-8affa9658223
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098669716 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.gpio_intr_test.4098669716
Directory /workspace/31.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.gpio_intr_test.2201505610
Short name T763
Test name
Test status
Simulation time 35018529 ps
CPU time 0.61 seconds
Started Jul 29 04:33:09 PM PDT 24
Finished Jul 29 04:33:09 PM PDT 24
Peak memory 194924 kb
Host smart-294a543f-3ec5-4193-b133-b7fe43f150cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201505610 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.gpio_intr_test.2201505610
Directory /workspace/32.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.gpio_intr_test.4012749554
Short name T722
Test name
Test status
Simulation time 26126245 ps
CPU time 0.56 seconds
Started Jul 29 04:33:09 PM PDT 24
Finished Jul 29 04:33:09 PM PDT 24
Peak memory 194852 kb
Host smart-0fbb6659-bcb9-4429-affd-9d5b0d3ba766
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012749554 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.gpio_intr_test.4012749554
Directory /workspace/33.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.gpio_intr_test.3048233504
Short name T742
Test name
Test status
Simulation time 66079730 ps
CPU time 0.56 seconds
Started Jul 29 04:33:11 PM PDT 24
Finished Jul 29 04:33:11 PM PDT 24
Peak memory 194220 kb
Host smart-d26d1617-b49c-4aa1-8e13-25522f29e7cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048233504 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.gpio_intr_test.3048233504
Directory /workspace/34.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.gpio_intr_test.2536047425
Short name T779
Test name
Test status
Simulation time 306318383 ps
CPU time 0.62 seconds
Started Jul 29 04:33:10 PM PDT 24
Finished Jul 29 04:33:11 PM PDT 24
Peak memory 194404 kb
Host smart-cc18dd5d-bff5-47cb-8ed4-fe01eeb1e08a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536047425 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.gpio_intr_test.2536047425
Directory /workspace/35.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.gpio_intr_test.2636640581
Short name T840
Test name
Test status
Simulation time 40068418 ps
CPU time 0.6 seconds
Started Jul 29 04:33:11 PM PDT 24
Finished Jul 29 04:33:11 PM PDT 24
Peak memory 194428 kb
Host smart-3204de08-6a78-400f-a529-327071a936e2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636640581 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.gpio_intr_test.2636640581
Directory /workspace/36.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.gpio_intr_test.2212159882
Short name T803
Test name
Test status
Simulation time 12693559 ps
CPU time 0.58 seconds
Started Jul 29 04:33:10 PM PDT 24
Finished Jul 29 04:33:11 PM PDT 24
Peak memory 194292 kb
Host smart-7b486292-0675-4331-8db0-5e8e0848f25c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212159882 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.gpio_intr_test.2212159882
Directory /workspace/37.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.gpio_intr_test.988203285
Short name T728
Test name
Test status
Simulation time 44401500 ps
CPU time 0.62 seconds
Started Jul 29 04:33:10 PM PDT 24
Finished Jul 29 04:33:10 PM PDT 24
Peak memory 194276 kb
Host smart-f52e0dc4-ece9-4cb9-b441-6d27e670bc31
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988203285 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.gpio_intr_test.988203285
Directory /workspace/38.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.gpio_intr_test.560717181
Short name T766
Test name
Test status
Simulation time 15930572 ps
CPU time 0.65 seconds
Started Jul 29 04:33:08 PM PDT 24
Finished Jul 29 04:33:09 PM PDT 24
Peak memory 194972 kb
Host smart-59346681-3dbd-44df-9f63-199e736dad25
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560717181 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.gpio_intr_test.560717181
Directory /workspace/39.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.2373953571
Short name T786
Test name
Test status
Simulation time 92899296 ps
CPU time 0.79 seconds
Started Jul 29 04:32:54 PM PDT 24
Finished Jul 29 04:32:55 PM PDT 24
Peak memory 197108 kb
Host smart-f9129eac-4fcc-4506-bcc0-e5a948eaa451
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373953571 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
4.gpio_csr_aliasing.2373953571
Directory /workspace/4.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_bit_bash.2965062494
Short name T782
Test name
Test status
Simulation time 1006825380 ps
CPU time 3.19 seconds
Started Jul 29 04:32:58 PM PDT 24
Finished Jul 29 04:33:01 PM PDT 24
Peak memory 197732 kb
Host smart-4630c3ce-1802-416b-9db9-18d98d0ee54f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965062494 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_bit_bash.2965062494
Directory /workspace/4.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.3975062883
Short name T78
Test name
Test status
Simulation time 35453477 ps
CPU time 0.68 seconds
Started Jul 29 04:32:53 PM PDT 24
Finished Jul 29 04:32:54 PM PDT 24
Peak memory 195424 kb
Host smart-f873da0e-c70e-4fc4-a37d-840e62175a4b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975062883 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_hw_reset.3975062883
Directory /workspace/4.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.1012505562
Short name T768
Test name
Test status
Simulation time 24308414 ps
CPU time 0.72 seconds
Started Jul 29 04:32:56 PM PDT 24
Finished Jul 29 04:32:57 PM PDT 24
Peak memory 198388 kb
Host smart-1eb6ec5d-e664-49ae-81a2-8e425656f5c6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012505562 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_mem_rw_with_rand_reset.1012505562
Directory /workspace/4.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_rw.906504729
Short name T71
Test name
Test status
Simulation time 56029343 ps
CPU time 0.62 seconds
Started Jul 29 04:32:59 PM PDT 24
Finished Jul 29 04:33:00 PM PDT 24
Peak memory 195464 kb
Host smart-610d60ef-5e36-47ea-b8e9-fdfdfc8ac044
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906504729 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_
csr_rw.906504729
Directory /workspace/4.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_intr_test.4157807458
Short name T833
Test name
Test status
Simulation time 49970305 ps
CPU time 0.59 seconds
Started Jul 29 04:32:52 PM PDT 24
Finished Jul 29 04:32:53 PM PDT 24
Peak memory 194376 kb
Host smart-0a9f560f-8bbb-444b-a43f-32596464c4ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157807458 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_intr_test.4157807458
Directory /workspace/4.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.4199139638
Short name T841
Test name
Test status
Simulation time 72272749 ps
CPU time 0.68 seconds
Started Jul 29 04:32:52 PM PDT 24
Finished Jul 29 04:32:53 PM PDT 24
Peak memory 195356 kb
Host smart-b2f864a1-245b-4597-a577-8784fe331f81
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199139638 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 4.gpio_same_csr_outstanding.4199139638
Directory /workspace/4.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_errors.152892350
Short name T745
Test name
Test status
Simulation time 85444371 ps
CPU time 1.35 seconds
Started Jul 29 04:32:53 PM PDT 24
Finished Jul 29 04:32:55 PM PDT 24
Peak memory 198624 kb
Host smart-0f073b26-30b2-4004-a7d6-011efdb83811
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152892350 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_tl_errors.152892350
Directory /workspace/4.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.2996071243
Short name T805
Test name
Test status
Simulation time 924411688 ps
CPU time 1.34 seconds
Started Jul 29 04:32:56 PM PDT 24
Finished Jul 29 04:32:58 PM PDT 24
Peak memory 198488 kb
Host smart-899b80d2-e48c-4224-987d-a4f0a3572023
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996071243 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 4.gpio_tl_intg_err.2996071243
Directory /workspace/4.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.gpio_intr_test.2400504799
Short name T827
Test name
Test status
Simulation time 12680949 ps
CPU time 0.57 seconds
Started Jul 29 04:33:09 PM PDT 24
Finished Jul 29 04:33:09 PM PDT 24
Peak memory 194228 kb
Host smart-7b783be2-d5a5-4bc6-b268-a013fa72a454
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400504799 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.gpio_intr_test.2400504799
Directory /workspace/40.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.gpio_intr_test.3380739183
Short name T775
Test name
Test status
Simulation time 42154320 ps
CPU time 0.64 seconds
Started Jul 29 04:33:08 PM PDT 24
Finished Jul 29 04:33:09 PM PDT 24
Peak memory 194296 kb
Host smart-5c79afcb-a6eb-4b4b-ac0a-19b79280c3c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380739183 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.gpio_intr_test.3380739183
Directory /workspace/41.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.gpio_intr_test.263187296
Short name T748
Test name
Test status
Simulation time 13062548 ps
CPU time 0.63 seconds
Started Jul 29 04:33:10 PM PDT 24
Finished Jul 29 04:33:11 PM PDT 24
Peak memory 194336 kb
Host smart-f2c24879-4f95-42b4-8090-7a8e20883ee6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263187296 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.gpio_intr_test.263187296
Directory /workspace/42.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.gpio_intr_test.534304991
Short name T739
Test name
Test status
Simulation time 20364802 ps
CPU time 0.63 seconds
Started Jul 29 04:33:10 PM PDT 24
Finished Jul 29 04:33:11 PM PDT 24
Peak memory 194284 kb
Host smart-1bc190bc-5b4f-4b0a-b0ea-ffc91a6fc690
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534304991 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.gpio_intr_test.534304991
Directory /workspace/43.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.gpio_intr_test.851460069
Short name T729
Test name
Test status
Simulation time 48364491 ps
CPU time 0.62 seconds
Started Jul 29 04:33:12 PM PDT 24
Finished Jul 29 04:33:13 PM PDT 24
Peak memory 194012 kb
Host smart-b2f23cd5-8d56-42b0-a38b-674f6507c8e8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851460069 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.gpio_intr_test.851460069
Directory /workspace/44.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.gpio_intr_test.1016649542
Short name T798
Test name
Test status
Simulation time 13696690 ps
CPU time 0.6 seconds
Started Jul 29 04:33:12 PM PDT 24
Finished Jul 29 04:33:13 PM PDT 24
Peak memory 194016 kb
Host smart-42f8a88e-b155-448f-b025-d0063c319377
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016649542 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.gpio_intr_test.1016649542
Directory /workspace/45.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.gpio_intr_test.2352209987
Short name T726
Test name
Test status
Simulation time 20002980 ps
CPU time 0.63 seconds
Started Jul 29 04:33:09 PM PDT 24
Finished Jul 29 04:33:10 PM PDT 24
Peak memory 194284 kb
Host smart-2214bddd-8bca-45d0-8c3b-cf381b93209a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352209987 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.gpio_intr_test.2352209987
Directory /workspace/46.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.gpio_intr_test.414136970
Short name T789
Test name
Test status
Simulation time 42489810 ps
CPU time 0.63 seconds
Started Jul 29 04:33:10 PM PDT 24
Finished Jul 29 04:33:11 PM PDT 24
Peak memory 194284 kb
Host smart-1c98d40d-1f29-4c81-9605-c5e46d6be10d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414136970 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.gpio_intr_test.414136970
Directory /workspace/47.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.gpio_intr_test.1389337433
Short name T749
Test name
Test status
Simulation time 33016284 ps
CPU time 0.61 seconds
Started Jul 29 04:33:08 PM PDT 24
Finished Jul 29 04:33:09 PM PDT 24
Peak memory 194988 kb
Host smart-674cb775-72bb-4185-af90-86b673357c48
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389337433 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.gpio_intr_test.1389337433
Directory /workspace/48.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.gpio_intr_test.4180958745
Short name T797
Test name
Test status
Simulation time 13138742 ps
CPU time 0.59 seconds
Started Jul 29 04:33:09 PM PDT 24
Finished Jul 29 04:33:10 PM PDT 24
Peak memory 194332 kb
Host smart-12117b6c-2a07-40a0-b282-99434df0dec3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180958745 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.gpio_intr_test.4180958745
Directory /workspace/49.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_mem_rw_with_rand_reset.1544685118
Short name T752
Test name
Test status
Simulation time 94494895 ps
CPU time 0.85 seconds
Started Jul 29 04:32:56 PM PDT 24
Finished Jul 29 04:32:57 PM PDT 24
Peak memory 198376 kb
Host smart-a325bb18-7a8f-455f-b0aa-22d2dc536c85
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544685118 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_csr_mem_rw_with_rand_reset.1544685118
Directory /workspace/5.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_rw.317928346
Short name T828
Test name
Test status
Simulation time 64748532 ps
CPU time 0.58 seconds
Started Jul 29 04:32:52 PM PDT 24
Finished Jul 29 04:32:52 PM PDT 24
Peak memory 193836 kb
Host smart-d315c3e5-9695-4b53-bdbd-f4e7bca3d165
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317928346 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_
csr_rw.317928346
Directory /workspace/5.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_intr_test.3635783862
Short name T757
Test name
Test status
Simulation time 19159591 ps
CPU time 0.64 seconds
Started Jul 29 04:32:52 PM PDT 24
Finished Jul 29 04:32:53 PM PDT 24
Peak memory 194312 kb
Host smart-c1e33d80-ea9c-4eb1-b329-73acf487bb75
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635783862 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_intr_test.3635783862
Directory /workspace/5.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.3481771967
Short name T86
Test name
Test status
Simulation time 191670172 ps
CPU time 0.71 seconds
Started Jul 29 04:32:54 PM PDT 24
Finished Jul 29 04:32:54 PM PDT 24
Peak memory 195400 kb
Host smart-68baec1e-70ac-4ab4-9c10-90df9ec96df5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481771967 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 5.gpio_same_csr_outstanding.3481771967
Directory /workspace/5.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_errors.3400805308
Short name T820
Test name
Test status
Simulation time 544652723 ps
CPU time 2.89 seconds
Started Jul 29 04:32:56 PM PDT 24
Finished Jul 29 04:32:59 PM PDT 24
Peak memory 198512 kb
Host smart-125c8261-f5f3-4d26-823d-79edfa090cbd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400805308 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_tl_errors.3400805308
Directory /workspace/5.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.3017081518
Short name T795
Test name
Test status
Simulation time 208902257 ps
CPU time 1.39 seconds
Started Jul 29 04:32:53 PM PDT 24
Finished Jul 29 04:32:55 PM PDT 24
Peak memory 198528 kb
Host smart-2888988e-746a-4e3f-b4d6-d32ed561021b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017081518 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 5.gpio_tl_intg_err.3017081518
Directory /workspace/5.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.1999748870
Short name T741
Test name
Test status
Simulation time 40326568 ps
CPU time 1.04 seconds
Started Jul 29 04:32:53 PM PDT 24
Finished Jul 29 04:32:54 PM PDT 24
Peak memory 198452 kb
Host smart-ebedf2d2-ad4f-4911-bb91-76d08a91d1f4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999748870 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_csr_mem_rw_with_rand_reset.1999748870
Directory /workspace/6.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_rw.1376406834
Short name T67
Test name
Test status
Simulation time 14220276 ps
CPU time 0.59 seconds
Started Jul 29 04:32:52 PM PDT 24
Finished Jul 29 04:32:53 PM PDT 24
Peak memory 194440 kb
Host smart-eb6b280e-e448-4473-98af-43d04903c1d2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376406834 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio
_csr_rw.1376406834
Directory /workspace/6.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_intr_test.3222711937
Short name T744
Test name
Test status
Simulation time 18311152 ps
CPU time 0.66 seconds
Started Jul 29 04:32:53 PM PDT 24
Finished Jul 29 04:32:54 PM PDT 24
Peak memory 194376 kb
Host smart-3052c688-4ee3-453b-9070-7383d960684d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222711937 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_intr_test.3222711937
Directory /workspace/6.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.3762722424
Short name T68
Test name
Test status
Simulation time 40020822 ps
CPU time 0.87 seconds
Started Jul 29 04:32:53 PM PDT 24
Finished Jul 29 04:32:54 PM PDT 24
Peak memory 196896 kb
Host smart-006fc47d-1077-45cf-a1b3-c73300631b45
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762722424 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 6.gpio_same_csr_outstanding.3762722424
Directory /workspace/6.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_errors.2322716465
Short name T812
Test name
Test status
Simulation time 126468966 ps
CPU time 2.44 seconds
Started Jul 29 04:32:52 PM PDT 24
Finished Jul 29 04:32:55 PM PDT 24
Peak memory 198536 kb
Host smart-1905a4b9-f1a6-47ac-86ad-98f2c77d211d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322716465 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_tl_errors.2322716465
Directory /workspace/6.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.2710067699
Short name T49
Test name
Test status
Simulation time 198445338 ps
CPU time 1.4 seconds
Started Jul 29 04:33:00 PM PDT 24
Finished Jul 29 04:33:01 PM PDT 24
Peak memory 198628 kb
Host smart-e98145b1-ff1a-4750-8b9e-d17eb4811da5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710067699 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 6.gpio_tl_intg_err.2710067699
Directory /workspace/6.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.572822700
Short name T760
Test name
Test status
Simulation time 76057202 ps
CPU time 1.16 seconds
Started Jul 29 04:32:53 PM PDT 24
Finished Jul 29 04:32:54 PM PDT 24
Peak memory 198672 kb
Host smart-e82ec356-af97-4336-abed-4385a4fa9146
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572822700 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_csr_mem_rw_with_rand_reset.572822700
Directory /workspace/7.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_rw.2693000785
Short name T834
Test name
Test status
Simulation time 39800563 ps
CPU time 0.56 seconds
Started Jul 29 04:32:53 PM PDT 24
Finished Jul 29 04:32:54 PM PDT 24
Peak memory 193868 kb
Host smart-e856bae8-c9cf-4a9c-bceb-47580bef6f86
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693000785 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio
_csr_rw.2693000785
Directory /workspace/7.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_intr_test.2970404222
Short name T817
Test name
Test status
Simulation time 24427280 ps
CPU time 0.62 seconds
Started Jul 29 04:33:01 PM PDT 24
Finished Jul 29 04:33:01 PM PDT 24
Peak memory 194392 kb
Host smart-5d8c4fd8-fa1c-4f32-a952-5dbf090c353a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970404222 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_intr_test.2970404222
Directory /workspace/7.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.251687581
Short name T88
Test name
Test status
Simulation time 49217207 ps
CPU time 0.8 seconds
Started Jul 29 04:32:53 PM PDT 24
Finished Jul 29 04:32:54 PM PDT 24
Peak memory 196580 kb
Host smart-45e98e11-d98c-490f-9d1b-3799bc769e54
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251687581 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 7.gpio_same_csr_outstanding.251687581
Directory /workspace/7.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_errors.3235865579
Short name T801
Test name
Test status
Simulation time 56184446 ps
CPU time 2.7 seconds
Started Jul 29 04:32:57 PM PDT 24
Finished Jul 29 04:33:00 PM PDT 24
Peak memory 198524 kb
Host smart-abd2eedd-cd1a-4d1d-b681-0034596da646
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235865579 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_tl_errors.3235865579
Directory /workspace/7.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.2725565510
Short name T51
Test name
Test status
Simulation time 498835703 ps
CPU time 1.2 seconds
Started Jul 29 04:33:12 PM PDT 24
Finished Jul 29 04:33:13 PM PDT 24
Peak memory 198344 kb
Host smart-61d5c0d7-46dc-45c1-bada-9a8c520203c9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725565510 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 7.gpio_tl_intg_err.2725565510
Directory /workspace/7.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.43447960
Short name T724
Test name
Test status
Simulation time 67104258 ps
CPU time 0.79 seconds
Started Jul 29 04:33:12 PM PDT 24
Finished Jul 29 04:33:13 PM PDT 24
Peak memory 198228 kb
Host smart-f51fd2db-a62f-4c53-bf4f-aefb554a677c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43447960 -assert
nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_csr_mem_rw_with_rand_reset.43447960
Directory /workspace/8.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_rw.3150455468
Short name T103
Test name
Test status
Simulation time 36175092 ps
CPU time 0.57 seconds
Started Jul 29 04:33:01 PM PDT 24
Finished Jul 29 04:33:02 PM PDT 24
Peak memory 193796 kb
Host smart-0c616a46-8502-48c2-976c-14ac52593cdd
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150455468 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio
_csr_rw.3150455468
Directory /workspace/8.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_intr_test.3746358747
Short name T727
Test name
Test status
Simulation time 50650005 ps
CPU time 0.55 seconds
Started Jul 29 04:33:09 PM PDT 24
Finished Jul 29 04:33:10 PM PDT 24
Peak memory 194256 kb
Host smart-9cd1fdee-35c1-40de-a39b-127897acc353
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746358747 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_intr_test.3746358747
Directory /workspace/8.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_same_csr_outstanding.581084841
Short name T825
Test name
Test status
Simulation time 30679583 ps
CPU time 0.75 seconds
Started Jul 29 04:33:09 PM PDT 24
Finished Jul 29 04:33:14 PM PDT 24
Peak memory 196612 kb
Host smart-e4227fea-5419-4ed6-965a-80a2211571c1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581084841 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 8.gpio_same_csr_outstanding.581084841
Directory /workspace/8.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_errors.1937382429
Short name T810
Test name
Test status
Simulation time 71640561 ps
CPU time 2.01 seconds
Started Jul 29 04:33:12 PM PDT 24
Finished Jul 29 04:33:14 PM PDT 24
Peak memory 198368 kb
Host smart-168c8147-1c25-4f50-a3cd-9c59a3c855af
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937382429 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_tl_errors.1937382429
Directory /workspace/8.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_intg_err.3275495676
Short name T836
Test name
Test status
Simulation time 97527129 ps
CPU time 1.44 seconds
Started Jul 29 04:32:57 PM PDT 24
Finished Jul 29 04:32:59 PM PDT 24
Peak memory 198604 kb
Host smart-95e21a0e-5e2b-4684-bd5e-0f553c11cb89
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275495676 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 8.gpio_tl_intg_err.3275495676
Directory /workspace/8.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.1456827861
Short name T721
Test name
Test status
Simulation time 142948226 ps
CPU time 0.86 seconds
Started Jul 29 04:33:01 PM PDT 24
Finished Jul 29 04:33:02 PM PDT 24
Peak memory 198468 kb
Host smart-a7f7abfb-496e-48c3-925f-68b7032cbb86
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456827861 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_csr_mem_rw_with_rand_reset.1456827861
Directory /workspace/9.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_rw.2801603996
Short name T85
Test name
Test status
Simulation time 45764966 ps
CPU time 0.66 seconds
Started Jul 29 04:32:58 PM PDT 24
Finished Jul 29 04:32:59 PM PDT 24
Peak memory 196096 kb
Host smart-a9f98a33-33a4-4b23-a920-3f8191662736
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801603996 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio
_csr_rw.2801603996
Directory /workspace/9.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_intr_test.3604049867
Short name T751
Test name
Test status
Simulation time 12530556 ps
CPU time 0.6 seconds
Started Jul 29 04:33:03 PM PDT 24
Finished Jul 29 04:33:03 PM PDT 24
Peak memory 194920 kb
Host smart-a8a63730-36af-42b4-841f-7517ed26f5f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604049867 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_intr_test.3604049867
Directory /workspace/9.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_same_csr_outstanding.1560110136
Short name T73
Test name
Test status
Simulation time 145421627 ps
CPU time 0.8 seconds
Started Jul 29 04:32:58 PM PDT 24
Finished Jul 29 04:32:59 PM PDT 24
Peak memory 196764 kb
Host smart-8fd82b49-896a-425a-be32-fe24cd4422a2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560110136 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 9.gpio_same_csr_outstanding.1560110136
Directory /workspace/9.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_errors.1683271289
Short name T753
Test name
Test status
Simulation time 430273821 ps
CPU time 2 seconds
Started Jul 29 04:33:09 PM PDT 24
Finished Jul 29 04:33:12 PM PDT 24
Peak memory 198588 kb
Host smart-a9313fbe-9ce8-4aad-a2df-40f393127b31
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683271289 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_tl_errors.1683271289
Directory /workspace/9.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.3143898146
Short name T47
Test name
Test status
Simulation time 229411862 ps
CPU time 1.48 seconds
Started Jul 29 04:33:09 PM PDT 24
Finished Jul 29 04:33:10 PM PDT 24
Peak memory 198536 kb
Host smart-2ea352d1-924c-4b2f-92cd-aed7e49ff74f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143898146 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 9.gpio_tl_intg_err.3143898146
Directory /workspace/9.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/0.gpio_alert_test.4112406514
Short name T711
Test name
Test status
Simulation time 14972437 ps
CPU time 0.57 seconds
Started Jul 29 04:33:31 PM PDT 24
Finished Jul 29 04:33:32 PM PDT 24
Peak memory 194460 kb
Host smart-d3ac0b42-30a5-434f-a172-8856bd056c21
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112406514 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_alert_test.4112406514
Directory /workspace/0.gpio_alert_test/latest

Test location /workspace/coverage/default/0.gpio_dout_din_regs_random_rw.3201808785
Short name T158
Test name
Test status
Simulation time 49540788 ps
CPU time 0.62 seconds
Started Jul 29 04:33:31 PM PDT 24
Finished Jul 29 04:33:31 PM PDT 24
Peak memory 194356 kb
Host smart-32060a7f-4c3b-4779-babd-9f69f834e463
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3201808785 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_dout_din_regs_random_rw.3201808785
Directory /workspace/0.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/0.gpio_filter_stress.4024934276
Short name T198
Test name
Test status
Simulation time 863216000 ps
CPU time 21.2 seconds
Started Jul 29 04:33:52 PM PDT 24
Finished Jul 29 04:34:14 PM PDT 24
Peak memory 195968 kb
Host smart-3303558c-2ca8-425f-8a1e-b0426a21219c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024934276 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_filter_stres
s.4024934276
Directory /workspace/0.gpio_filter_stress/latest

Test location /workspace/coverage/default/0.gpio_full_random.1489277169
Short name T272
Test name
Test status
Simulation time 25011780 ps
CPU time 0.63 seconds
Started Jul 29 04:33:39 PM PDT 24
Finished Jul 29 04:33:40 PM PDT 24
Peak memory 194832 kb
Host smart-f4a96ea4-7dc0-466f-bfe1-92feeb8ecfbd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489277169 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_full_random.1489277169
Directory /workspace/0.gpio_full_random/latest

Test location /workspace/coverage/default/0.gpio_intr_rand_pgm.4173831627
Short name T393
Test name
Test status
Simulation time 37371033 ps
CPU time 1.1 seconds
Started Jul 29 04:33:37 PM PDT 24
Finished Jul 29 04:33:38 PM PDT 24
Peak memory 196520 kb
Host smart-be433525-abc2-4169-b13a-15839cc28567
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173831627 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_intr_rand_pgm.4173831627
Directory /workspace/0.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/0.gpio_intr_with_filter_rand_intr_event.977017746
Short name T583
Test name
Test status
Simulation time 132915396 ps
CPU time 2.6 seconds
Started Jul 29 04:33:25 PM PDT 24
Finished Jul 29 04:33:28 PM PDT 24
Peak memory 198584 kb
Host smart-6232d438-4c5b-43ff-a4f1-72e2bf5229ed
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977017746 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 0.gpio_intr_with_filter_rand_intr_event.977017746
Directory /workspace/0.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/0.gpio_rand_intr_trigger.2106899071
Short name T513
Test name
Test status
Simulation time 62027685 ps
CPU time 0.92 seconds
Started Jul 29 04:33:42 PM PDT 24
Finished Jul 29 04:33:43 PM PDT 24
Peak memory 194904 kb
Host smart-dcfbf6a8-257d-4c62-9a40-19ce93a6ffac
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106899071 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_rand_intr_trigger.
2106899071
Directory /workspace/0.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din.2964911371
Short name T570
Test name
Test status
Simulation time 60218073 ps
CPU time 1.16 seconds
Started Jul 29 04:33:31 PM PDT 24
Finished Jul 29 04:33:32 PM PDT 24
Peak memory 196224 kb
Host smart-a22c1a7b-8c04-405d-96a7-7101bbd5d995
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964911371 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din.2964911371
Directory /workspace/0.gpio_random_dout_din/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din_no_pullup_pulldown.4154238185
Short name T239
Test name
Test status
Simulation time 40525601 ps
CPU time 0.86 seconds
Started Jul 29 04:33:26 PM PDT 24
Finished Jul 29 04:33:27 PM PDT 24
Peak memory 196872 kb
Host smart-e51ca08a-36ee-49e2-839e-be8b95b67688
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154238185 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din_no_pullup
_pulldown.4154238185
Directory /workspace/0.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_random_long_reg_writes_reg_reads.1142251015
Short name T490
Test name
Test status
Simulation time 1312072208 ps
CPU time 4.18 seconds
Started Jul 29 04:33:29 PM PDT 24
Finished Jul 29 04:33:33 PM PDT 24
Peak memory 198300 kb
Host smart-1d0a9a4a-c2d9-4736-a380-e49c50e6f515
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142251015 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_ran
dom_long_reg_writes_reg_reads.1142251015
Directory /workspace/0.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/0.gpio_sec_cm.229771372
Short name T52
Test name
Test status
Simulation time 130926944 ps
CPU time 0.81 seconds
Started Jul 29 04:33:31 PM PDT 24
Finished Jul 29 04:33:32 PM PDT 24
Peak memory 214284 kb
Host smart-65ca28c8-ffbb-4d1f-b7aa-16fe2568f6c5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229771372 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_sec_cm.229771372
Directory /workspace/0.gpio_sec_cm/latest

Test location /workspace/coverage/default/0.gpio_smoke.3725812476
Short name T685
Test name
Test status
Simulation time 324512560 ps
CPU time 1.25 seconds
Started Jul 29 04:33:24 PM PDT 24
Finished Jul 29 04:33:26 PM PDT 24
Peak memory 196124 kb
Host smart-c2734344-240c-4240-9c81-b7c93065ab43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3725812476 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke.3725812476
Directory /workspace/0.gpio_smoke/latest

Test location /workspace/coverage/default/0.gpio_smoke_no_pullup_pulldown.492161177
Short name T594
Test name
Test status
Simulation time 56891532 ps
CPU time 1.07 seconds
Started Jul 29 04:33:39 PM PDT 24
Finished Jul 29 04:33:40 PM PDT 24
Peak memory 196788 kb
Host smart-689ff7aa-b5ef-4178-9445-2d81d0a72466
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492161177 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown.492161177
Directory /workspace/0.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_stress_all_with_rand_reset.1159857908
Short name T421
Test name
Test status
Simulation time 72161192787 ps
CPU time 1984.35 seconds
Started Jul 29 04:33:31 PM PDT 24
Finished Jul 29 05:06:36 PM PDT 24
Peak memory 198696 kb
Host smart-511c8fe6-7f63-44ac-8e18-ca056973eb56
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1159857908 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_stress_all_with_rand_reset.1159857908
Directory /workspace/0.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.gpio_alert_test.4018291473
Short name T252
Test name
Test status
Simulation time 19823196 ps
CPU time 0.56 seconds
Started Jul 29 04:33:37 PM PDT 24
Finished Jul 29 04:33:38 PM PDT 24
Peak memory 194960 kb
Host smart-400edae5-1c9c-458e-8063-7bd0ccd016c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018291473 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_alert_test.4018291473
Directory /workspace/1.gpio_alert_test/latest

Test location /workspace/coverage/default/1.gpio_dout_din_regs_random_rw.4082304465
Short name T124
Test name
Test status
Simulation time 133542278 ps
CPU time 0.83 seconds
Started Jul 29 04:33:48 PM PDT 24
Finished Jul 29 04:33:49 PM PDT 24
Peak memory 196304 kb
Host smart-be854e3e-7bb6-40f6-aa95-780f6fdd9c69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082304465 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_dout_din_regs_random_rw.4082304465
Directory /workspace/1.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/1.gpio_filter_stress.319280738
Short name T227
Test name
Test status
Simulation time 2763406348 ps
CPU time 18.76 seconds
Started Jul 29 04:33:37 PM PDT 24
Finished Jul 29 04:33:56 PM PDT 24
Peak memory 197384 kb
Host smart-ea0fb93f-879d-479e-8c8d-20cbc94a130f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319280738 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_filter_stress
.319280738
Directory /workspace/1.gpio_filter_stress/latest

Test location /workspace/coverage/default/1.gpio_full_random.1833606357
Short name T231
Test name
Test status
Simulation time 23307785 ps
CPU time 0.58 seconds
Started Jul 29 04:33:36 PM PDT 24
Finished Jul 29 04:33:36 PM PDT 24
Peak memory 195556 kb
Host smart-5c72df0e-ac6a-435e-820b-f4b05d93786f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833606357 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_full_random.1833606357
Directory /workspace/1.gpio_full_random/latest

Test location /workspace/coverage/default/1.gpio_intr_rand_pgm.1359249693
Short name T111
Test name
Test status
Simulation time 267569654 ps
CPU time 0.97 seconds
Started Jul 29 04:33:26 PM PDT 24
Finished Jul 29 04:33:27 PM PDT 24
Peak memory 196448 kb
Host smart-d1e8395d-5187-4d65-b360-d3d8c5e9fc22
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359249693 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_intr_rand_pgm.1359249693
Directory /workspace/1.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/1.gpio_intr_with_filter_rand_intr_event.3631331281
Short name T297
Test name
Test status
Simulation time 56753646 ps
CPU time 1.28 seconds
Started Jul 29 04:33:30 PM PDT 24
Finished Jul 29 04:33:32 PM PDT 24
Peak memory 196932 kb
Host smart-c9547515-66cf-45c3-9dcb-79872e5512e2
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631331281 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.gpio_intr_with_filter_rand_intr_event.3631331281
Directory /workspace/1.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/1.gpio_rand_intr_trigger.31832699
Short name T584
Test name
Test status
Simulation time 314594632 ps
CPU time 2.34 seconds
Started Jul 29 04:33:28 PM PDT 24
Finished Jul 29 04:33:31 PM PDT 24
Peak memory 197300 kb
Host smart-364c515b-ed66-41d3-ba50-49691711bf57
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31832699 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_rand_intr_trigger.31832699
Directory /workspace/1.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din.1441932536
Short name T712
Test name
Test status
Simulation time 34382409 ps
CPU time 1.2 seconds
Started Jul 29 04:33:31 PM PDT 24
Finished Jul 29 04:33:32 PM PDT 24
Peak memory 198444 kb
Host smart-a513bcb4-9cce-4012-b49e-4efec1b2621e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1441932536 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din.1441932536
Directory /workspace/1.gpio_random_dout_din/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din_no_pullup_pulldown.260974035
Short name T148
Test name
Test status
Simulation time 42090446 ps
CPU time 1.05 seconds
Started Jul 29 04:33:40 PM PDT 24
Finished Jul 29 04:33:41 PM PDT 24
Peak memory 197016 kb
Host smart-bcd04414-604b-4b48-ac98-89b5003312ca
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260974035 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din_no_pullup_
pulldown.260974035
Directory /workspace/1.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_random_long_reg_writes_reg_reads.570190241
Short name T484
Test name
Test status
Simulation time 112360781 ps
CPU time 1.78 seconds
Started Jul 29 04:33:36 PM PDT 24
Finished Jul 29 04:33:38 PM PDT 24
Peak memory 198300 kb
Host smart-2a535c39-63b1-49d8-bf6a-4b0de70718db
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570190241 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_rand
om_long_reg_writes_reg_reads.570190241
Directory /workspace/1.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/1.gpio_sec_cm.900913452
Short name T53
Test name
Test status
Simulation time 47945415 ps
CPU time 0.79 seconds
Started Jul 29 04:33:27 PM PDT 24
Finished Jul 29 04:33:28 PM PDT 24
Peak memory 215040 kb
Host smart-c3eb2db2-06e8-4e0f-a031-8ebe1647bcc2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900913452 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_sec_cm.900913452
Directory /workspace/1.gpio_sec_cm/latest

Test location /workspace/coverage/default/1.gpio_smoke.2079928345
Short name T254
Test name
Test status
Simulation time 215493977 ps
CPU time 1.06 seconds
Started Jul 29 04:33:27 PM PDT 24
Finished Jul 29 04:33:28 PM PDT 24
Peak memory 196684 kb
Host smart-edf65cd8-ec7f-48de-a652-fa383098c7d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2079928345 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke.2079928345
Directory /workspace/1.gpio_smoke/latest

Test location /workspace/coverage/default/1.gpio_smoke_no_pullup_pulldown.2186437435
Short name T538
Test name
Test status
Simulation time 292004383 ps
CPU time 1.08 seconds
Started Jul 29 04:33:25 PM PDT 24
Finished Jul 29 04:33:26 PM PDT 24
Peak memory 196648 kb
Host smart-16b90ff7-08eb-4989-a7a2-6449b1f3abe0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186437435 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown.2186437435
Directory /workspace/1.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_stress_all.1639105382
Short name T8
Test name
Test status
Simulation time 20112952445 ps
CPU time 212.51 seconds
Started Jul 29 04:33:27 PM PDT 24
Finished Jul 29 04:36:59 PM PDT 24
Peak memory 198632 kb
Host smart-ca643a0f-a2ce-4499-8dc5-838134b14c61
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639105382 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.g
pio_stress_all.1639105382
Directory /workspace/1.gpio_stress_all/latest

Test location /workspace/coverage/default/10.gpio_alert_test.3191420196
Short name T491
Test name
Test status
Simulation time 13978039 ps
CPU time 0.58 seconds
Started Jul 29 04:34:04 PM PDT 24
Finished Jul 29 04:34:05 PM PDT 24
Peak memory 194312 kb
Host smart-3534bcca-c154-46ad-aa08-ed2b8279185f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191420196 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_alert_test.3191420196
Directory /workspace/10.gpio_alert_test/latest

Test location /workspace/coverage/default/10.gpio_dout_din_regs_random_rw.2929220027
Short name T633
Test name
Test status
Simulation time 41243568 ps
CPU time 0.68 seconds
Started Jul 29 04:34:03 PM PDT 24
Finished Jul 29 04:34:04 PM PDT 24
Peak memory 195140 kb
Host smart-8faab90f-4a27-4d29-a38a-fe69fd592d53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2929220027 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_dout_din_regs_random_rw.2929220027
Directory /workspace/10.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/10.gpio_filter_stress.791354344
Short name T677
Test name
Test status
Simulation time 640263252 ps
CPU time 17.5 seconds
Started Jul 29 04:34:04 PM PDT 24
Finished Jul 29 04:34:21 PM PDT 24
Peak memory 197360 kb
Host smart-2c42256a-13d6-4ba4-b9cc-f6e68fde7680
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791354344 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_filter_stres
s.791354344
Directory /workspace/10.gpio_filter_stress/latest

Test location /workspace/coverage/default/10.gpio_full_random.236286208
Short name T142
Test name
Test status
Simulation time 265166403 ps
CPU time 0.89 seconds
Started Jul 29 04:34:00 PM PDT 24
Finished Jul 29 04:34:01 PM PDT 24
Peak memory 197648 kb
Host smart-66375a87-f716-4657-8624-2f2828d55e0e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236286208 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_full_random.236286208
Directory /workspace/10.gpio_full_random/latest

Test location /workspace/coverage/default/10.gpio_intr_rand_pgm.2854470582
Short name T411
Test name
Test status
Simulation time 111400350 ps
CPU time 1.05 seconds
Started Jul 29 04:33:58 PM PDT 24
Finished Jul 29 04:33:59 PM PDT 24
Peak memory 196552 kb
Host smart-54533a8d-8463-4aae-a803-7fb74f80250a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854470582 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_intr_rand_pgm.2854470582
Directory /workspace/10.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/10.gpio_intr_with_filter_rand_intr_event.3445009903
Short name T113
Test name
Test status
Simulation time 160862347 ps
CPU time 3.26 seconds
Started Jul 29 04:34:01 PM PDT 24
Finished Jul 29 04:34:05 PM PDT 24
Peak memory 198380 kb
Host smart-84144cb5-9f7a-4138-be73-5653774480c3
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445009903 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.gpio_intr_with_filter_rand_intr_event.3445009903
Directory /workspace/10.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/10.gpio_rand_intr_trigger.2145178567
Short name T409
Test name
Test status
Simulation time 548011408 ps
CPU time 2.85 seconds
Started Jul 29 04:34:01 PM PDT 24
Finished Jul 29 04:34:04 PM PDT 24
Peak memory 196872 kb
Host smart-53950081-7772-4ca9-96a9-3c0e3aff3357
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145178567 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_rand_intr_trigger
.2145178567
Directory /workspace/10.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din.3262041464
Short name T222
Test name
Test status
Simulation time 139125688 ps
CPU time 0.88 seconds
Started Jul 29 04:33:59 PM PDT 24
Finished Jul 29 04:34:00 PM PDT 24
Peak memory 197688 kb
Host smart-41a08c18-74c5-424d-8b14-15b47997ab92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262041464 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din.3262041464
Directory /workspace/10.gpio_random_dout_din/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din_no_pullup_pulldown.809727168
Short name T331
Test name
Test status
Simulation time 29903273 ps
CPU time 0.74 seconds
Started Jul 29 04:34:05 PM PDT 24
Finished Jul 29 04:34:06 PM PDT 24
Peak memory 195680 kb
Host smart-2965c145-a245-4f50-a2a2-cbdd361cf0bb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809727168 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din_no_pullup
_pulldown.809727168
Directory /workspace/10.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_random_long_reg_writes_reg_reads.1014392949
Short name T527
Test name
Test status
Simulation time 123532889 ps
CPU time 2.26 seconds
Started Jul 29 04:33:57 PM PDT 24
Finished Jul 29 04:34:00 PM PDT 24
Peak memory 198400 kb
Host smart-18a178e6-38ca-4d6a-9195-72fac783c3a9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014392949 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_ra
ndom_long_reg_writes_reg_reads.1014392949
Directory /workspace/10.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/10.gpio_smoke.1339450132
Short name T28
Test name
Test status
Simulation time 55286999 ps
CPU time 1.08 seconds
Started Jul 29 04:33:58 PM PDT 24
Finished Jul 29 04:33:59 PM PDT 24
Peak memory 196140 kb
Host smart-c2d64706-54f8-4377-ab5f-4ec5ea39b0b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1339450132 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke.1339450132
Directory /workspace/10.gpio_smoke/latest

Test location /workspace/coverage/default/10.gpio_smoke_no_pullup_pulldown.3627638959
Short name T448
Test name
Test status
Simulation time 73693120 ps
CPU time 1.24 seconds
Started Jul 29 04:33:53 PM PDT 24
Finished Jul 29 04:33:55 PM PDT 24
Peak memory 197096 kb
Host smart-23dae0ee-879d-4da7-bb6d-06a5444c683e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627638959 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown.3627638959
Directory /workspace/10.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_stress_all.2649792219
Short name T519
Test name
Test status
Simulation time 25567172961 ps
CPU time 184.58 seconds
Started Jul 29 04:34:05 PM PDT 24
Finished Jul 29 04:37:10 PM PDT 24
Peak memory 198524 kb
Host smart-de771112-f78d-4ef5-a181-0a2986dc13cd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649792219 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.
gpio_stress_all.2649792219
Directory /workspace/10.gpio_stress_all/latest

Test location /workspace/coverage/default/11.gpio_alert_test.2982778489
Short name T557
Test name
Test status
Simulation time 13425338 ps
CPU time 0.57 seconds
Started Jul 29 04:34:04 PM PDT 24
Finished Jul 29 04:34:05 PM PDT 24
Peak memory 195196 kb
Host smart-1ea4100e-2a78-4855-b51f-81d47760cb42
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982778489 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_alert_test.2982778489
Directory /workspace/11.gpio_alert_test/latest

Test location /workspace/coverage/default/11.gpio_dout_din_regs_random_rw.3371315366
Short name T122
Test name
Test status
Simulation time 17363652 ps
CPU time 0.67 seconds
Started Jul 29 04:33:50 PM PDT 24
Finished Jul 29 04:33:51 PM PDT 24
Peak memory 194516 kb
Host smart-c0cbf6a4-cbc6-437e-8971-d090c5804bab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3371315366 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_dout_din_regs_random_rw.3371315366
Directory /workspace/11.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/11.gpio_filter_stress.1081190117
Short name T508
Test name
Test status
Simulation time 123525983 ps
CPU time 6.49 seconds
Started Jul 29 04:34:02 PM PDT 24
Finished Jul 29 04:34:09 PM PDT 24
Peak memory 198332 kb
Host smart-e8036376-9a45-41eb-b3ae-792f58441da1
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081190117 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_filter_stre
ss.1081190117
Directory /workspace/11.gpio_filter_stress/latest

Test location /workspace/coverage/default/11.gpio_full_random.1521488599
Short name T19
Test name
Test status
Simulation time 113976445 ps
CPU time 0.8 seconds
Started Jul 29 04:34:00 PM PDT 24
Finished Jul 29 04:34:01 PM PDT 24
Peak memory 197012 kb
Host smart-b4ee9f86-53f8-43fb-aad5-3f9051304c30
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521488599 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_full_random.1521488599
Directory /workspace/11.gpio_full_random/latest

Test location /workspace/coverage/default/11.gpio_intr_rand_pgm.3600512930
Short name T313
Test name
Test status
Simulation time 45243033 ps
CPU time 0.8 seconds
Started Jul 29 04:34:07 PM PDT 24
Finished Jul 29 04:34:08 PM PDT 24
Peak memory 196488 kb
Host smart-d69fe12b-a068-4150-b3d6-41a6d2799112
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600512930 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_intr_rand_pgm.3600512930
Directory /workspace/11.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/11.gpio_intr_with_filter_rand_intr_event.4133889866
Short name T630
Test name
Test status
Simulation time 147188209 ps
CPU time 3.03 seconds
Started Jul 29 04:34:02 PM PDT 24
Finished Jul 29 04:34:05 PM PDT 24
Peak memory 198504 kb
Host smart-9e2e592a-5654-47a5-81ec-305175ca8067
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133889866 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.gpio_intr_with_filter_rand_intr_event.4133889866
Directory /workspace/11.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/11.gpio_rand_intr_trigger.2718330557
Short name T328
Test name
Test status
Simulation time 96023675 ps
CPU time 2.9 seconds
Started Jul 29 04:33:53 PM PDT 24
Finished Jul 29 04:33:56 PM PDT 24
Peak memory 196232 kb
Host smart-5b4a95a2-f300-4c1d-b8a1-ce1efc326dc9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718330557 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_rand_intr_trigger
.2718330557
Directory /workspace/11.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din.3864226267
Short name T431
Test name
Test status
Simulation time 229923572 ps
CPU time 1.19 seconds
Started Jul 29 04:33:57 PM PDT 24
Finished Jul 29 04:33:59 PM PDT 24
Peak memory 197420 kb
Host smart-f0a2bf65-cff7-493c-bfc0-7512f0fbc04d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3864226267 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din.3864226267
Directory /workspace/11.gpio_random_dout_din/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din_no_pullup_pulldown.1458907676
Short name T648
Test name
Test status
Simulation time 168228126 ps
CPU time 1.06 seconds
Started Jul 29 04:34:08 PM PDT 24
Finished Jul 29 04:34:09 PM PDT 24
Peak memory 196188 kb
Host smart-5ce24344-bfee-4759-a50e-a8ac6b116695
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458907676 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din_no_pullu
p_pulldown.1458907676
Directory /workspace/11.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_random_long_reg_writes_reg_reads.4236925454
Short name T643
Test name
Test status
Simulation time 851764479 ps
CPU time 4.32 seconds
Started Jul 29 04:34:03 PM PDT 24
Finished Jul 29 04:34:07 PM PDT 24
Peak memory 198420 kb
Host smart-b3753ac5-8146-4512-a6b7-65c17f25fe3a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236925454 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_ra
ndom_long_reg_writes_reg_reads.4236925454
Directory /workspace/11.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/11.gpio_smoke.432204611
Short name T499
Test name
Test status
Simulation time 43926644 ps
CPU time 0.77 seconds
Started Jul 29 04:34:05 PM PDT 24
Finished Jul 29 04:34:06 PM PDT 24
Peak memory 196276 kb
Host smart-f1f11150-0e49-428b-975a-66faf33ecf36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=432204611 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke.432204611
Directory /workspace/11.gpio_smoke/latest

Test location /workspace/coverage/default/11.gpio_smoke_no_pullup_pulldown.287536443
Short name T13
Test name
Test status
Simulation time 165050012 ps
CPU time 1.25 seconds
Started Jul 29 04:34:00 PM PDT 24
Finished Jul 29 04:34:02 PM PDT 24
Peak memory 198416 kb
Host smart-91eeb9a6-692d-4d4e-a536-48fbac145b26
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287536443 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown.287536443
Directory /workspace/11.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_stress_all.1198609158
Short name T416
Test name
Test status
Simulation time 11556991667 ps
CPU time 149.23 seconds
Started Jul 29 04:33:59 PM PDT 24
Finished Jul 29 04:36:28 PM PDT 24
Peak memory 198564 kb
Host smart-a256063d-ef4d-4ded-af9e-ced3a80d7ca9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198609158 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.
gpio_stress_all.1198609158
Directory /workspace/11.gpio_stress_all/latest

Test location /workspace/coverage/default/12.gpio_alert_test.711916496
Short name T613
Test name
Test status
Simulation time 46909862 ps
CPU time 0.59 seconds
Started Jul 29 04:33:57 PM PDT 24
Finished Jul 29 04:33:57 PM PDT 24
Peak memory 195112 kb
Host smart-6766c101-4d9b-4228-8a34-d6ea777bdc32
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711916496 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_alert_test.711916496
Directory /workspace/12.gpio_alert_test/latest

Test location /workspace/coverage/default/12.gpio_dout_din_regs_random_rw.546242558
Short name T705
Test name
Test status
Simulation time 408941412 ps
CPU time 0.91 seconds
Started Jul 29 04:33:59 PM PDT 24
Finished Jul 29 04:34:00 PM PDT 24
Peak memory 196900 kb
Host smart-4354ee5e-5328-4afc-b702-21e961dfdf89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=546242558 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_dout_din_regs_random_rw.546242558
Directory /workspace/12.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/12.gpio_filter_stress.9783418
Short name T355
Test name
Test status
Simulation time 434652428 ps
CPU time 22.45 seconds
Started Jul 29 04:34:01 PM PDT 24
Finished Jul 29 04:34:24 PM PDT 24
Peak memory 197500 kb
Host smart-8dff89fc-4a49-4ce4-a868-0dbbc2efbbcd
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9783418 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_s
tress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_filter_stress.9783418
Directory /workspace/12.gpio_filter_stress/latest

Test location /workspace/coverage/default/12.gpio_full_random.1273380219
Short name T631
Test name
Test status
Simulation time 40754792 ps
CPU time 0.71 seconds
Started Jul 29 04:34:05 PM PDT 24
Finished Jul 29 04:34:06 PM PDT 24
Peak memory 195836 kb
Host smart-8ed34e03-877a-4277-a736-b475955c046b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273380219 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_full_random.1273380219
Directory /workspace/12.gpio_full_random/latest

Test location /workspace/coverage/default/12.gpio_intr_rand_pgm.939417445
Short name T210
Test name
Test status
Simulation time 162287069 ps
CPU time 1.14 seconds
Started Jul 29 04:33:58 PM PDT 24
Finished Jul 29 04:33:59 PM PDT 24
Peak memory 196472 kb
Host smart-0c07355a-3225-461d-83e0-a17163105cb9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939417445 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_intr_rand_pgm.939417445
Directory /workspace/12.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/12.gpio_intr_with_filter_rand_intr_event.1754865753
Short name T540
Test name
Test status
Simulation time 86108049 ps
CPU time 3.52 seconds
Started Jul 29 04:33:49 PM PDT 24
Finished Jul 29 04:33:53 PM PDT 24
Peak memory 198336 kb
Host smart-6fe08030-0bf8-4dd1-86d9-00cc7f13dbcf
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754865753 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 12.gpio_intr_with_filter_rand_intr_event.1754865753
Directory /workspace/12.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/12.gpio_rand_intr_trigger.2385701128
Short name T18
Test name
Test status
Simulation time 236274238 ps
CPU time 3.25 seconds
Started Jul 29 04:34:08 PM PDT 24
Finished Jul 29 04:34:12 PM PDT 24
Peak memory 197288 kb
Host smart-9ba9dbed-4d0d-4eb5-be8a-5c96cf754759
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385701128 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_rand_intr_trigger
.2385701128
Directory /workspace/12.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din.2972314763
Short name T471
Test name
Test status
Simulation time 78348721 ps
CPU time 1.31 seconds
Started Jul 29 04:33:58 PM PDT 24
Finished Jul 29 04:34:00 PM PDT 24
Peak memory 197384 kb
Host smart-20da1636-f007-4771-9ae0-8c79d0eea6b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2972314763 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din.2972314763
Directory /workspace/12.gpio_random_dout_din/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din_no_pullup_pulldown.2255061039
Short name T612
Test name
Test status
Simulation time 172283744 ps
CPU time 0.78 seconds
Started Jul 29 04:33:57 PM PDT 24
Finished Jul 29 04:33:58 PM PDT 24
Peak memory 196628 kb
Host smart-57540b83-9f0c-43b0-a2a4-c9f8e6ff5f7d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255061039 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din_no_pullu
p_pulldown.2255061039
Directory /workspace/12.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_random_long_reg_writes_reg_reads.2100488635
Short name T534
Test name
Test status
Simulation time 3467682533 ps
CPU time 3.07 seconds
Started Jul 29 04:33:58 PM PDT 24
Finished Jul 29 04:34:01 PM PDT 24
Peak memory 198620 kb
Host smart-076e6929-c4ff-4b19-abb4-6ffc9f40f3a3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100488635 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_ra
ndom_long_reg_writes_reg_reads.2100488635
Directory /workspace/12.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/12.gpio_smoke.772299087
Short name T159
Test name
Test status
Simulation time 104103459 ps
CPU time 1.46 seconds
Started Jul 29 04:33:58 PM PDT 24
Finished Jul 29 04:34:00 PM PDT 24
Peak memory 195952 kb
Host smart-090bb234-da22-4c51-8f58-0a4395f66ae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=772299087 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke.772299087
Directory /workspace/12.gpio_smoke/latest

Test location /workspace/coverage/default/12.gpio_smoke_no_pullup_pulldown.3444638250
Short name T351
Test name
Test status
Simulation time 37560150 ps
CPU time 0.86 seconds
Started Jul 29 04:33:59 PM PDT 24
Finished Jul 29 04:34:00 PM PDT 24
Peak memory 196696 kb
Host smart-0bcf9fbe-28c2-43c0-b94a-4ee16e41e6cd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444638250 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown.3444638250
Directory /workspace/12.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_stress_all.2202632118
Short name T211
Test name
Test status
Simulation time 20697941868 ps
CPU time 121.9 seconds
Started Jul 29 04:33:53 PM PDT 24
Finished Jul 29 04:35:55 PM PDT 24
Peak memory 198708 kb
Host smart-28ba438d-bdda-46cb-8c78-fb2a844c858d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202632118 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.
gpio_stress_all.2202632118
Directory /workspace/12.gpio_stress_all/latest

Test location /workspace/coverage/default/12.gpio_stress_all_with_rand_reset.3159633198
Short name T548
Test name
Test status
Simulation time 409263438456 ps
CPU time 2393.45 seconds
Started Jul 29 04:34:11 PM PDT 24
Finished Jul 29 05:14:05 PM PDT 24
Peak memory 198692 kb
Host smart-06e1cf64-8619-438e-946a-71da4dbe1de2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3159633198 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_stress_all_with_rand_reset.3159633198
Directory /workspace/12.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.gpio_alert_test.2318239910
Short name T665
Test name
Test status
Simulation time 32206821 ps
CPU time 0.58 seconds
Started Jul 29 04:34:03 PM PDT 24
Finished Jul 29 04:34:04 PM PDT 24
Peak memory 194972 kb
Host smart-c6917b98-6996-4b51-8d8a-2bd4f2508f2b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318239910 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_alert_test.2318239910
Directory /workspace/13.gpio_alert_test/latest

Test location /workspace/coverage/default/13.gpio_dout_din_regs_random_rw.2103911435
Short name T282
Test name
Test status
Simulation time 67699312 ps
CPU time 0.81 seconds
Started Jul 29 04:34:07 PM PDT 24
Finished Jul 29 04:34:08 PM PDT 24
Peak memory 196420 kb
Host smart-8a24f9d5-8a6d-4de8-95ec-d0de9d71a15f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103911435 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_dout_din_regs_random_rw.2103911435
Directory /workspace/13.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/13.gpio_filter_stress.3486801884
Short name T588
Test name
Test status
Simulation time 922555802 ps
CPU time 13.12 seconds
Started Jul 29 04:34:20 PM PDT 24
Finished Jul 29 04:34:33 PM PDT 24
Peak memory 197368 kb
Host smart-6180af06-d036-45e7-b422-dd6acb445df3
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486801884 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_filter_stre
ss.3486801884
Directory /workspace/13.gpio_filter_stress/latest

Test location /workspace/coverage/default/13.gpio_full_random.1720259931
Short name T1
Test name
Test status
Simulation time 172797712 ps
CPU time 0.95 seconds
Started Jul 29 04:34:13 PM PDT 24
Finished Jul 29 04:34:14 PM PDT 24
Peak memory 196956 kb
Host smart-80d19bc3-b0a1-4c4e-b48e-eacc571f453b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720259931 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_full_random.1720259931
Directory /workspace/13.gpio_full_random/latest

Test location /workspace/coverage/default/13.gpio_intr_rand_pgm.3199801308
Short name T494
Test name
Test status
Simulation time 65127441 ps
CPU time 0.78 seconds
Started Jul 29 04:34:18 PM PDT 24
Finished Jul 29 04:34:18 PM PDT 24
Peak memory 195976 kb
Host smart-4a4a21eb-27c9-4e73-bb5a-fa56565af29f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199801308 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_intr_rand_pgm.3199801308
Directory /workspace/13.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/13.gpio_intr_with_filter_rand_intr_event.2903562437
Short name T634
Test name
Test status
Simulation time 30257814 ps
CPU time 1.29 seconds
Started Jul 29 04:34:07 PM PDT 24
Finished Jul 29 04:34:09 PM PDT 24
Peak memory 198132 kb
Host smart-e2719d67-13fa-4771-9fa7-b2c9a67010cb
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903562437 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 13.gpio_intr_with_filter_rand_intr_event.2903562437
Directory /workspace/13.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/13.gpio_rand_intr_trigger.2442053891
Short name T388
Test name
Test status
Simulation time 231506527 ps
CPU time 3.36 seconds
Started Jul 29 04:34:01 PM PDT 24
Finished Jul 29 04:34:04 PM PDT 24
Peak memory 198408 kb
Host smart-20187ce2-a49d-4898-a3ca-3dc4301403ef
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442053891 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_rand_intr_trigger
.2442053891
Directory /workspace/13.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din.1701940441
Short name T164
Test name
Test status
Simulation time 161746182 ps
CPU time 1.04 seconds
Started Jul 29 04:33:58 PM PDT 24
Finished Jul 29 04:33:59 PM PDT 24
Peak memory 196996 kb
Host smart-32f844e9-d85b-4e0c-8fb6-d453c8c9aa04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1701940441 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din.1701940441
Directory /workspace/13.gpio_random_dout_din/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din_no_pullup_pulldown.2918150774
Short name T526
Test name
Test status
Simulation time 25068307 ps
CPU time 0.68 seconds
Started Jul 29 04:33:51 PM PDT 24
Finished Jul 29 04:33:52 PM PDT 24
Peak memory 194648 kb
Host smart-efc6d588-83a0-4954-8ae5-df6530101c0f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918150774 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din_no_pullu
p_pulldown.2918150774
Directory /workspace/13.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_random_long_reg_writes_reg_reads.1618183811
Short name T408
Test name
Test status
Simulation time 384518814 ps
CPU time 4.27 seconds
Started Jul 29 04:34:01 PM PDT 24
Finished Jul 29 04:34:05 PM PDT 24
Peak memory 198312 kb
Host smart-e2bbe9db-e317-4488-a117-3083184db59f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618183811 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_ra
ndom_long_reg_writes_reg_reads.1618183811
Directory /workspace/13.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/13.gpio_smoke.95434988
Short name T528
Test name
Test status
Simulation time 43078456 ps
CPU time 1.27 seconds
Started Jul 29 04:34:00 PM PDT 24
Finished Jul 29 04:34:02 PM PDT 24
Peak memory 198356 kb
Host smart-9d470763-a97b-4379-b348-bef7ce247599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95434988 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke.95434988
Directory /workspace/13.gpio_smoke/latest

Test location /workspace/coverage/default/13.gpio_smoke_no_pullup_pulldown.1963777764
Short name T691
Test name
Test status
Simulation time 46660146 ps
CPU time 1.26 seconds
Started Jul 29 04:34:02 PM PDT 24
Finished Jul 29 04:34:03 PM PDT 24
Peak memory 195908 kb
Host smart-a483821a-0dfe-4139-8b74-85d7cb4ca8cd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963777764 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown.1963777764
Directory /workspace/13.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_stress_all.2723240334
Short name T447
Test name
Test status
Simulation time 57038854611 ps
CPU time 148.41 seconds
Started Jul 29 04:34:19 PM PDT 24
Finished Jul 29 04:36:48 PM PDT 24
Peak memory 198536 kb
Host smart-1ecb2fef-454a-40d2-8ecd-10f780c0e3b1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723240334 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.
gpio_stress_all.2723240334
Directory /workspace/13.gpio_stress_all/latest

Test location /workspace/coverage/default/13.gpio_stress_all_with_rand_reset.1054812244
Short name T437
Test name
Test status
Simulation time 181521279748 ps
CPU time 2023.81 seconds
Started Jul 29 04:34:08 PM PDT 24
Finished Jul 29 05:07:52 PM PDT 24
Peak memory 198764 kb
Host smart-72111b59-1916-4677-a4a9-eb1e3affa1fa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1054812244 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_stress_all_with_rand_reset.1054812244
Directory /workspace/13.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.gpio_dout_din_regs_random_rw.2896119265
Short name T517
Test name
Test status
Simulation time 24166309 ps
CPU time 0.76 seconds
Started Jul 29 04:33:59 PM PDT 24
Finished Jul 29 04:34:00 PM PDT 24
Peak memory 195652 kb
Host smart-ceb94b71-8d99-42fe-ba82-433ec371d485
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2896119265 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_dout_din_regs_random_rw.2896119265
Directory /workspace/14.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/14.gpio_filter_stress.1348693227
Short name T704
Test name
Test status
Simulation time 2301014987 ps
CPU time 24.37 seconds
Started Jul 29 04:34:17 PM PDT 24
Finished Jul 29 04:34:42 PM PDT 24
Peak memory 197412 kb
Host smart-05e71d4c-d95a-4bfe-9e15-5863a46b6ef3
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348693227 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_filter_stre
ss.1348693227
Directory /workspace/14.gpio_filter_stress/latest

Test location /workspace/coverage/default/14.gpio_full_random.3625826159
Short name T656
Test name
Test status
Simulation time 274175326 ps
CPU time 0.97 seconds
Started Jul 29 04:34:03 PM PDT 24
Finished Jul 29 04:34:04 PM PDT 24
Peak memory 197288 kb
Host smart-f4d59b9a-456a-49d0-9df0-6ac4685bc554
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625826159 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_full_random.3625826159
Directory /workspace/14.gpio_full_random/latest

Test location /workspace/coverage/default/14.gpio_intr_rand_pgm.2878053389
Short name T664
Test name
Test status
Simulation time 71650250 ps
CPU time 0.64 seconds
Started Jul 29 04:34:05 PM PDT 24
Finished Jul 29 04:34:05 PM PDT 24
Peak memory 194604 kb
Host smart-831abfa4-6bc2-4e18-9774-6b8aa6df3e56
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878053389 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_intr_rand_pgm.2878053389
Directory /workspace/14.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/14.gpio_intr_with_filter_rand_intr_event.4041711467
Short name T309
Test name
Test status
Simulation time 159265272 ps
CPU time 2.07 seconds
Started Jul 29 04:34:03 PM PDT 24
Finished Jul 29 04:34:05 PM PDT 24
Peak memory 198560 kb
Host smart-fda4700b-ea40-4221-a082-958e2bb45537
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041711467 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.gpio_intr_with_filter_rand_intr_event.4041711467
Directory /workspace/14.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/14.gpio_rand_intr_trigger.1624288362
Short name T449
Test name
Test status
Simulation time 109715786 ps
CPU time 2.4 seconds
Started Jul 29 04:34:09 PM PDT 24
Finished Jul 29 04:34:12 PM PDT 24
Peak memory 197620 kb
Host smart-26cdf800-f1c7-442b-b4f0-8b91a4373bd3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624288362 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_rand_intr_trigger
.1624288362
Directory /workspace/14.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din.746072330
Short name T478
Test name
Test status
Simulation time 76908313 ps
CPU time 1.43 seconds
Started Jul 29 04:33:57 PM PDT 24
Finished Jul 29 04:33:59 PM PDT 24
Peak memory 197404 kb
Host smart-12301d35-0b8d-477b-8050-96fddd93bd2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=746072330 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din.746072330
Directory /workspace/14.gpio_random_dout_din/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din_no_pullup_pulldown.3402922367
Short name T320
Test name
Test status
Simulation time 44549823 ps
CPU time 0.7 seconds
Started Jul 29 04:34:07 PM PDT 24
Finished Jul 29 04:34:08 PM PDT 24
Peak memory 194652 kb
Host smart-3fc1333d-a4af-4dda-97be-60026bdb78b6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402922367 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din_no_pullu
p_pulldown.3402922367
Directory /workspace/14.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_random_long_reg_writes_reg_reads.1078414717
Short name T371
Test name
Test status
Simulation time 1209076027 ps
CPU time 3.84 seconds
Started Jul 29 04:34:13 PM PDT 24
Finished Jul 29 04:34:17 PM PDT 24
Peak memory 198364 kb
Host smart-f0a856be-42ae-4829-a45a-3763660ec7fb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078414717 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_ra
ndom_long_reg_writes_reg_reads.1078414717
Directory /workspace/14.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/14.gpio_smoke.1253004749
Short name T341
Test name
Test status
Simulation time 104786567 ps
CPU time 0.79 seconds
Started Jul 29 04:33:55 PM PDT 24
Finished Jul 29 04:33:56 PM PDT 24
Peak memory 196220 kb
Host smart-8eb887a0-eb54-4697-8cdf-b3710aa27ef1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1253004749 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke.1253004749
Directory /workspace/14.gpio_smoke/latest

Test location /workspace/coverage/default/14.gpio_smoke_no_pullup_pulldown.1824516757
Short name T289
Test name
Test status
Simulation time 72853893 ps
CPU time 1.19 seconds
Started Jul 29 04:33:59 PM PDT 24
Finished Jul 29 04:34:01 PM PDT 24
Peak memory 197152 kb
Host smart-a6545aaa-fabb-4920-b17f-dd802bffbe97
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824516757 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown.1824516757
Directory /workspace/14.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_stress_all.2093178464
Short name T7
Test name
Test status
Simulation time 9864961401 ps
CPU time 55.41 seconds
Started Jul 29 04:34:10 PM PDT 24
Finished Jul 29 04:35:06 PM PDT 24
Peak memory 198520 kb
Host smart-195b933c-a132-4448-896e-842e5dd85275
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093178464 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.
gpio_stress_all.2093178464
Directory /workspace/14.gpio_stress_all/latest

Test location /workspace/coverage/default/15.gpio_alert_test.3206176909
Short name T205
Test name
Test status
Simulation time 14442051 ps
CPU time 0.59 seconds
Started Jul 29 04:34:04 PM PDT 24
Finished Jul 29 04:34:05 PM PDT 24
Peak memory 194500 kb
Host smart-d729c8e8-7437-4119-91a9-d36127569b1f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206176909 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_alert_test.3206176909
Directory /workspace/15.gpio_alert_test/latest

Test location /workspace/coverage/default/15.gpio_dout_din_regs_random_rw.1693250727
Short name T136
Test name
Test status
Simulation time 36279432 ps
CPU time 0.86 seconds
Started Jul 29 04:34:04 PM PDT 24
Finished Jul 29 04:34:05 PM PDT 24
Peak memory 196960 kb
Host smart-dd2f57bb-55b8-44c1-8a6c-4104e1d68f98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1693250727 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_dout_din_regs_random_rw.1693250727
Directory /workspace/15.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/15.gpio_filter_stress.3148451057
Short name T689
Test name
Test status
Simulation time 3388210723 ps
CPU time 26.24 seconds
Started Jul 29 04:34:24 PM PDT 24
Finished Jul 29 04:34:50 PM PDT 24
Peak memory 197120 kb
Host smart-0cbba541-f5fa-4d25-9b56-bf99c52caf13
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148451057 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_filter_stre
ss.3148451057
Directory /workspace/15.gpio_filter_stress/latest

Test location /workspace/coverage/default/15.gpio_intr_rand_pgm.2309954086
Short name T120
Test name
Test status
Simulation time 54604628 ps
CPU time 0.78 seconds
Started Jul 29 04:34:07 PM PDT 24
Finished Jul 29 04:34:08 PM PDT 24
Peak memory 195916 kb
Host smart-091bebf8-1f40-41b3-b0dd-5652d805bb06
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309954086 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_intr_rand_pgm.2309954086
Directory /workspace/15.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/15.gpio_intr_with_filter_rand_intr_event.1553976851
Short name T192
Test name
Test status
Simulation time 366754388 ps
CPU time 3.35 seconds
Started Jul 29 04:34:06 PM PDT 24
Finished Jul 29 04:34:10 PM PDT 24
Peak memory 196884 kb
Host smart-48274c61-5ad6-40d0-bddf-a77c15ab3960
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553976851 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.gpio_intr_with_filter_rand_intr_event.1553976851
Directory /workspace/15.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/15.gpio_rand_intr_trigger.2018357651
Short name T264
Test name
Test status
Simulation time 100831807 ps
CPU time 2.98 seconds
Started Jul 29 04:33:59 PM PDT 24
Finished Jul 29 04:34:02 PM PDT 24
Peak memory 197496 kb
Host smart-e22fc4d4-86e9-41e3-8b9e-100a43390b3c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018357651 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_rand_intr_trigger
.2018357651
Directory /workspace/15.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din.167422096
Short name T485
Test name
Test status
Simulation time 56769718 ps
CPU time 0.79 seconds
Started Jul 29 04:34:00 PM PDT 24
Finished Jul 29 04:34:01 PM PDT 24
Peak memory 195848 kb
Host smart-c18a87be-b30d-46a1-9de4-d1e9980ec7ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=167422096 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din.167422096
Directory /workspace/15.gpio_random_dout_din/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din_no_pullup_pulldown.2794222634
Short name T451
Test name
Test status
Simulation time 47290389 ps
CPU time 1.13 seconds
Started Jul 29 04:34:08 PM PDT 24
Finished Jul 29 04:34:09 PM PDT 24
Peak memory 196420 kb
Host smart-e16fe3e4-c595-4a16-874d-1dbeffe683ad
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794222634 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din_no_pullu
p_pulldown.2794222634
Directory /workspace/15.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_random_long_reg_writes_reg_reads.3708052385
Short name T649
Test name
Test status
Simulation time 310513835 ps
CPU time 4.54 seconds
Started Jul 29 04:34:06 PM PDT 24
Finished Jul 29 04:34:11 PM PDT 24
Peak memory 198268 kb
Host smart-09f806cd-6145-4940-8717-e25fdfaf532c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708052385 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_ra
ndom_long_reg_writes_reg_reads.3708052385
Directory /workspace/15.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/15.gpio_smoke.1371813473
Short name T578
Test name
Test status
Simulation time 52713452 ps
CPU time 1.2 seconds
Started Jul 29 04:34:02 PM PDT 24
Finished Jul 29 04:34:04 PM PDT 24
Peak memory 195924 kb
Host smart-9b429a25-a97d-4324-bf99-848bd14e3066
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1371813473 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke.1371813473
Directory /workspace/15.gpio_smoke/latest

Test location /workspace/coverage/default/15.gpio_smoke_no_pullup_pulldown.2928765803
Short name T607
Test name
Test status
Simulation time 101259844 ps
CPU time 0.89 seconds
Started Jul 29 04:34:06 PM PDT 24
Finished Jul 29 04:34:07 PM PDT 24
Peak memory 196208 kb
Host smart-d2d8e193-e680-4516-81c8-5c1ecf1acc85
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928765803 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown.2928765803
Directory /workspace/15.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_stress_all.3908823428
Short name T602
Test name
Test status
Simulation time 2308357026 ps
CPU time 51.5 seconds
Started Jul 29 04:34:14 PM PDT 24
Finished Jul 29 04:35:06 PM PDT 24
Peak memory 198324 kb
Host smart-c6235faa-881b-4968-ac86-3f5ba432d7af
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908823428 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.
gpio_stress_all.3908823428
Directory /workspace/15.gpio_stress_all/latest

Test location /workspace/coverage/default/16.gpio_alert_test.1279152813
Short name T322
Test name
Test status
Simulation time 34824840 ps
CPU time 0.55 seconds
Started Jul 29 04:34:04 PM PDT 24
Finished Jul 29 04:34:05 PM PDT 24
Peak memory 194408 kb
Host smart-7381ffc9-194d-4380-902e-62dbbf1ba9ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279152813 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_alert_test.1279152813
Directory /workspace/16.gpio_alert_test/latest

Test location /workspace/coverage/default/16.gpio_dout_din_regs_random_rw.2448434426
Short name T614
Test name
Test status
Simulation time 19904234 ps
CPU time 0.64 seconds
Started Jul 29 04:34:04 PM PDT 24
Finished Jul 29 04:34:05 PM PDT 24
Peak memory 194388 kb
Host smart-098c220d-d55f-440a-afc2-0bbedde8beee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448434426 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_dout_din_regs_random_rw.2448434426
Directory /workspace/16.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/16.gpio_filter_stress.3950854652
Short name T573
Test name
Test status
Simulation time 325922377 ps
CPU time 8.83 seconds
Started Jul 29 04:34:21 PM PDT 24
Finished Jul 29 04:34:30 PM PDT 24
Peak memory 197224 kb
Host smart-5c7881a8-6e3f-496c-84f7-365a08e7ae43
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950854652 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_filter_stre
ss.3950854652
Directory /workspace/16.gpio_filter_stress/latest

Test location /workspace/coverage/default/16.gpio_full_random.1849904482
Short name T593
Test name
Test status
Simulation time 61980653 ps
CPU time 0.88 seconds
Started Jul 29 04:34:05 PM PDT 24
Finished Jul 29 04:34:06 PM PDT 24
Peak memory 197544 kb
Host smart-b2b2e553-663a-4583-b18b-36d62fc2c2f0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849904482 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_full_random.1849904482
Directory /workspace/16.gpio_full_random/latest

Test location /workspace/coverage/default/16.gpio_intr_rand_pgm.715295048
Short name T603
Test name
Test status
Simulation time 53944672 ps
CPU time 0.65 seconds
Started Jul 29 04:34:05 PM PDT 24
Finished Jul 29 04:34:05 PM PDT 24
Peak memory 194552 kb
Host smart-7bd22382-2149-4914-9c5e-35e80276b19a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715295048 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_intr_rand_pgm.715295048
Directory /workspace/16.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/16.gpio_intr_with_filter_rand_intr_event.4153373535
Short name T197
Test name
Test status
Simulation time 395967441 ps
CPU time 2.12 seconds
Started Jul 29 04:34:18 PM PDT 24
Finished Jul 29 04:34:21 PM PDT 24
Peak memory 198440 kb
Host smart-d2e31525-4356-4d2f-af2e-03b4046674ec
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153373535 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.gpio_intr_with_filter_rand_intr_event.4153373535
Directory /workspace/16.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/16.gpio_rand_intr_trigger.3554282649
Short name T453
Test name
Test status
Simulation time 342280465 ps
CPU time 3.19 seconds
Started Jul 29 04:34:02 PM PDT 24
Finished Jul 29 04:34:05 PM PDT 24
Peak memory 198420 kb
Host smart-77853ba4-797f-452c-bea5-22883ea58dab
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554282649 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_rand_intr_trigger
.3554282649
Directory /workspace/16.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din.2283114513
Short name T473
Test name
Test status
Simulation time 45405132 ps
CPU time 0.95 seconds
Started Jul 29 04:34:21 PM PDT 24
Finished Jul 29 04:34:22 PM PDT 24
Peak memory 196436 kb
Host smart-ec42b4eb-cf73-46b0-a32b-80fea0959a95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2283114513 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din.2283114513
Directory /workspace/16.gpio_random_dout_din/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din_no_pullup_pulldown.910169085
Short name T112
Test name
Test status
Simulation time 23780802 ps
CPU time 0.86 seconds
Started Jul 29 04:33:59 PM PDT 24
Finished Jul 29 04:34:00 PM PDT 24
Peak memory 197128 kb
Host smart-13c939f7-4950-4f6b-a94a-206b00cbd654
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910169085 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din_no_pullup
_pulldown.910169085
Directory /workspace/16.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_random_long_reg_writes_reg_reads.3968732170
Short name T56
Test name
Test status
Simulation time 133553919 ps
CPU time 5.57 seconds
Started Jul 29 04:34:02 PM PDT 24
Finished Jul 29 04:34:08 PM PDT 24
Peak memory 198336 kb
Host smart-1dea708c-9d0e-45ad-9400-6331bf2b5052
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968732170 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_ra
ndom_long_reg_writes_reg_reads.3968732170
Directory /workspace/16.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/16.gpio_smoke.2899423966
Short name T441
Test name
Test status
Simulation time 360617566 ps
CPU time 0.81 seconds
Started Jul 29 04:34:13 PM PDT 24
Finished Jul 29 04:34:14 PM PDT 24
Peak memory 195660 kb
Host smart-141dc113-5b63-4a44-8bad-1e34aa36b8ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2899423966 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke.2899423966
Directory /workspace/16.gpio_smoke/latest

Test location /workspace/coverage/default/16.gpio_smoke_no_pullup_pulldown.2251900126
Short name T57
Test name
Test status
Simulation time 154283372 ps
CPU time 1.32 seconds
Started Jul 29 04:34:10 PM PDT 24
Finished Jul 29 04:34:11 PM PDT 24
Peak memory 197244 kb
Host smart-b48ebcce-4888-462c-8ac0-6667972c3dbb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251900126 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown.2251900126
Directory /workspace/16.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_stress_all.1597797946
Short name T626
Test name
Test status
Simulation time 5321148206 ps
CPU time 32.87 seconds
Started Jul 29 04:34:27 PM PDT 24
Finished Jul 29 04:35:00 PM PDT 24
Peak memory 198596 kb
Host smart-9e555d2b-0194-4262-afa8-dc2fa3ac4e1b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597797946 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.
gpio_stress_all.1597797946
Directory /workspace/16.gpio_stress_all/latest

Test location /workspace/coverage/default/16.gpio_stress_all_with_rand_reset.1509111382
Short name T64
Test name
Test status
Simulation time 66925440746 ps
CPU time 529.58 seconds
Started Jul 29 04:34:17 PM PDT 24
Finished Jul 29 04:43:07 PM PDT 24
Peak memory 198692 kb
Host smart-521e2b89-42c0-422a-ac4d-af8f37fde3c5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1509111382 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_stress_all_with_rand_reset.1509111382
Directory /workspace/16.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.gpio_alert_test.1865833639
Short name T324
Test name
Test status
Simulation time 9898561 ps
CPU time 0.55 seconds
Started Jul 29 04:34:04 PM PDT 24
Finished Jul 29 04:34:05 PM PDT 24
Peak memory 194328 kb
Host smart-f2daace3-1226-4ab0-9bce-bea24c0ffb71
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865833639 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_alert_test.1865833639
Directory /workspace/17.gpio_alert_test/latest

Test location /workspace/coverage/default/17.gpio_dout_din_regs_random_rw.313250591
Short name T445
Test name
Test status
Simulation time 133277156 ps
CPU time 0.88 seconds
Started Jul 29 04:34:10 PM PDT 24
Finished Jul 29 04:34:11 PM PDT 24
Peak memory 197116 kb
Host smart-95fb524c-ebf2-4851-ac14-94da99010e61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=313250591 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_dout_din_regs_random_rw.313250591
Directory /workspace/17.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/17.gpio_filter_stress.2316645148
Short name T316
Test name
Test status
Simulation time 360581920 ps
CPU time 19.14 seconds
Started Jul 29 04:34:05 PM PDT 24
Finished Jul 29 04:34:24 PM PDT 24
Peak memory 197312 kb
Host smart-13a2514e-6d5d-4cdf-a117-cbac8b9e4146
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316645148 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_filter_stre
ss.2316645148
Directory /workspace/17.gpio_filter_stress/latest

Test location /workspace/coverage/default/17.gpio_full_random.2820797667
Short name T455
Test name
Test status
Simulation time 136564012 ps
CPU time 0.74 seconds
Started Jul 29 04:34:09 PM PDT 24
Finished Jul 29 04:34:10 PM PDT 24
Peak memory 195772 kb
Host smart-aecb327a-b07b-41f0-bd8a-9d3255c414ee
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820797667 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_full_random.2820797667
Directory /workspace/17.gpio_full_random/latest

Test location /workspace/coverage/default/17.gpio_intr_rand_pgm.3072804092
Short name T442
Test name
Test status
Simulation time 86203811 ps
CPU time 1.23 seconds
Started Jul 29 04:34:10 PM PDT 24
Finished Jul 29 04:34:12 PM PDT 24
Peak memory 196588 kb
Host smart-9ea59c35-352b-43a8-b1f1-c2dcb62d70aa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072804092 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_intr_rand_pgm.3072804092
Directory /workspace/17.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/17.gpio_intr_with_filter_rand_intr_event.3145642614
Short name T182
Test name
Test status
Simulation time 71696719 ps
CPU time 0.96 seconds
Started Jul 29 04:34:04 PM PDT 24
Finished Jul 29 04:34:05 PM PDT 24
Peak memory 196340 kb
Host smart-a69d0342-06a0-4fa6-ba92-83455e34bf7d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145642614 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.gpio_intr_with_filter_rand_intr_event.3145642614
Directory /workspace/17.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/17.gpio_rand_intr_trigger.3983771421
Short name T168
Test name
Test status
Simulation time 350750173 ps
CPU time 1.27 seconds
Started Jul 29 04:34:11 PM PDT 24
Finished Jul 29 04:34:12 PM PDT 24
Peak memory 197968 kb
Host smart-9672dacd-ef3f-46d2-bfcb-2c7be4f5d65b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983771421 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_rand_intr_trigger
.3983771421
Directory /workspace/17.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din.3362291369
Short name T26
Test name
Test status
Simulation time 145857477 ps
CPU time 1.3 seconds
Started Jul 29 04:34:05 PM PDT 24
Finished Jul 29 04:34:07 PM PDT 24
Peak memory 197340 kb
Host smart-34404ae6-a2de-4412-943f-b98929f3b9b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3362291369 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din.3362291369
Directory /workspace/17.gpio_random_dout_din/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din_no_pullup_pulldown.3211908315
Short name T169
Test name
Test status
Simulation time 95789304 ps
CPU time 0.94 seconds
Started Jul 29 04:34:13 PM PDT 24
Finished Jul 29 04:34:14 PM PDT 24
Peak memory 196404 kb
Host smart-39e16f3b-18f5-46fb-8771-4d89b718bf2d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211908315 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din_no_pullu
p_pulldown.3211908315
Directory /workspace/17.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_random_long_reg_writes_reg_reads.877526866
Short name T580
Test name
Test status
Simulation time 456268462 ps
CPU time 3.5 seconds
Started Jul 29 04:34:06 PM PDT 24
Finished Jul 29 04:34:09 PM PDT 24
Peak memory 198268 kb
Host smart-324186e5-d72d-4b79-bb6c-d38af07af646
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877526866 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_ran
dom_long_reg_writes_reg_reads.877526866
Directory /workspace/17.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/17.gpio_smoke.2663760263
Short name T537
Test name
Test status
Simulation time 29933583 ps
CPU time 0.89 seconds
Started Jul 29 04:34:00 PM PDT 24
Finished Jul 29 04:34:01 PM PDT 24
Peak memory 196824 kb
Host smart-154b6b9e-4212-4022-8fb4-89db026cc859
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2663760263 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke.2663760263
Directory /workspace/17.gpio_smoke/latest

Test location /workspace/coverage/default/17.gpio_smoke_no_pullup_pulldown.2002012976
Short name T98
Test name
Test status
Simulation time 41740456 ps
CPU time 1.28 seconds
Started Jul 29 04:34:18 PM PDT 24
Finished Jul 29 04:34:20 PM PDT 24
Peak memory 197028 kb
Host smart-3d2abf8e-6f48-4bc2-91b8-eb366ac493e4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002012976 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown.2002012976
Directory /workspace/17.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_stress_all.3679115933
Short name T376
Test name
Test status
Simulation time 69091467942 ps
CPU time 173.9 seconds
Started Jul 29 04:34:08 PM PDT 24
Finished Jul 29 04:37:02 PM PDT 24
Peak memory 198556 kb
Host smart-a486012c-2625-463a-bfbf-67eb54cf9910
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679115933 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.
gpio_stress_all.3679115933
Directory /workspace/17.gpio_stress_all/latest

Test location /workspace/coverage/default/18.gpio_alert_test.3555149554
Short name T638
Test name
Test status
Simulation time 15028704 ps
CPU time 0.59 seconds
Started Jul 29 04:34:24 PM PDT 24
Finished Jul 29 04:34:25 PM PDT 24
Peak memory 195336 kb
Host smart-f80f4ac1-839a-40e4-a7c7-a1f7b5a904b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555149554 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_alert_test.3555149554
Directory /workspace/18.gpio_alert_test/latest

Test location /workspace/coverage/default/18.gpio_dout_din_regs_random_rw.1645666763
Short name T659
Test name
Test status
Simulation time 136444752 ps
CPU time 0.85 seconds
Started Jul 29 04:34:14 PM PDT 24
Finished Jul 29 04:34:15 PM PDT 24
Peak memory 195740 kb
Host smart-9a671172-3b06-4146-8e99-1c438c569e5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1645666763 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_dout_din_regs_random_rw.1645666763
Directory /workspace/18.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/18.gpio_filter_stress.1513305464
Short name T610
Test name
Test status
Simulation time 206863151 ps
CPU time 10.55 seconds
Started Jul 29 04:34:04 PM PDT 24
Finished Jul 29 04:34:15 PM PDT 24
Peak memory 197180 kb
Host smart-c1b19aa2-00fc-414c-9366-607a148c1ae0
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513305464 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_filter_stre
ss.1513305464
Directory /workspace/18.gpio_filter_stress/latest

Test location /workspace/coverage/default/18.gpio_full_random.3764019301
Short name T407
Test name
Test status
Simulation time 277722009 ps
CPU time 0.97 seconds
Started Jul 29 04:34:09 PM PDT 24
Finished Jul 29 04:34:10 PM PDT 24
Peak memory 197040 kb
Host smart-3d941d62-6698-4ef4-8249-d0b8870836ab
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764019301 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_full_random.3764019301
Directory /workspace/18.gpio_full_random/latest

Test location /workspace/coverage/default/18.gpio_intr_rand_pgm.1942082476
Short name T30
Test name
Test status
Simulation time 44122565 ps
CPU time 0.93 seconds
Started Jul 29 04:34:10 PM PDT 24
Finished Jul 29 04:34:11 PM PDT 24
Peak memory 196500 kb
Host smart-c379dec6-35ac-4a15-a41c-2d1ba159700a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942082476 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_intr_rand_pgm.1942082476
Directory /workspace/18.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/18.gpio_intr_with_filter_rand_intr_event.25222875
Short name T251
Test name
Test status
Simulation time 358080370 ps
CPU time 3.28 seconds
Started Jul 29 04:34:11 PM PDT 24
Finished Jul 29 04:34:14 PM PDT 24
Peak memory 198588 kb
Host smart-5c9baaba-ea23-4703-9de6-0cf2e08d5349
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25222875 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 18.gpio_intr_with_filter_rand_intr_event.25222875
Directory /workspace/18.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/18.gpio_rand_intr_trigger.3116294919
Short name T190
Test name
Test status
Simulation time 783217354 ps
CPU time 2.93 seconds
Started Jul 29 04:34:11 PM PDT 24
Finished Jul 29 04:34:14 PM PDT 24
Peak memory 197616 kb
Host smart-ad24533d-a8df-4bbb-882d-0072ccab7f54
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116294919 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_rand_intr_trigger
.3116294919
Directory /workspace/18.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din.2034380719
Short name T693
Test name
Test status
Simulation time 32903060 ps
CPU time 1.19 seconds
Started Jul 29 04:34:09 PM PDT 24
Finished Jul 29 04:34:10 PM PDT 24
Peak memory 196956 kb
Host smart-251dfb20-1543-4852-8ff7-0d23623503dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2034380719 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din.2034380719
Directory /workspace/18.gpio_random_dout_din/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din_no_pullup_pulldown.3497029661
Short name T539
Test name
Test status
Simulation time 163092714 ps
CPU time 1.01 seconds
Started Jul 29 04:34:19 PM PDT 24
Finished Jul 29 04:34:20 PM PDT 24
Peak memory 196996 kb
Host smart-d9b67966-d17f-492d-ab0f-ae3e567973fb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497029661 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din_no_pullu
p_pulldown.3497029661
Directory /workspace/18.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_random_long_reg_writes_reg_reads.1057413980
Short name T121
Test name
Test status
Simulation time 345509535 ps
CPU time 4.11 seconds
Started Jul 29 04:34:10 PM PDT 24
Finished Jul 29 04:34:14 PM PDT 24
Peak memory 198344 kb
Host smart-43c88d6d-ae27-4ea0-b8ea-ddad46f6deb6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057413980 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_ra
ndom_long_reg_writes_reg_reads.1057413980
Directory /workspace/18.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/18.gpio_smoke.3141990379
Short name T663
Test name
Test status
Simulation time 361270546 ps
CPU time 1.23 seconds
Started Jul 29 04:33:57 PM PDT 24
Finished Jul 29 04:33:59 PM PDT 24
Peak memory 197028 kb
Host smart-d99d1b18-421a-4f3a-83ff-6bd3047bc55f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3141990379 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke.3141990379
Directory /workspace/18.gpio_smoke/latest

Test location /workspace/coverage/default/18.gpio_smoke_no_pullup_pulldown.3239600655
Short name T645
Test name
Test status
Simulation time 27970112 ps
CPU time 0.8 seconds
Started Jul 29 04:34:15 PM PDT 24
Finished Jul 29 04:34:16 PM PDT 24
Peak memory 196368 kb
Host smart-8048f76c-95aa-4e98-8428-98b2d1dffd48
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239600655 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown.3239600655
Directory /workspace/18.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_stress_all.1660517099
Short name T238
Test name
Test status
Simulation time 27811363390 ps
CPU time 167.72 seconds
Started Jul 29 04:34:10 PM PDT 24
Finished Jul 29 04:36:58 PM PDT 24
Peak memory 198588 kb
Host smart-655809c5-1950-44ec-9850-87aadd8547de
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660517099 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.
gpio_stress_all.1660517099
Directory /workspace/18.gpio_stress_all/latest

Test location /workspace/coverage/default/18.gpio_stress_all_with_rand_reset.1131207357
Short name T433
Test name
Test status
Simulation time 73770567349 ps
CPU time 476.95 seconds
Started Jul 29 04:34:05 PM PDT 24
Finished Jul 29 04:42:02 PM PDT 24
Peak memory 199080 kb
Host smart-f125464a-074c-4ae4-810f-c50d7560ee83
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1131207357 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_stress_all_with_rand_reset.1131207357
Directory /workspace/18.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.gpio_alert_test.1457461978
Short name T418
Test name
Test status
Simulation time 11307087 ps
CPU time 0.56 seconds
Started Jul 29 04:34:03 PM PDT 24
Finished Jul 29 04:34:04 PM PDT 24
Peak memory 194196 kb
Host smart-e02ae3c3-4e33-4619-990d-5bf97583ce7b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457461978 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_alert_test.1457461978
Directory /workspace/19.gpio_alert_test/latest

Test location /workspace/coverage/default/19.gpio_dout_din_regs_random_rw.3365110667
Short name T186
Test name
Test status
Simulation time 42072702 ps
CPU time 0.9 seconds
Started Jul 29 04:34:12 PM PDT 24
Finished Jul 29 04:34:13 PM PDT 24
Peak memory 196172 kb
Host smart-2c17695d-e5fe-44cf-b401-c9e2654643c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3365110667 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_dout_din_regs_random_rw.3365110667
Directory /workspace/19.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/19.gpio_filter_stress.4066391524
Short name T682
Test name
Test status
Simulation time 763134697 ps
CPU time 13.21 seconds
Started Jul 29 04:34:06 PM PDT 24
Finished Jul 29 04:34:20 PM PDT 24
Peak memory 198416 kb
Host smart-d31eb3c1-6d01-4974-bbbc-961880de65d2
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066391524 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_filter_stre
ss.4066391524
Directory /workspace/19.gpio_filter_stress/latest

Test location /workspace/coverage/default/19.gpio_full_random.1423177610
Short name T414
Test name
Test status
Simulation time 112775419 ps
CPU time 0.78 seconds
Started Jul 29 04:34:09 PM PDT 24
Finished Jul 29 04:34:10 PM PDT 24
Peak memory 196064 kb
Host smart-1f5853a9-e354-4435-83cd-09c50dc41b5c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423177610 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_full_random.1423177610
Directory /workspace/19.gpio_full_random/latest

Test location /workspace/coverage/default/19.gpio_intr_rand_pgm.1844913210
Short name T424
Test name
Test status
Simulation time 26935257 ps
CPU time 0.7 seconds
Started Jul 29 04:34:22 PM PDT 24
Finished Jul 29 04:34:23 PM PDT 24
Peak memory 195388 kb
Host smart-85f73385-c5ba-4013-bcba-78a39a086f0e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844913210 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_intr_rand_pgm.1844913210
Directory /workspace/19.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/19.gpio_intr_with_filter_rand_intr_event.2414738415
Short name T684
Test name
Test status
Simulation time 58135161 ps
CPU time 1.32 seconds
Started Jul 29 04:34:10 PM PDT 24
Finished Jul 29 04:34:11 PM PDT 24
Peak memory 196800 kb
Host smart-d48e2288-24fe-49e8-a030-5af49921a6aa
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414738415 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 19.gpio_intr_with_filter_rand_intr_event.2414738415
Directory /workspace/19.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/19.gpio_rand_intr_trigger.3521273263
Short name T335
Test name
Test status
Simulation time 162035881 ps
CPU time 2.01 seconds
Started Jul 29 04:34:09 PM PDT 24
Finished Jul 29 04:34:12 PM PDT 24
Peak memory 196360 kb
Host smart-2b0a7cbd-f97c-4dc3-9dcf-563bfdcc9fc4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521273263 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_rand_intr_trigger
.3521273263
Directory /workspace/19.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din.27020346
Short name T622
Test name
Test status
Simulation time 32542950 ps
CPU time 1.27 seconds
Started Jul 29 04:34:11 PM PDT 24
Finished Jul 29 04:34:13 PM PDT 24
Peak memory 196256 kb
Host smart-da7c0850-acef-46b3-b28e-ec386bd5b99e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27020346 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din.27020346
Directory /workspace/19.gpio_random_dout_din/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din_no_pullup_pulldown.1899319208
Short name T258
Test name
Test status
Simulation time 25695036 ps
CPU time 0.62 seconds
Started Jul 29 04:34:12 PM PDT 24
Finished Jul 29 04:34:13 PM PDT 24
Peak memory 195356 kb
Host smart-3a8c0778-8e67-498e-b749-089ced276564
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899319208 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din_no_pullu
p_pulldown.1899319208
Directory /workspace/19.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_random_long_reg_writes_reg_reads.1760039826
Short name T215
Test name
Test status
Simulation time 380922815 ps
CPU time 3.89 seconds
Started Jul 29 04:34:09 PM PDT 24
Finished Jul 29 04:34:13 PM PDT 24
Peak memory 198344 kb
Host smart-ad7128aa-ccec-4c11-bebf-ad5b5ab2a7f6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760039826 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_ra
ndom_long_reg_writes_reg_reads.1760039826
Directory /workspace/19.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/19.gpio_smoke.1557662913
Short name T716
Test name
Test status
Simulation time 64256204 ps
CPU time 1.15 seconds
Started Jul 29 04:34:13 PM PDT 24
Finished Jul 29 04:34:15 PM PDT 24
Peak memory 196632 kb
Host smart-5ff6b0bf-c1ab-49e4-84a8-8a0db7a98edb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1557662913 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke.1557662913
Directory /workspace/19.gpio_smoke/latest

Test location /workspace/coverage/default/19.gpio_smoke_no_pullup_pulldown.117689590
Short name T216
Test name
Test status
Simulation time 186493900 ps
CPU time 1.31 seconds
Started Jul 29 04:34:10 PM PDT 24
Finished Jul 29 04:34:11 PM PDT 24
Peak memory 197236 kb
Host smart-b57d382b-0afe-4cdc-be7b-ccfeb44cebdf
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117689590 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown.117689590
Directory /workspace/19.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_stress_all.121216596
Short name T427
Test name
Test status
Simulation time 7252268426 ps
CPU time 185.29 seconds
Started Jul 29 04:34:18 PM PDT 24
Finished Jul 29 04:37:24 PM PDT 24
Peak memory 198500 kb
Host smart-8f9596e6-87b8-41f1-9187-348dc60615e6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121216596 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.g
pio_stress_all.121216596
Directory /workspace/19.gpio_stress_all/latest

Test location /workspace/coverage/default/2.gpio_alert_test.164424055
Short name T615
Test name
Test status
Simulation time 56241253 ps
CPU time 0.56 seconds
Started Jul 29 04:33:34 PM PDT 24
Finished Jul 29 04:33:34 PM PDT 24
Peak memory 194556 kb
Host smart-3fee922b-c4b7-454b-8c77-8133ba7d9d5c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164424055 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_alert_test.164424055
Directory /workspace/2.gpio_alert_test/latest

Test location /workspace/coverage/default/2.gpio_dout_din_regs_random_rw.4225614851
Short name T562
Test name
Test status
Simulation time 50753435 ps
CPU time 0.6 seconds
Started Jul 29 04:33:33 PM PDT 24
Finished Jul 29 04:33:33 PM PDT 24
Peak memory 194416 kb
Host smart-4599b9b8-c0d4-44c3-a3eb-c9ef87b35caa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4225614851 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_dout_din_regs_random_rw.4225614851
Directory /workspace/2.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/2.gpio_filter_stress.2969293938
Short name T502
Test name
Test status
Simulation time 595004370 ps
CPU time 7.56 seconds
Started Jul 29 04:33:38 PM PDT 24
Finished Jul 29 04:33:46 PM PDT 24
Peak memory 198292 kb
Host smart-3b49ae95-2843-4c6e-be1c-cadda6f7d2e7
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969293938 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_filter_stres
s.2969293938
Directory /workspace/2.gpio_filter_stress/latest

Test location /workspace/coverage/default/2.gpio_full_random.3948035457
Short name T466
Test name
Test status
Simulation time 27109266 ps
CPU time 0.66 seconds
Started Jul 29 04:33:41 PM PDT 24
Finished Jul 29 04:33:42 PM PDT 24
Peak memory 195564 kb
Host smart-e683f2a2-3108-4126-a4d9-3c96e9f91a25
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948035457 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_full_random.3948035457
Directory /workspace/2.gpio_full_random/latest

Test location /workspace/coverage/default/2.gpio_intr_rand_pgm.836582943
Short name T294
Test name
Test status
Simulation time 44090594 ps
CPU time 0.91 seconds
Started Jul 29 04:33:31 PM PDT 24
Finished Jul 29 04:33:32 PM PDT 24
Peak memory 196112 kb
Host smart-80fa1470-8c0f-476f-a5ef-abc1a5f3c4da
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836582943 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_intr_rand_pgm.836582943
Directory /workspace/2.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/2.gpio_intr_with_filter_rand_intr_event.2881238977
Short name T346
Test name
Test status
Simulation time 145108124 ps
CPU time 1.57 seconds
Started Jul 29 04:33:31 PM PDT 24
Finished Jul 29 04:33:32 PM PDT 24
Peak memory 197016 kb
Host smart-d94a9867-0371-46a1-9f81-9b55550dd174
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881238977 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.gpio_intr_with_filter_rand_intr_event.2881238977
Directory /workspace/2.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/2.gpio_rand_intr_trigger.2233661557
Short name T396
Test name
Test status
Simulation time 1207626264 ps
CPU time 3.18 seconds
Started Jul 29 04:33:28 PM PDT 24
Finished Jul 29 04:33:31 PM PDT 24
Peak memory 197384 kb
Host smart-d49ae26d-5903-4855-b350-6feabac59428
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233661557 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_rand_intr_trigger.
2233661557
Directory /workspace/2.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din.3936239809
Short name T243
Test name
Test status
Simulation time 25027629 ps
CPU time 0.94 seconds
Started Jul 29 04:33:27 PM PDT 24
Finished Jul 29 04:33:28 PM PDT 24
Peak memory 196340 kb
Host smart-00d2f8f3-a239-489b-8db4-e4a904ac9c91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936239809 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din.3936239809
Directory /workspace/2.gpio_random_dout_din/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din_no_pullup_pulldown.3069106286
Short name T647
Test name
Test status
Simulation time 45538760 ps
CPU time 0.97 seconds
Started Jul 29 04:33:34 PM PDT 24
Finished Jul 29 04:33:35 PM PDT 24
Peak memory 196428 kb
Host smart-b949d68d-d116-49c9-84c8-5dde29ad3b2f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069106286 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din_no_pullup
_pulldown.3069106286
Directory /workspace/2.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_random_long_reg_writes_reg_reads.1901192623
Short name T188
Test name
Test status
Simulation time 102143155 ps
CPU time 2.55 seconds
Started Jul 29 04:33:33 PM PDT 24
Finished Jul 29 04:33:36 PM PDT 24
Peak memory 198388 kb
Host smart-71a94a8c-6469-46cd-a99d-bee9f68cf353
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901192623 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_ran
dom_long_reg_writes_reg_reads.1901192623
Directory /workspace/2.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/2.gpio_sec_cm.2526295587
Short name T44
Test name
Test status
Simulation time 136862845 ps
CPU time 0.78 seconds
Started Jul 29 04:33:34 PM PDT 24
Finished Jul 29 04:33:35 PM PDT 24
Peak memory 214124 kb
Host smart-f6aa2cc4-72aa-4696-b628-7bf5935709f9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526295587 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_sec_cm.2526295587
Directory /workspace/2.gpio_sec_cm/latest

Test location /workspace/coverage/default/2.gpio_smoke.1315340489
Short name T228
Test name
Test status
Simulation time 230209284 ps
CPU time 1.13 seconds
Started Jul 29 04:33:28 PM PDT 24
Finished Jul 29 04:33:29 PM PDT 24
Peak memory 196012 kb
Host smart-5a66c4d3-d115-45eb-96f2-0a5d5dca38f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1315340489 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke.1315340489
Directory /workspace/2.gpio_smoke/latest

Test location /workspace/coverage/default/2.gpio_smoke_no_pullup_pulldown.3319634286
Short name T280
Test name
Test status
Simulation time 355206563 ps
CPU time 1.54 seconds
Started Jul 29 04:33:24 PM PDT 24
Finished Jul 29 04:33:26 PM PDT 24
Peak memory 198372 kb
Host smart-5b2271e3-bfbc-4191-ab0f-265d1d116e2f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319634286 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown.3319634286
Directory /workspace/2.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_stress_all.3736313929
Short name T674
Test name
Test status
Simulation time 12005581975 ps
CPU time 160.87 seconds
Started Jul 29 04:33:58 PM PDT 24
Finished Jul 29 04:36:39 PM PDT 24
Peak memory 198580 kb
Host smart-eaf8dc75-0c9b-4127-ab5c-df6ee9060261
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736313929 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.g
pio_stress_all.3736313929
Directory /workspace/2.gpio_stress_all/latest

Test location /workspace/coverage/default/2.gpio_stress_all_with_rand_reset.2040116990
Short name T492
Test name
Test status
Simulation time 31140776144 ps
CPU time 917 seconds
Started Jul 29 04:33:32 PM PDT 24
Finished Jul 29 04:48:49 PM PDT 24
Peak memory 198812 kb
Host smart-dd67ee6a-d309-4b19-a96c-7b386597766b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2040116990 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_stress_all_with_rand_reset.2040116990
Directory /workspace/2.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.gpio_alert_test.2757959175
Short name T286
Test name
Test status
Simulation time 108969719 ps
CPU time 0.58 seconds
Started Jul 29 04:34:10 PM PDT 24
Finished Jul 29 04:34:11 PM PDT 24
Peak memory 195164 kb
Host smart-2cd692d0-1a35-45b8-9ea3-07cfe459573a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757959175 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_alert_test.2757959175
Directory /workspace/20.gpio_alert_test/latest

Test location /workspace/coverage/default/20.gpio_dout_din_regs_random_rw.1049696573
Short name T126
Test name
Test status
Simulation time 47633083 ps
CPU time 0.91 seconds
Started Jul 29 04:34:09 PM PDT 24
Finished Jul 29 04:34:10 PM PDT 24
Peak memory 196876 kb
Host smart-e8181fd7-8312-42f0-a49a-a9ac70654d7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1049696573 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_dout_din_regs_random_rw.1049696573
Directory /workspace/20.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/20.gpio_filter_stress.1066260654
Short name T189
Test name
Test status
Simulation time 685876653 ps
CPU time 17.71 seconds
Started Jul 29 04:34:05 PM PDT 24
Finished Jul 29 04:34:23 PM PDT 24
Peak memory 198284 kb
Host smart-68cf8667-ab78-4b08-8f82-bda8c71c49b6
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066260654 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_filter_stre
ss.1066260654
Directory /workspace/20.gpio_filter_stress/latest

Test location /workspace/coverage/default/20.gpio_full_random.2813412146
Short name T151
Test name
Test status
Simulation time 124967237 ps
CPU time 0.86 seconds
Started Jul 29 04:34:21 PM PDT 24
Finished Jul 29 04:34:22 PM PDT 24
Peak memory 196340 kb
Host smart-5c3b522c-de05-411c-9664-944c5ddea520
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813412146 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_full_random.2813412146
Directory /workspace/20.gpio_full_random/latest

Test location /workspace/coverage/default/20.gpio_intr_rand_pgm.1014169560
Short name T196
Test name
Test status
Simulation time 530927583 ps
CPU time 0.95 seconds
Started Jul 29 04:34:13 PM PDT 24
Finished Jul 29 04:34:15 PM PDT 24
Peak memory 197100 kb
Host smart-4c9b4487-d4cc-4330-87f4-86adde66db9c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014169560 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_intr_rand_pgm.1014169560
Directory /workspace/20.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/20.gpio_intr_with_filter_rand_intr_event.1684785422
Short name T533
Test name
Test status
Simulation time 26135906 ps
CPU time 1.11 seconds
Started Jul 29 04:34:17 PM PDT 24
Finished Jul 29 04:34:18 PM PDT 24
Peak memory 198312 kb
Host smart-2bd2be9b-0ad5-4f40-af38-047d8edb10b7
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684785422 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 20.gpio_intr_with_filter_rand_intr_event.1684785422
Directory /workspace/20.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/20.gpio_rand_intr_trigger.3166971388
Short name T592
Test name
Test status
Simulation time 84252960 ps
CPU time 1.9 seconds
Started Jul 29 04:34:13 PM PDT 24
Finished Jul 29 04:34:15 PM PDT 24
Peak memory 197312 kb
Host smart-e6122595-e6e2-43c4-81c6-64ac3629f631
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166971388 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_rand_intr_trigger
.3166971388
Directory /workspace/20.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din.2730286888
Short name T116
Test name
Test status
Simulation time 31335612 ps
CPU time 1.16 seconds
Started Jul 29 04:34:06 PM PDT 24
Finished Jul 29 04:34:07 PM PDT 24
Peak memory 198448 kb
Host smart-f10e4c19-a452-4bfd-977d-ed992c877ffe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730286888 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din.2730286888
Directory /workspace/20.gpio_random_dout_din/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din_no_pullup_pulldown.4157848381
Short name T290
Test name
Test status
Simulation time 175742488 ps
CPU time 1.16 seconds
Started Jul 29 04:34:25 PM PDT 24
Finished Jul 29 04:34:26 PM PDT 24
Peak memory 196444 kb
Host smart-fb81e7b8-10dc-488d-b5e3-72e37010a626
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157848381 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din_no_pullu
p_pulldown.4157848381
Directory /workspace/20.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_random_long_reg_writes_reg_reads.2981757215
Short name T568
Test name
Test status
Simulation time 2197964326 ps
CPU time 6.26 seconds
Started Jul 29 04:34:24 PM PDT 24
Finished Jul 29 04:34:31 PM PDT 24
Peak memory 198792 kb
Host smart-98b8fc38-a626-405e-84cf-f9c32a682acd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981757215 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_ra
ndom_long_reg_writes_reg_reads.2981757215
Directory /workspace/20.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/20.gpio_smoke.1000674948
Short name T400
Test name
Test status
Simulation time 133463363 ps
CPU time 1.18 seconds
Started Jul 29 04:34:12 PM PDT 24
Finished Jul 29 04:34:13 PM PDT 24
Peak memory 196664 kb
Host smart-6eb7eb1f-a48b-4836-8766-b9814cbfda93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000674948 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke.1000674948
Directory /workspace/20.gpio_smoke/latest

Test location /workspace/coverage/default/20.gpio_smoke_no_pullup_pulldown.1671804896
Short name T564
Test name
Test status
Simulation time 189626191 ps
CPU time 1.35 seconds
Started Jul 29 04:34:12 PM PDT 24
Finished Jul 29 04:34:13 PM PDT 24
Peak memory 197252 kb
Host smart-888db4e1-8f80-4794-b917-438006669234
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671804896 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown.1671804896
Directory /workspace/20.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_stress_all.3576093279
Short name T456
Test name
Test status
Simulation time 5231550580 ps
CPU time 65.84 seconds
Started Jul 29 04:34:10 PM PDT 24
Finished Jul 29 04:35:16 PM PDT 24
Peak memory 198600 kb
Host smart-8967cfeb-8b5f-4541-92be-a4fe705112a4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576093279 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.
gpio_stress_all.3576093279
Directory /workspace/20.gpio_stress_all/latest

Test location /workspace/coverage/default/21.gpio_alert_test.142362644
Short name T356
Test name
Test status
Simulation time 36033003 ps
CPU time 0.53 seconds
Started Jul 29 04:34:07 PM PDT 24
Finished Jul 29 04:34:08 PM PDT 24
Peak memory 194948 kb
Host smart-5a2d5c18-9374-4d40-931d-388ed7c340eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142362644 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_alert_test.142362644
Directory /workspace/21.gpio_alert_test/latest

Test location /workspace/coverage/default/21.gpio_dout_din_regs_random_rw.1945875976
Short name T233
Test name
Test status
Simulation time 30475730 ps
CPU time 0.81 seconds
Started Jul 29 04:34:42 PM PDT 24
Finished Jul 29 04:34:43 PM PDT 24
Peak memory 196740 kb
Host smart-0689764a-f786-4184-87ad-5821e22ceb3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1945875976 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_dout_din_regs_random_rw.1945875976
Directory /workspace/21.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/21.gpio_filter_stress.1945380130
Short name T439
Test name
Test status
Simulation time 1438585935 ps
CPU time 9.87 seconds
Started Jul 29 04:34:12 PM PDT 24
Finished Jul 29 04:34:22 PM PDT 24
Peak memory 195916 kb
Host smart-a76d3b13-123f-4972-bf63-4c914bcfe34b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945380130 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_filter_stre
ss.1945380130
Directory /workspace/21.gpio_filter_stress/latest

Test location /workspace/coverage/default/21.gpio_full_random.711849999
Short name T394
Test name
Test status
Simulation time 29137337 ps
CPU time 0.67 seconds
Started Jul 29 04:34:17 PM PDT 24
Finished Jul 29 04:34:18 PM PDT 24
Peak memory 194748 kb
Host smart-0e27c188-6596-4a98-96c1-2221762e75e0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711849999 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_full_random.711849999
Directory /workspace/21.gpio_full_random/latest

Test location /workspace/coverage/default/21.gpio_intr_rand_pgm.2212793938
Short name T385
Test name
Test status
Simulation time 28661546 ps
CPU time 0.71 seconds
Started Jul 29 04:34:27 PM PDT 24
Finished Jul 29 04:34:28 PM PDT 24
Peak memory 194752 kb
Host smart-5e6d49b0-1c34-4a0a-947f-e2648a9e42fa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212793938 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_intr_rand_pgm.2212793938
Directory /workspace/21.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/21.gpio_intr_with_filter_rand_intr_event.2732796270
Short name T489
Test name
Test status
Simulation time 337984471 ps
CPU time 2.37 seconds
Started Jul 29 04:34:14 PM PDT 24
Finished Jul 29 04:34:17 PM PDT 24
Peak memory 198432 kb
Host smart-f9ccad5f-4ad1-4a41-9f39-168bbc87c172
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732796270 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 21.gpio_intr_with_filter_rand_intr_event.2732796270
Directory /workspace/21.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/21.gpio_rand_intr_trigger.2475031465
Short name T435
Test name
Test status
Simulation time 157786197 ps
CPU time 1.77 seconds
Started Jul 29 04:34:10 PM PDT 24
Finished Jul 29 04:34:12 PM PDT 24
Peak memory 196540 kb
Host smart-31923193-cf9c-4d2c-a814-75f0ef86d378
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475031465 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_rand_intr_trigger
.2475031465
Directory /workspace/21.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din.2096680931
Short name T305
Test name
Test status
Simulation time 98376529 ps
CPU time 0.83 seconds
Started Jul 29 04:34:09 PM PDT 24
Finished Jul 29 04:34:10 PM PDT 24
Peak memory 197488 kb
Host smart-610e6286-b1ba-46ca-b9ff-70bca87eb85d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096680931 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din.2096680931
Directory /workspace/21.gpio_random_dout_din/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din_no_pullup_pulldown.4265239626
Short name T417
Test name
Test status
Simulation time 32832847 ps
CPU time 0.93 seconds
Started Jul 29 04:34:28 PM PDT 24
Finished Jul 29 04:34:29 PM PDT 24
Peak memory 196368 kb
Host smart-dc9dcc5f-82f8-46e2-8e6f-6583d633db30
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265239626 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din_no_pullu
p_pulldown.4265239626
Directory /workspace/21.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_random_long_reg_writes_reg_reads.3012554413
Short name T504
Test name
Test status
Simulation time 208606275 ps
CPU time 3.04 seconds
Started Jul 29 04:34:19 PM PDT 24
Finished Jul 29 04:34:22 PM PDT 24
Peak memory 198332 kb
Host smart-20f6490b-c1b7-48c7-bd9d-8740d08d7baa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012554413 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_ra
ndom_long_reg_writes_reg_reads.3012554413
Directory /workspace/21.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/21.gpio_smoke.354136333
Short name T642
Test name
Test status
Simulation time 170445477 ps
CPU time 1.07 seconds
Started Jul 29 04:34:18 PM PDT 24
Finished Jul 29 04:34:19 PM PDT 24
Peak memory 196504 kb
Host smart-8c9932f8-f65c-42b9-9d16-f219055134af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=354136333 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke.354136333
Directory /workspace/21.gpio_smoke/latest

Test location /workspace/coverage/default/21.gpio_smoke_no_pullup_pulldown.4191657358
Short name T361
Test name
Test status
Simulation time 205837138 ps
CPU time 1.13 seconds
Started Jul 29 04:34:11 PM PDT 24
Finished Jul 29 04:34:12 PM PDT 24
Peak memory 196324 kb
Host smart-c166f0ae-6a5d-4107-a83a-2c77635b1ea6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191657358 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown.4191657358
Directory /workspace/21.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_stress_all.1941651754
Short name T207
Test name
Test status
Simulation time 10774156427 ps
CPU time 141.98 seconds
Started Jul 29 04:34:08 PM PDT 24
Finished Jul 29 04:36:30 PM PDT 24
Peak memory 198580 kb
Host smart-03c6f7e1-3d19-413d-8a79-7cc54d77d73b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941651754 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.
gpio_stress_all.1941651754
Directory /workspace/21.gpio_stress_all/latest

Test location /workspace/coverage/default/22.gpio_alert_test.3364238940
Short name T377
Test name
Test status
Simulation time 38590245 ps
CPU time 0.57 seconds
Started Jul 29 04:34:25 PM PDT 24
Finished Jul 29 04:34:26 PM PDT 24
Peak memory 194924 kb
Host smart-7078faf0-6e28-49ad-ad73-7b6923230f65
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364238940 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_alert_test.3364238940
Directory /workspace/22.gpio_alert_test/latest

Test location /workspace/coverage/default/22.gpio_dout_din_regs_random_rw.2464912716
Short name T217
Test name
Test status
Simulation time 36786628 ps
CPU time 0.71 seconds
Started Jul 29 04:34:22 PM PDT 24
Finished Jul 29 04:34:23 PM PDT 24
Peak memory 196200 kb
Host smart-30c6bcc5-b672-4d35-94dd-76d39e720c3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464912716 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_dout_din_regs_random_rw.2464912716
Directory /workspace/22.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/22.gpio_filter_stress.1891228309
Short name T147
Test name
Test status
Simulation time 3177931308 ps
CPU time 21.59 seconds
Started Jul 29 04:34:28 PM PDT 24
Finished Jul 29 04:34:50 PM PDT 24
Peak memory 198468 kb
Host smart-0f7e1cf7-0628-4be1-881e-95e3fe421225
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891228309 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_filter_stre
ss.1891228309
Directory /workspace/22.gpio_filter_stress/latest

Test location /workspace/coverage/default/22.gpio_full_random.3182009769
Short name T342
Test name
Test status
Simulation time 51573239 ps
CPU time 0.65 seconds
Started Jul 29 04:34:15 PM PDT 24
Finished Jul 29 04:34:16 PM PDT 24
Peak memory 195052 kb
Host smart-ee906d6d-5978-439d-9d60-2f0cb2175976
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182009769 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_full_random.3182009769
Directory /workspace/22.gpio_full_random/latest

Test location /workspace/coverage/default/22.gpio_intr_rand_pgm.2653475170
Short name T284
Test name
Test status
Simulation time 176212566 ps
CPU time 1 seconds
Started Jul 29 04:34:12 PM PDT 24
Finished Jul 29 04:34:14 PM PDT 24
Peak memory 196180 kb
Host smart-2cb8e1fc-6405-42c4-9338-190df10a8857
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653475170 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_intr_rand_pgm.2653475170
Directory /workspace/22.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/22.gpio_intr_with_filter_rand_intr_event.620728895
Short name T702
Test name
Test status
Simulation time 137409084 ps
CPU time 0.93 seconds
Started Jul 29 04:34:23 PM PDT 24
Finished Jul 29 04:34:24 PM PDT 24
Peak memory 197196 kb
Host smart-61b309bc-fc88-46fe-b858-b563c32f83d0
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620728895 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 22.gpio_intr_with_filter_rand_intr_event.620728895
Directory /workspace/22.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/22.gpio_rand_intr_trigger.2507847660
Short name T426
Test name
Test status
Simulation time 83384417 ps
CPU time 1.21 seconds
Started Jul 29 04:34:12 PM PDT 24
Finished Jul 29 04:34:14 PM PDT 24
Peak memory 196788 kb
Host smart-d4aa7d9a-bb80-462e-a4f1-94be33b724dd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507847660 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_rand_intr_trigger
.2507847660
Directory /workspace/22.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din.3422921102
Short name T419
Test name
Test status
Simulation time 66572697 ps
CPU time 1.17 seconds
Started Jul 29 04:34:16 PM PDT 24
Finished Jul 29 04:34:18 PM PDT 24
Peak memory 196252 kb
Host smart-6972c9f9-5c6b-4839-b02d-914ccc27eb33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3422921102 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din.3422921102
Directory /workspace/22.gpio_random_dout_din/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din_no_pullup_pulldown.3487645732
Short name T263
Test name
Test status
Simulation time 23978719 ps
CPU time 0.98 seconds
Started Jul 29 04:34:11 PM PDT 24
Finished Jul 29 04:34:13 PM PDT 24
Peak memory 196372 kb
Host smart-7178a121-4af0-4393-b02e-d5eb822f02b3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487645732 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din_no_pullu
p_pulldown.3487645732
Directory /workspace/22.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_random_long_reg_writes_reg_reads.1398562935
Short name T344
Test name
Test status
Simulation time 199921648 ps
CPU time 4.33 seconds
Started Jul 29 04:34:10 PM PDT 24
Finished Jul 29 04:34:14 PM PDT 24
Peak memory 198348 kb
Host smart-7f9434be-dd54-419f-829c-7a7043a7a2b8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398562935 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_ra
ndom_long_reg_writes_reg_reads.1398562935
Directory /workspace/22.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/22.gpio_smoke.1120688362
Short name T178
Test name
Test status
Simulation time 42474968 ps
CPU time 1.22 seconds
Started Jul 29 04:34:17 PM PDT 24
Finished Jul 29 04:34:18 PM PDT 24
Peak memory 197208 kb
Host smart-22369505-a307-4140-983c-6c3192de4d65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1120688362 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke.1120688362
Directory /workspace/22.gpio_smoke/latest

Test location /workspace/coverage/default/22.gpio_smoke_no_pullup_pulldown.3700014066
Short name T600
Test name
Test status
Simulation time 50837634 ps
CPU time 1 seconds
Started Jul 29 04:34:18 PM PDT 24
Finished Jul 29 04:34:19 PM PDT 24
Peak memory 196892 kb
Host smart-708f606d-b4c5-4263-87d3-081344bccc33
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700014066 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown.3700014066
Directory /workspace/22.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_stress_all.1830440900
Short name T323
Test name
Test status
Simulation time 13373498594 ps
CPU time 143.85 seconds
Started Jul 29 04:34:12 PM PDT 24
Finished Jul 29 04:36:36 PM PDT 24
Peak memory 198572 kb
Host smart-bf011f24-ee90-4630-8781-da46e87786fc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830440900 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.
gpio_stress_all.1830440900
Directory /workspace/22.gpio_stress_all/latest

Test location /workspace/coverage/default/22.gpio_stress_all_with_rand_reset.3482774342
Short name T93
Test name
Test status
Simulation time 90360479927 ps
CPU time 2196.11 seconds
Started Jul 29 04:34:13 PM PDT 24
Finished Jul 29 05:10:50 PM PDT 24
Peak memory 198676 kb
Host smart-99027e31-b14c-4e3e-9f0b-5361016468fe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3482774342 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_stress_all_with_rand_reset.3482774342
Directory /workspace/22.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.gpio_alert_test.840744543
Short name T718
Test name
Test status
Simulation time 65311058 ps
CPU time 0.58 seconds
Started Jul 29 04:34:15 PM PDT 24
Finished Jul 29 04:34:15 PM PDT 24
Peak memory 195028 kb
Host smart-2117c6b5-e621-4e7c-82e5-126a36a91e4e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840744543 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_alert_test.840744543
Directory /workspace/23.gpio_alert_test/latest

Test location /workspace/coverage/default/23.gpio_dout_din_regs_random_rw.3725571771
Short name T547
Test name
Test status
Simulation time 33451693 ps
CPU time 0.66 seconds
Started Jul 29 04:34:29 PM PDT 24
Finished Jul 29 04:34:30 PM PDT 24
Peak memory 194428 kb
Host smart-d56b5724-b571-43d9-a2cd-6c72f9838d4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3725571771 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_dout_din_regs_random_rw.3725571771
Directory /workspace/23.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/23.gpio_filter_stress.2522275605
Short name T443
Test name
Test status
Simulation time 816518694 ps
CPU time 14.87 seconds
Started Jul 29 04:34:13 PM PDT 24
Finished Jul 29 04:34:28 PM PDT 24
Peak memory 197412 kb
Host smart-d2f8c1c1-4b9c-4c1b-bf09-2c540ab1396a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522275605 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_filter_stre
ss.2522275605
Directory /workspace/23.gpio_filter_stress/latest

Test location /workspace/coverage/default/23.gpio_full_random.3010762873
Short name T343
Test name
Test status
Simulation time 435466909 ps
CPU time 0.84 seconds
Started Jul 29 04:34:20 PM PDT 24
Finished Jul 29 04:34:21 PM PDT 24
Peak memory 196308 kb
Host smart-dba6c5dc-b504-4f43-9d22-bdad74751f2b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010762873 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_full_random.3010762873
Directory /workspace/23.gpio_full_random/latest

Test location /workspace/coverage/default/23.gpio_intr_rand_pgm.836798374
Short name T392
Test name
Test status
Simulation time 31875273 ps
CPU time 0.86 seconds
Started Jul 29 04:34:31 PM PDT 24
Finished Jul 29 04:34:32 PM PDT 24
Peak memory 197812 kb
Host smart-7666cf00-a5f9-4757-bde9-499a4d399a2d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836798374 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_intr_rand_pgm.836798374
Directory /workspace/23.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/23.gpio_intr_with_filter_rand_intr_event.1192512884
Short name T698
Test name
Test status
Simulation time 71508828 ps
CPU time 2.91 seconds
Started Jul 29 04:34:33 PM PDT 24
Finished Jul 29 04:34:36 PM PDT 24
Peak memory 198520 kb
Host smart-69187d54-4096-46b4-86a9-d9f2adb0ffa8
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192512884 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 23.gpio_intr_with_filter_rand_intr_event.1192512884
Directory /workspace/23.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/23.gpio_rand_intr_trigger.2170623538
Short name T515
Test name
Test status
Simulation time 77947117 ps
CPU time 1.64 seconds
Started Jul 29 04:34:26 PM PDT 24
Finished Jul 29 04:34:28 PM PDT 24
Peak memory 196400 kb
Host smart-eeb1a6d6-c7dd-4fd9-a89a-72c794e38a93
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170623538 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_rand_intr_trigger
.2170623538
Directory /workspace/23.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din.2403797834
Short name T450
Test name
Test status
Simulation time 241912011 ps
CPU time 1.12 seconds
Started Jul 29 04:34:22 PM PDT 24
Finished Jul 29 04:34:23 PM PDT 24
Peak memory 196488 kb
Host smart-9b6a0a67-f7d2-4fd9-aeb5-cb862c3ca36e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2403797834 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din.2403797834
Directory /workspace/23.gpio_random_dout_din/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din_no_pullup_pulldown.4138889508
Short name T250
Test name
Test status
Simulation time 24098257 ps
CPU time 0.76 seconds
Started Jul 29 04:34:22 PM PDT 24
Finished Jul 29 04:34:23 PM PDT 24
Peak memory 195764 kb
Host smart-f0160296-f898-4270-be5f-e30de4bb090b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138889508 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din_no_pullu
p_pulldown.4138889508
Directory /workspace/23.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_random_long_reg_writes_reg_reads.2170960648
Short name T463
Test name
Test status
Simulation time 929597274 ps
CPU time 4.02 seconds
Started Jul 29 04:34:25 PM PDT 24
Finished Jul 29 04:34:29 PM PDT 24
Peak memory 198308 kb
Host smart-6f12c568-fddb-4c6e-9998-7db3279ed620
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170960648 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_ra
ndom_long_reg_writes_reg_reads.2170960648
Directory /workspace/23.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/23.gpio_smoke.3588299333
Short name T621
Test name
Test status
Simulation time 73065818 ps
CPU time 1.26 seconds
Started Jul 29 04:34:22 PM PDT 24
Finished Jul 29 04:34:24 PM PDT 24
Peak memory 197164 kb
Host smart-9b1a5f43-c9cf-4cd1-8ac6-e489b86cd40a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3588299333 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke.3588299333
Directory /workspace/23.gpio_smoke/latest

Test location /workspace/coverage/default/23.gpio_smoke_no_pullup_pulldown.2187757994
Short name T461
Test name
Test status
Simulation time 52528516 ps
CPU time 1.12 seconds
Started Jul 29 04:34:29 PM PDT 24
Finished Jul 29 04:34:30 PM PDT 24
Peak memory 196096 kb
Host smart-0f911d2b-cb53-4a61-91a3-b5acee668a95
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187757994 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown.2187757994
Directory /workspace/23.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_stress_all.3097360883
Short name T102
Test name
Test status
Simulation time 34819674712 ps
CPU time 85.7 seconds
Started Jul 29 04:34:13 PM PDT 24
Finished Jul 29 04:35:39 PM PDT 24
Peak memory 198544 kb
Host smart-4b642649-ef64-4105-9516-08933d5e391a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097360883 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.
gpio_stress_all.3097360883
Directory /workspace/23.gpio_stress_all/latest

Test location /workspace/coverage/default/23.gpio_stress_all_with_rand_reset.4190827339
Short name T37
Test name
Test status
Simulation time 74739644697 ps
CPU time 449.93 seconds
Started Jul 29 04:34:24 PM PDT 24
Finished Jul 29 04:41:54 PM PDT 24
Peak memory 206864 kb
Host smart-194e776c-286b-4d02-a45e-a67de0d1632f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4190827339 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_stress_all_with_rand_reset.4190827339
Directory /workspace/23.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.gpio_alert_test.4286303099
Short name T338
Test name
Test status
Simulation time 104864569 ps
CPU time 0.62 seconds
Started Jul 29 04:34:31 PM PDT 24
Finished Jul 29 04:34:32 PM PDT 24
Peak memory 194476 kb
Host smart-7f386167-e157-41a3-9db7-89f4b06aec9a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286303099 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_alert_test.4286303099
Directory /workspace/24.gpio_alert_test/latest

Test location /workspace/coverage/default/24.gpio_dout_din_regs_random_rw.1699852659
Short name T311
Test name
Test status
Simulation time 24617497 ps
CPU time 0.61 seconds
Started Jul 29 04:34:12 PM PDT 24
Finished Jul 29 04:34:13 PM PDT 24
Peak memory 194300 kb
Host smart-98b1a5a8-6784-46dd-b1f1-fb8bc42304cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1699852659 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_dout_din_regs_random_rw.1699852659
Directory /workspace/24.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/24.gpio_filter_stress.1705539989
Short name T520
Test name
Test status
Simulation time 848595735 ps
CPU time 24.27 seconds
Started Jul 29 04:34:13 PM PDT 24
Finished Jul 29 04:34:37 PM PDT 24
Peak memory 197272 kb
Host smart-da908b2d-a001-4569-a02b-0f9e5938640c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705539989 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_filter_stre
ss.1705539989
Directory /workspace/24.gpio_filter_stress/latest

Test location /workspace/coverage/default/24.gpio_full_random.4060804867
Short name T500
Test name
Test status
Simulation time 65116195 ps
CPU time 0.85 seconds
Started Jul 29 04:34:30 PM PDT 24
Finished Jul 29 04:34:31 PM PDT 24
Peak memory 196360 kb
Host smart-e00ad4dc-b6af-42e7-b363-f9c487cc2fb0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060804867 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_full_random.4060804867
Directory /workspace/24.gpio_full_random/latest

Test location /workspace/coverage/default/24.gpio_intr_rand_pgm.2056646179
Short name T512
Test name
Test status
Simulation time 61631908 ps
CPU time 0.77 seconds
Started Jul 29 04:34:29 PM PDT 24
Finished Jul 29 04:34:30 PM PDT 24
Peak memory 196968 kb
Host smart-b2139ced-ef4b-49df-9a5a-ada4c25653bc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056646179 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_intr_rand_pgm.2056646179
Directory /workspace/24.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/24.gpio_intr_with_filter_rand_intr_event.8350661
Short name T354
Test name
Test status
Simulation time 375300210 ps
CPU time 3.41 seconds
Started Jul 29 04:34:27 PM PDT 24
Finished Jul 29 04:34:31 PM PDT 24
Peak memory 198356 kb
Host smart-97922ce2-8855-4406-af3e-1803ab2688c6
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8350661 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SE
Q=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 24.gpio_intr_with_filter_rand_intr_event.8350661
Directory /workspace/24.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/24.gpio_rand_intr_trigger.1224922916
Short name T152
Test name
Test status
Simulation time 99288502 ps
CPU time 1.91 seconds
Started Jul 29 04:34:20 PM PDT 24
Finished Jul 29 04:34:22 PM PDT 24
Peak memory 196292 kb
Host smart-3f9f4131-0b8c-4280-81d7-ff1b96ae7e05
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224922916 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_rand_intr_trigger
.1224922916
Directory /workspace/24.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din.2647676412
Short name T259
Test name
Test status
Simulation time 82809584 ps
CPU time 0.88 seconds
Started Jul 29 04:34:22 PM PDT 24
Finished Jul 29 04:34:23 PM PDT 24
Peak memory 196396 kb
Host smart-fdb7b1e0-ff6c-4bbe-a428-b0adf1352dd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2647676412 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din.2647676412
Directory /workspace/24.gpio_random_dout_din/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din_no_pullup_pulldown.579397038
Short name T606
Test name
Test status
Simulation time 224691401 ps
CPU time 1.17 seconds
Started Jul 29 04:34:22 PM PDT 24
Finished Jul 29 04:34:23 PM PDT 24
Peak memory 197236 kb
Host smart-5a4d6ce7-3279-4f97-aa15-563c8c05d74f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579397038 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din_no_pullup
_pulldown.579397038
Directory /workspace/24.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_random_long_reg_writes_reg_reads.929129667
Short name T644
Test name
Test status
Simulation time 619215510 ps
CPU time 2.83 seconds
Started Jul 29 04:34:35 PM PDT 24
Finished Jul 29 04:34:38 PM PDT 24
Peak memory 198332 kb
Host smart-c0e8f751-32cf-434f-a6fc-b39f36f0cab2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929129667 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_ran
dom_long_reg_writes_reg_reads.929129667
Directory /workspace/24.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/24.gpio_smoke.3576869025
Short name T108
Test name
Test status
Simulation time 117459329 ps
CPU time 1.24 seconds
Started Jul 29 04:34:15 PM PDT 24
Finished Jul 29 04:34:16 PM PDT 24
Peak memory 198528 kb
Host smart-e476bf51-d8f2-4d52-8579-4d83aa4de966
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3576869025 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke.3576869025
Directory /workspace/24.gpio_smoke/latest

Test location /workspace/coverage/default/24.gpio_smoke_no_pullup_pulldown.1123015947
Short name T123
Test name
Test status
Simulation time 83255279 ps
CPU time 0.89 seconds
Started Jul 29 04:34:15 PM PDT 24
Finished Jul 29 04:34:16 PM PDT 24
Peak memory 196040 kb
Host smart-54534581-93d2-49ef-bcd7-f9a14e052fe5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123015947 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown.1123015947
Directory /workspace/24.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_stress_all.1882205998
Short name T132
Test name
Test status
Simulation time 84971856953 ps
CPU time 130.84 seconds
Started Jul 29 04:34:19 PM PDT 24
Finished Jul 29 04:36:30 PM PDT 24
Peak memory 198528 kb
Host smart-33075753-749e-4229-bd6b-81a15b5b6f66
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882205998 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.
gpio_stress_all.1882205998
Directory /workspace/24.gpio_stress_all/latest

Test location /workspace/coverage/default/24.gpio_stress_all_with_rand_reset.2705285400
Short name T63
Test name
Test status
Simulation time 414316511849 ps
CPU time 2303.94 seconds
Started Jul 29 04:34:10 PM PDT 24
Finished Jul 29 05:12:34 PM PDT 24
Peak memory 198732 kb
Host smart-8494bc6e-c791-41cd-9425-c935fd2d113e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2705285400 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_stress_all_with_rand_reset.2705285400
Directory /workspace/24.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.gpio_alert_test.4202918839
Short name T312
Test name
Test status
Simulation time 14291848 ps
CPU time 0.55 seconds
Started Jul 29 04:34:13 PM PDT 24
Finished Jul 29 04:34:14 PM PDT 24
Peak memory 194332 kb
Host smart-f296be4c-8d72-443a-a59c-64685e8b1ab7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202918839 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_alert_test.4202918839
Directory /workspace/25.gpio_alert_test/latest

Test location /workspace/coverage/default/25.gpio_dout_din_regs_random_rw.441666779
Short name T194
Test name
Test status
Simulation time 64493388 ps
CPU time 0.65 seconds
Started Jul 29 04:34:20 PM PDT 24
Finished Jul 29 04:34:20 PM PDT 24
Peak memory 195060 kb
Host smart-54cd0481-540d-410f-91f5-7bbd9eee4955
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=441666779 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_dout_din_regs_random_rw.441666779
Directory /workspace/25.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/25.gpio_filter_stress.267693429
Short name T640
Test name
Test status
Simulation time 471431320 ps
CPU time 5.91 seconds
Started Jul 29 04:34:30 PM PDT 24
Finished Jul 29 04:34:36 PM PDT 24
Peak memory 197252 kb
Host smart-f1333a18-1c8e-4e89-830d-bccb90ddb988
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267693429 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_filter_stres
s.267693429
Directory /workspace/25.gpio_filter_stress/latest

Test location /workspace/coverage/default/25.gpio_full_random.1947196095
Short name T608
Test name
Test status
Simulation time 67011189 ps
CPU time 1 seconds
Started Jul 29 04:34:24 PM PDT 24
Finished Jul 29 04:34:25 PM PDT 24
Peak memory 197576 kb
Host smart-0cc26aad-e4a0-40b6-ac20-dc50cd91a9d7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947196095 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_full_random.1947196095
Directory /workspace/25.gpio_full_random/latest

Test location /workspace/coverage/default/25.gpio_intr_rand_pgm.1592707725
Short name T271
Test name
Test status
Simulation time 169535441 ps
CPU time 1.11 seconds
Started Jul 29 04:34:27 PM PDT 24
Finished Jul 29 04:34:29 PM PDT 24
Peak memory 196408 kb
Host smart-f18a6bda-7760-4f4c-9132-2e765f9649ba
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592707725 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_intr_rand_pgm.1592707725
Directory /workspace/25.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/25.gpio_intr_with_filter_rand_intr_event.1250209374
Short name T157
Test name
Test status
Simulation time 22031137 ps
CPU time 0.89 seconds
Started Jul 29 04:34:36 PM PDT 24
Finished Jul 29 04:34:37 PM PDT 24
Peak memory 196416 kb
Host smart-700a65bb-348e-4c63-8e03-b56abb16cce6
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250209374 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 25.gpio_intr_with_filter_rand_intr_event.1250209374
Directory /workspace/25.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/25.gpio_rand_intr_trigger.306089744
Short name T261
Test name
Test status
Simulation time 80551829 ps
CPU time 2.27 seconds
Started Jul 29 04:34:25 PM PDT 24
Finished Jul 29 04:34:27 PM PDT 24
Peak memory 197648 kb
Host smart-56d50859-ed8f-462d-9153-da0318e92b84
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306089744 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_rand_intr_trigger.
306089744
Directory /workspace/25.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din.1508586963
Short name T372
Test name
Test status
Simulation time 918908455 ps
CPU time 1.14 seconds
Started Jul 29 04:34:30 PM PDT 24
Finished Jul 29 04:34:31 PM PDT 24
Peak memory 197132 kb
Host smart-17ca6310-11bb-4373-8a5f-b6e257115b5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1508586963 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din.1508586963
Directory /workspace/25.gpio_random_dout_din/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din_no_pullup_pulldown.1374077733
Short name T175
Test name
Test status
Simulation time 29445019 ps
CPU time 0.77 seconds
Started Jul 29 04:34:13 PM PDT 24
Finished Jul 29 04:34:14 PM PDT 24
Peak memory 195692 kb
Host smart-9e910b53-0bd4-41e2-9482-e49de9cb75c8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374077733 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din_no_pullu
p_pulldown.1374077733
Directory /workspace/25.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_random_long_reg_writes_reg_reads.381167693
Short name T345
Test name
Test status
Simulation time 1113747560 ps
CPU time 3.62 seconds
Started Jul 29 04:34:27 PM PDT 24
Finished Jul 29 04:34:31 PM PDT 24
Peak memory 197884 kb
Host smart-c66c5abd-34c2-4f91-b76d-173e83ec7f48
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381167693 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_ran
dom_long_reg_writes_reg_reads.381167693
Directory /workspace/25.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/25.gpio_smoke.1393332525
Short name T145
Test name
Test status
Simulation time 31440568 ps
CPU time 0.91 seconds
Started Jul 29 04:34:15 PM PDT 24
Finished Jul 29 04:34:16 PM PDT 24
Peak memory 196496 kb
Host smart-5257a5da-5b84-4321-a0c7-ef17fb69e6a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1393332525 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke.1393332525
Directory /workspace/25.gpio_smoke/latest

Test location /workspace/coverage/default/25.gpio_smoke_no_pullup_pulldown.2873805440
Short name T576
Test name
Test status
Simulation time 106125564 ps
CPU time 1.12 seconds
Started Jul 29 04:34:12 PM PDT 24
Finished Jul 29 04:34:13 PM PDT 24
Peak memory 196188 kb
Host smart-54431d98-eca7-4ad9-a48f-8eef1a947c86
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873805440 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown.2873805440
Directory /workspace/25.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_stress_all.1992338509
Short name T476
Test name
Test status
Simulation time 3171242004 ps
CPU time 40.94 seconds
Started Jul 29 04:34:20 PM PDT 24
Finished Jul 29 04:35:02 PM PDT 24
Peak memory 198608 kb
Host smart-739a28dc-b965-4d0e-a7fd-ac24e184ca9d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992338509 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.
gpio_stress_all.1992338509
Directory /workspace/25.gpio_stress_all/latest

Test location /workspace/coverage/default/26.gpio_alert_test.834188819
Short name T181
Test name
Test status
Simulation time 14882963 ps
CPU time 0.68 seconds
Started Jul 29 04:34:22 PM PDT 24
Finished Jul 29 04:34:23 PM PDT 24
Peak memory 194524 kb
Host smart-52c705b5-5ca3-423f-abfd-7916294277e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834188819 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_alert_test.834188819
Directory /workspace/26.gpio_alert_test/latest

Test location /workspace/coverage/default/26.gpio_dout_din_regs_random_rw.814952473
Short name T636
Test name
Test status
Simulation time 48559945 ps
CPU time 0.79 seconds
Started Jul 29 04:34:30 PM PDT 24
Finished Jul 29 04:34:31 PM PDT 24
Peak memory 196288 kb
Host smart-0537fd73-5bc7-44a0-8af7-e29e14f3af13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=814952473 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_dout_din_regs_random_rw.814952473
Directory /workspace/26.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/26.gpio_filter_stress.3949663099
Short name T457
Test name
Test status
Simulation time 8908772808 ps
CPU time 17.05 seconds
Started Jul 29 04:34:29 PM PDT 24
Finished Jul 29 04:34:46 PM PDT 24
Peak memory 198004 kb
Host smart-8faddbc3-5a8f-463e-816d-d2e2d663fa96
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949663099 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_filter_stre
ss.3949663099
Directory /workspace/26.gpio_filter_stress/latest

Test location /workspace/coverage/default/26.gpio_full_random.3044746898
Short name T365
Test name
Test status
Simulation time 134512615 ps
CPU time 0.8 seconds
Started Jul 29 04:34:25 PM PDT 24
Finished Jul 29 04:34:26 PM PDT 24
Peak memory 196104 kb
Host smart-1715cabe-b3df-4a58-90e0-30e387efe492
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044746898 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_full_random.3044746898
Directory /workspace/26.gpio_full_random/latest

Test location /workspace/coverage/default/26.gpio_intr_rand_pgm.1385615179
Short name T497
Test name
Test status
Simulation time 55237452 ps
CPU time 0.91 seconds
Started Jul 29 04:34:35 PM PDT 24
Finished Jul 29 04:34:36 PM PDT 24
Peak memory 196436 kb
Host smart-6606613d-870a-4ee1-acc3-4d92b9b10919
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385615179 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_intr_rand_pgm.1385615179
Directory /workspace/26.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/26.gpio_rand_intr_trigger.45973463
Short name T632
Test name
Test status
Simulation time 411541742 ps
CPU time 3.55 seconds
Started Jul 29 04:34:15 PM PDT 24
Finished Jul 29 04:34:18 PM PDT 24
Peak memory 198472 kb
Host smart-5beae5af-97f5-4a07-b4b0-d327c404f41b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45973463 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_rand_intr_trigger.45973463
Directory /workspace/26.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din.1390086390
Short name T248
Test name
Test status
Simulation time 114332355 ps
CPU time 1.18 seconds
Started Jul 29 04:34:14 PM PDT 24
Finished Jul 29 04:34:15 PM PDT 24
Peak memory 197408 kb
Host smart-3afef61c-a280-400b-8228-7af853866696
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1390086390 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din.1390086390
Directory /workspace/26.gpio_random_dout_din/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din_no_pullup_pulldown.605600091
Short name T379
Test name
Test status
Simulation time 107118776 ps
CPU time 0.8 seconds
Started Jul 29 04:34:16 PM PDT 24
Finished Jul 29 04:34:17 PM PDT 24
Peak memory 196960 kb
Host smart-45ac3c8a-1436-4775-bc9d-b773032632b1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605600091 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din_no_pullup
_pulldown.605600091
Directory /workspace/26.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_random_long_reg_writes_reg_reads.879891564
Short name T669
Test name
Test status
Simulation time 1477705760 ps
CPU time 4.9 seconds
Started Jul 29 04:34:21 PM PDT 24
Finished Jul 29 04:34:26 PM PDT 24
Peak memory 198404 kb
Host smart-a13fe55b-26d7-4363-a7bd-378ba9f49fdf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879891564 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_ran
dom_long_reg_writes_reg_reads.879891564
Directory /workspace/26.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/26.gpio_smoke.416141884
Short name T694
Test name
Test status
Simulation time 32260274 ps
CPU time 0.78 seconds
Started Jul 29 04:34:35 PM PDT 24
Finished Jul 29 04:34:36 PM PDT 24
Peak memory 196208 kb
Host smart-d280efd2-58d1-440b-83a2-f3abf89c0419
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=416141884 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke.416141884
Directory /workspace/26.gpio_smoke/latest

Test location /workspace/coverage/default/26.gpio_smoke_no_pullup_pulldown.3306076439
Short name T545
Test name
Test status
Simulation time 105455750 ps
CPU time 1.02 seconds
Started Jul 29 04:34:18 PM PDT 24
Finished Jul 29 04:34:19 PM PDT 24
Peak memory 196172 kb
Host smart-2dcd329f-8a35-4c63-8c12-47101f505f92
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306076439 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown.3306076439
Directory /workspace/26.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_stress_all.486957902
Short name T713
Test name
Test status
Simulation time 9629252039 ps
CPU time 52.02 seconds
Started Jul 29 04:34:21 PM PDT 24
Finished Jul 29 04:35:13 PM PDT 24
Peak memory 198588 kb
Host smart-d0e83495-cda4-411e-b7d4-cdd65c5f37c5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486957902 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.g
pio_stress_all.486957902
Directory /workspace/26.gpio_stress_all/latest

Test location /workspace/coverage/default/27.gpio_alert_test.1486954409
Short name T223
Test name
Test status
Simulation time 96678715 ps
CPU time 0.55 seconds
Started Jul 29 04:34:20 PM PDT 24
Finished Jul 29 04:34:21 PM PDT 24
Peak memory 194264 kb
Host smart-0211b3ad-1d71-40ea-b980-a3eed3075a7c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486954409 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_alert_test.1486954409
Directory /workspace/27.gpio_alert_test/latest

Test location /workspace/coverage/default/27.gpio_dout_din_regs_random_rw.1391067377
Short name T375
Test name
Test status
Simulation time 31097327 ps
CPU time 0.73 seconds
Started Jul 29 04:34:19 PM PDT 24
Finished Jul 29 04:34:20 PM PDT 24
Peak memory 194628 kb
Host smart-fae51c77-46b0-418a-b873-660ac1e4c7eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1391067377 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_dout_din_regs_random_rw.1391067377
Directory /workspace/27.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/27.gpio_filter_stress.2196101124
Short name T127
Test name
Test status
Simulation time 312468277 ps
CPU time 17.16 seconds
Started Jul 29 04:34:42 PM PDT 24
Finished Jul 29 04:34:59 PM PDT 24
Peak memory 196664 kb
Host smart-6dce9826-78ec-4fc5-945e-81f95cbd1719
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196101124 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_filter_stre
ss.2196101124
Directory /workspace/27.gpio_filter_stress/latest

Test location /workspace/coverage/default/27.gpio_full_random.1168054502
Short name T404
Test name
Test status
Simulation time 734306167 ps
CPU time 1.03 seconds
Started Jul 29 04:34:19 PM PDT 24
Finished Jul 29 04:34:20 PM PDT 24
Peak memory 197024 kb
Host smart-096e7587-5328-4f8d-9d46-ff05b5986b2c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168054502 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_full_random.1168054502
Directory /workspace/27.gpio_full_random/latest

Test location /workspace/coverage/default/27.gpio_intr_rand_pgm.63083038
Short name T179
Test name
Test status
Simulation time 179604237 ps
CPU time 1.25 seconds
Started Jul 29 04:34:29 PM PDT 24
Finished Jul 29 04:34:31 PM PDT 24
Peak memory 196668 kb
Host smart-8ebc0b7e-d6fb-428b-8756-ede7f4e3fcca
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63083038 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_intr_rand_pgm.63083038
Directory /workspace/27.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/27.gpio_intr_with_filter_rand_intr_event.1921906578
Short name T283
Test name
Test status
Simulation time 133689106 ps
CPU time 2.82 seconds
Started Jul 29 04:34:57 PM PDT 24
Finished Jul 29 04:35:00 PM PDT 24
Peak memory 198884 kb
Host smart-5d6e6344-8c0b-4d06-a6cc-679a5a57c1ac
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921906578 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 27.gpio_intr_with_filter_rand_intr_event.1921906578
Directory /workspace/27.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/27.gpio_rand_intr_trigger.942317092
Short name T598
Test name
Test status
Simulation time 1389882322 ps
CPU time 2.49 seconds
Started Jul 29 04:34:39 PM PDT 24
Finished Jul 29 04:34:42 PM PDT 24
Peak memory 197564 kb
Host smart-b9563a19-0ff1-437d-be93-c036b95a7502
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942317092 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_rand_intr_trigger.
942317092
Directory /workspace/27.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din.1161188659
Short name T187
Test name
Test status
Simulation time 468859956 ps
CPU time 1.25 seconds
Started Jul 29 04:35:03 PM PDT 24
Finished Jul 29 04:35:05 PM PDT 24
Peak memory 197604 kb
Host smart-4262bd11-e5e4-4336-b22a-03778b968ef4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1161188659 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din.1161188659
Directory /workspace/27.gpio_random_dout_din/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din_no_pullup_pulldown.2181329932
Short name T296
Test name
Test status
Simulation time 122926424 ps
CPU time 1.11 seconds
Started Jul 29 04:34:40 PM PDT 24
Finished Jul 29 04:34:42 PM PDT 24
Peak memory 196640 kb
Host smart-caec02a0-4068-4a8a-935d-35108e093bbe
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181329932 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din_no_pullu
p_pulldown.2181329932
Directory /workspace/27.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_random_long_reg_writes_reg_reads.778538188
Short name T535
Test name
Test status
Simulation time 82966832 ps
CPU time 3.66 seconds
Started Jul 29 04:34:22 PM PDT 24
Finished Jul 29 04:34:26 PM PDT 24
Peak memory 198416 kb
Host smart-455f5624-0cf4-4244-a0c3-37a5f5e5cbc1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778538188 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_ran
dom_long_reg_writes_reg_reads.778538188
Directory /workspace/27.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/27.gpio_smoke.3265882172
Short name T143
Test name
Test status
Simulation time 360315460 ps
CPU time 1.08 seconds
Started Jul 29 04:34:30 PM PDT 24
Finished Jul 29 04:34:31 PM PDT 24
Peak memory 196628 kb
Host smart-bce22087-cdd4-4b4d-a4a5-eb81b22a473e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265882172 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke.3265882172
Directory /workspace/27.gpio_smoke/latest

Test location /workspace/coverage/default/27.gpio_smoke_no_pullup_pulldown.3310188560
Short name T432
Test name
Test status
Simulation time 247645214 ps
CPU time 1.16 seconds
Started Jul 29 04:34:20 PM PDT 24
Finished Jul 29 04:34:22 PM PDT 24
Peak memory 196340 kb
Host smart-ea5c7d22-a0fe-42d0-a3dc-c21dd14e4a50
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310188560 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown.3310188560
Directory /workspace/27.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_stress_all.1107403769
Short name T572
Test name
Test status
Simulation time 4448857603 ps
CPU time 104.56 seconds
Started Jul 29 04:34:40 PM PDT 24
Finished Jul 29 04:36:25 PM PDT 24
Peak memory 198536 kb
Host smart-924e33c9-71e6-45d8-8e5d-3a2697724aef
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107403769 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.
gpio_stress_all.1107403769
Directory /workspace/27.gpio_stress_all/latest

Test location /workspace/coverage/default/27.gpio_stress_all_with_rand_reset.1447732074
Short name T467
Test name
Test status
Simulation time 397814842035 ps
CPU time 1202.71 seconds
Started Jul 29 04:34:30 PM PDT 24
Finished Jul 29 04:54:33 PM PDT 24
Peak memory 198700 kb
Host smart-3b9122d6-f277-40ba-a041-d2ff46bc4ed5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1447732074 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_stress_all_with_rand_reset.1447732074
Directory /workspace/27.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.gpio_alert_test.459000222
Short name T45
Test name
Test status
Simulation time 39859173 ps
CPU time 0.55 seconds
Started Jul 29 04:34:39 PM PDT 24
Finished Jul 29 04:34:40 PM PDT 24
Peak memory 194284 kb
Host smart-85cc167c-6904-47b2-a400-56d20948a204
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459000222 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_alert_test.459000222
Directory /workspace/28.gpio_alert_test/latest

Test location /workspace/coverage/default/28.gpio_dout_din_regs_random_rw.2138898531
Short name T321
Test name
Test status
Simulation time 146283710 ps
CPU time 0.92 seconds
Started Jul 29 04:34:18 PM PDT 24
Finished Jul 29 04:34:19 PM PDT 24
Peak memory 196200 kb
Host smart-45105866-2b31-4464-9067-03aa116c692b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2138898531 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_dout_din_regs_random_rw.2138898531
Directory /workspace/28.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/28.gpio_filter_stress.982013789
Short name T114
Test name
Test status
Simulation time 505878163 ps
CPU time 25.91 seconds
Started Jul 29 04:34:39 PM PDT 24
Finished Jul 29 04:35:05 PM PDT 24
Peak memory 197120 kb
Host smart-ef52c53b-5e1c-43a8-8f90-ce9ecf0ac977
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982013789 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_filter_stres
s.982013789
Directory /workspace/28.gpio_filter_stress/latest

Test location /workspace/coverage/default/28.gpio_full_random.373003772
Short name T118
Test name
Test status
Simulation time 81152301 ps
CPU time 0.67 seconds
Started Jul 29 04:34:42 PM PDT 24
Finished Jul 29 04:34:42 PM PDT 24
Peak memory 195020 kb
Host smart-c8913908-6eef-4edc-ae09-7cf89f2a87b9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373003772 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_full_random.373003772
Directory /workspace/28.gpio_full_random/latest

Test location /workspace/coverage/default/28.gpio_intr_rand_pgm.3109949950
Short name T334
Test name
Test status
Simulation time 51204776 ps
CPU time 0.95 seconds
Started Jul 29 04:34:44 PM PDT 24
Finished Jul 29 04:34:45 PM PDT 24
Peak memory 196476 kb
Host smart-682376f4-5e56-4a33-a1c5-457c263efe56
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109949950 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_intr_rand_pgm.3109949950
Directory /workspace/28.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/28.gpio_intr_with_filter_rand_intr_event.247187138
Short name T410
Test name
Test status
Simulation time 82573096 ps
CPU time 3.15 seconds
Started Jul 29 04:34:37 PM PDT 24
Finished Jul 29 04:34:40 PM PDT 24
Peak memory 198360 kb
Host smart-ba4e0d14-08ca-4f35-a353-51786c19c857
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247187138 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 28.gpio_intr_with_filter_rand_intr_event.247187138
Directory /workspace/28.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/28.gpio_rand_intr_trigger.304825605
Short name T676
Test name
Test status
Simulation time 522316418 ps
CPU time 1.79 seconds
Started Jul 29 04:34:35 PM PDT 24
Finished Jul 29 04:34:37 PM PDT 24
Peak memory 196204 kb
Host smart-5efbad11-eeab-4622-bde1-db4730ac6c23
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304825605 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_rand_intr_trigger.
304825605
Directory /workspace/28.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din.1667957097
Short name T319
Test name
Test status
Simulation time 65950174 ps
CPU time 1.18 seconds
Started Jul 29 04:34:39 PM PDT 24
Finished Jul 29 04:34:40 PM PDT 24
Peak memory 198452 kb
Host smart-7f6bd0df-5cf4-4a08-9979-728a125c9a0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1667957097 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din.1667957097
Directory /workspace/28.gpio_random_dout_din/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din_no_pullup_pulldown.1088871304
Short name T397
Test name
Test status
Simulation time 45841353 ps
CPU time 1.1 seconds
Started Jul 29 04:34:38 PM PDT 24
Finished Jul 29 04:34:40 PM PDT 24
Peak memory 196244 kb
Host smart-e9922aa0-c7eb-4552-adbf-29f50e13ed47
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088871304 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din_no_pullu
p_pulldown.1088871304
Directory /workspace/28.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_random_long_reg_writes_reg_reads.2356971007
Short name T262
Test name
Test status
Simulation time 365592223 ps
CPU time 3.07 seconds
Started Jul 29 04:34:46 PM PDT 24
Finished Jul 29 04:34:49 PM PDT 24
Peak memory 198396 kb
Host smart-6853a760-ba93-4de9-b1e9-adadc2633237
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356971007 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_ra
ndom_long_reg_writes_reg_reads.2356971007
Directory /workspace/28.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/28.gpio_smoke.302075487
Short name T131
Test name
Test status
Simulation time 169205226 ps
CPU time 1.35 seconds
Started Jul 29 04:34:54 PM PDT 24
Finished Jul 29 04:34:55 PM PDT 24
Peak memory 197096 kb
Host smart-a0c6f3ee-6010-4987-ad73-75dfe6fc2679
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=302075487 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke.302075487
Directory /workspace/28.gpio_smoke/latest

Test location /workspace/coverage/default/28.gpio_smoke_no_pullup_pulldown.929390088
Short name T266
Test name
Test status
Simulation time 298728213 ps
CPU time 1.19 seconds
Started Jul 29 04:34:26 PM PDT 24
Finished Jul 29 04:34:27 PM PDT 24
Peak memory 196100 kb
Host smart-594c4e34-3d34-4db3-b7bd-fdcc582ac82c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929390088 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown.929390088
Directory /workspace/28.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_stress_all.2873875872
Short name T369
Test name
Test status
Simulation time 10304362174 ps
CPU time 170.26 seconds
Started Jul 29 04:34:49 PM PDT 24
Finished Jul 29 04:37:40 PM PDT 24
Peak memory 198704 kb
Host smart-1e56cdd0-780e-46bc-af8b-83b3d62b65f0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873875872 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.
gpio_stress_all.2873875872
Directory /workspace/28.gpio_stress_all/latest

Test location /workspace/coverage/default/28.gpio_stress_all_with_rand_reset.534513222
Short name T66
Test name
Test status
Simulation time 455241461790 ps
CPU time 571.02 seconds
Started Jul 29 04:34:30 PM PDT 24
Finished Jul 29 04:44:01 PM PDT 24
Peak memory 206908 kb
Host smart-febf1ccb-b160-44b6-9435-59f9d8cde219
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=534513222 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_stress_all_with_rand_reset.534513222
Directory /workspace/28.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.gpio_alert_test.3754903930
Short name T191
Test name
Test status
Simulation time 24199827 ps
CPU time 0.55 seconds
Started Jul 29 04:34:29 PM PDT 24
Finished Jul 29 04:34:30 PM PDT 24
Peak memory 194320 kb
Host smart-738325e2-ea3a-4681-a116-b4fae7576ab7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754903930 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_alert_test.3754903930
Directory /workspace/29.gpio_alert_test/latest

Test location /workspace/coverage/default/29.gpio_dout_din_regs_random_rw.3364120711
Short name T503
Test name
Test status
Simulation time 55135647 ps
CPU time 0.73 seconds
Started Jul 29 04:34:50 PM PDT 24
Finished Jul 29 04:34:51 PM PDT 24
Peak memory 195588 kb
Host smart-b92b76e5-8e43-4701-bad7-7f5bcc279a17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3364120711 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_dout_din_regs_random_rw.3364120711
Directory /workspace/29.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/29.gpio_filter_stress.3598712295
Short name T380
Test name
Test status
Simulation time 928788030 ps
CPU time 27.07 seconds
Started Jul 29 04:34:32 PM PDT 24
Finished Jul 29 04:34:59 PM PDT 24
Peak memory 197324 kb
Host smart-4db8043e-2d19-4195-b8dc-604e67c3a8d7
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598712295 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_filter_stre
ss.3598712295
Directory /workspace/29.gpio_filter_stress/latest

Test location /workspace/coverage/default/29.gpio_full_random.3381263671
Short name T298
Test name
Test status
Simulation time 49012005 ps
CPU time 0.81 seconds
Started Jul 29 04:34:26 PM PDT 24
Finished Jul 29 04:34:27 PM PDT 24
Peak memory 196200 kb
Host smart-2df23e52-ae57-41fd-b8cb-ab4dde4bad0b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381263671 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_full_random.3381263671
Directory /workspace/29.gpio_full_random/latest

Test location /workspace/coverage/default/29.gpio_intr_rand_pgm.792062467
Short name T249
Test name
Test status
Simulation time 60976742 ps
CPU time 1.07 seconds
Started Jul 29 04:34:33 PM PDT 24
Finished Jul 29 04:34:34 PM PDT 24
Peak memory 197196 kb
Host smart-492d3bb8-5d97-4f1a-bb40-781457526769
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792062467 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_intr_rand_pgm.792062467
Directory /workspace/29.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/29.gpio_intr_with_filter_rand_intr_event.871698678
Short name T475
Test name
Test status
Simulation time 49784091 ps
CPU time 1.13 seconds
Started Jul 29 04:34:33 PM PDT 24
Finished Jul 29 04:34:34 PM PDT 24
Peak memory 198440 kb
Host smart-1b8dc721-fe70-4c95-aeb6-3634360a11a2
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871698678 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 29.gpio_intr_with_filter_rand_intr_event.871698678
Directory /workspace/29.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/29.gpio_rand_intr_trigger.1140454796
Short name T567
Test name
Test status
Simulation time 482477884 ps
CPU time 1.86 seconds
Started Jul 29 04:34:41 PM PDT 24
Finished Jul 29 04:34:43 PM PDT 24
Peak memory 197060 kb
Host smart-2deb04a9-ca40-493e-b2ed-86750278e333
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140454796 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_rand_intr_trigger
.1140454796
Directory /workspace/29.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din.370958439
Short name T318
Test name
Test status
Simulation time 125046139 ps
CPU time 0.95 seconds
Started Jul 29 04:34:45 PM PDT 24
Finished Jul 29 04:34:46 PM PDT 24
Peak memory 196872 kb
Host smart-bd689a9e-1908-404e-8010-553be5630831
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=370958439 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din.370958439
Directory /workspace/29.gpio_random_dout_din/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din_no_pullup_pulldown.2050311240
Short name T692
Test name
Test status
Simulation time 298799397 ps
CPU time 1.25 seconds
Started Jul 29 04:34:44 PM PDT 24
Finished Jul 29 04:34:46 PM PDT 24
Peak memory 198436 kb
Host smart-c5a64479-04a2-4590-b81b-dde2fd22fde6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050311240 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din_no_pullu
p_pulldown.2050311240
Directory /workspace/29.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_random_long_reg_writes_reg_reads.4165137514
Short name T472
Test name
Test status
Simulation time 83653430 ps
CPU time 3.72 seconds
Started Jul 29 04:34:32 PM PDT 24
Finished Jul 29 04:34:35 PM PDT 24
Peak memory 198380 kb
Host smart-e60e4ecd-7379-48b1-89e5-7fff03128e66
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165137514 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_ra
ndom_long_reg_writes_reg_reads.4165137514
Directory /workspace/29.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/29.gpio_smoke.1742049197
Short name T325
Test name
Test status
Simulation time 116788671 ps
CPU time 0.81 seconds
Started Jul 29 04:34:29 PM PDT 24
Finished Jul 29 04:34:30 PM PDT 24
Peak memory 195684 kb
Host smart-09058cad-ab1b-4595-9566-c257cbf2fc98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1742049197 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke.1742049197
Directory /workspace/29.gpio_smoke/latest

Test location /workspace/coverage/default/29.gpio_smoke_no_pullup_pulldown.3753804201
Short name T413
Test name
Test status
Simulation time 31078798 ps
CPU time 0.92 seconds
Started Jul 29 04:34:48 PM PDT 24
Finished Jul 29 04:34:49 PM PDT 24
Peak memory 195964 kb
Host smart-a7bbaf83-97c3-4e72-b779-21d4da137453
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753804201 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown.3753804201
Directory /workspace/29.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_stress_all.2998811308
Short name T11
Test name
Test status
Simulation time 7520434993 ps
CPU time 99.73 seconds
Started Jul 29 04:34:40 PM PDT 24
Finished Jul 29 04:36:20 PM PDT 24
Peak memory 198572 kb
Host smart-42971505-29a3-4cc7-83cb-7ae9a25b1e2d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998811308 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.
gpio_stress_all.2998811308
Directory /workspace/29.gpio_stress_all/latest

Test location /workspace/coverage/default/3.gpio_alert_test.2905379900
Short name T353
Test name
Test status
Simulation time 15909467 ps
CPU time 0.61 seconds
Started Jul 29 04:33:38 PM PDT 24
Finished Jul 29 04:33:39 PM PDT 24
Peak memory 194296 kb
Host smart-80aa3abc-d5bc-477a-9462-e6c7b2389f27
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905379900 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_alert_test.2905379900
Directory /workspace/3.gpio_alert_test/latest

Test location /workspace/coverage/default/3.gpio_dout_din_regs_random_rw.3952224561
Short name T203
Test name
Test status
Simulation time 109975382 ps
CPU time 0.86 seconds
Started Jul 29 04:33:33 PM PDT 24
Finished Jul 29 04:33:34 PM PDT 24
Peak memory 196840 kb
Host smart-25fce146-307f-44b4-8b02-f44283c90cf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3952224561 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_dout_din_regs_random_rw.3952224561
Directory /workspace/3.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/3.gpio_filter_stress.1939731254
Short name T373
Test name
Test status
Simulation time 1266509726 ps
CPU time 4.3 seconds
Started Jul 29 04:33:42 PM PDT 24
Finished Jul 29 04:33:47 PM PDT 24
Peak memory 196588 kb
Host smart-aac75016-6b22-406d-8992-e2629019a09c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939731254 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_filter_stres
s.1939731254
Directory /workspace/3.gpio_filter_stress/latest

Test location /workspace/coverage/default/3.gpio_full_random.3999724593
Short name T94
Test name
Test status
Simulation time 289494305 ps
CPU time 0.99 seconds
Started Jul 29 04:33:39 PM PDT 24
Finished Jul 29 04:33:41 PM PDT 24
Peak memory 197628 kb
Host smart-9293acc3-c18e-430a-8e53-00a5be11480e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999724593 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_full_random.3999724593
Directory /workspace/3.gpio_full_random/latest

Test location /workspace/coverage/default/3.gpio_intr_rand_pgm.3709886255
Short name T701
Test name
Test status
Simulation time 40468550 ps
CPU time 0.84 seconds
Started Jul 29 04:33:34 PM PDT 24
Finished Jul 29 04:33:35 PM PDT 24
Peak memory 196088 kb
Host smart-badd1d71-19ed-4bde-bafd-fc5aae8a38a4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709886255 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_intr_rand_pgm.3709886255
Directory /workspace/3.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/3.gpio_intr_with_filter_rand_intr_event.3536354976
Short name T106
Test name
Test status
Simulation time 150898241 ps
CPU time 1.69 seconds
Started Jul 29 04:33:31 PM PDT 24
Finished Jul 29 04:33:33 PM PDT 24
Peak memory 196860 kb
Host smart-282649d2-0917-40ba-8752-697023615199
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536354976 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.gpio_intr_with_filter_rand_intr_event.3536354976
Directory /workspace/3.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/3.gpio_rand_intr_trigger.163332245
Short name T270
Test name
Test status
Simulation time 166504527 ps
CPU time 2.09 seconds
Started Jul 29 04:33:43 PM PDT 24
Finished Jul 29 04:33:46 PM PDT 24
Peak memory 196552 kb
Host smart-8da2b845-abaa-482b-9dbf-e60bed40c69c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163332245 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_rand_intr_trigger.163332245
Directory /workspace/3.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din.2321506412
Short name T273
Test name
Test status
Simulation time 36561355 ps
CPU time 0.69 seconds
Started Jul 29 04:33:34 PM PDT 24
Finished Jul 29 04:33:35 PM PDT 24
Peak memory 194736 kb
Host smart-291eaa19-b9aa-447e-a95d-d8299d1dfdc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2321506412 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din.2321506412
Directory /workspace/3.gpio_random_dout_din/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din_no_pullup_pulldown.2492529062
Short name T549
Test name
Test status
Simulation time 57962630 ps
CPU time 0.63 seconds
Started Jul 29 04:33:31 PM PDT 24
Finished Jul 29 04:33:32 PM PDT 24
Peak memory 194668 kb
Host smart-93855cee-329e-414f-b7f7-84bcd64e36a9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492529062 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din_no_pullup
_pulldown.2492529062
Directory /workspace/3.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_random_long_reg_writes_reg_reads.1093261614
Short name T595
Test name
Test status
Simulation time 867929604 ps
CPU time 3.97 seconds
Started Jul 29 04:33:34 PM PDT 24
Finished Jul 29 04:33:38 PM PDT 24
Peak memory 198420 kb
Host smart-06db4c71-2a30-4311-83dc-ae9eb39ce366
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093261614 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_ran
dom_long_reg_writes_reg_reads.1093261614
Directory /workspace/3.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/3.gpio_smoke.2050197742
Short name T624
Test name
Test status
Simulation time 82573065 ps
CPU time 1.17 seconds
Started Jul 29 04:33:41 PM PDT 24
Finished Jul 29 04:33:42 PM PDT 24
Peak memory 196536 kb
Host smart-034c7f02-f482-4137-beda-61296dbcaff4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2050197742 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke.2050197742
Directory /workspace/3.gpio_smoke/latest

Test location /workspace/coverage/default/3.gpio_smoke_no_pullup_pulldown.2548470530
Short name T153
Test name
Test status
Simulation time 123156936 ps
CPU time 1.04 seconds
Started Jul 29 04:33:38 PM PDT 24
Finished Jul 29 04:33:39 PM PDT 24
Peak memory 196800 kb
Host smart-564f205e-bc7b-4feb-879e-b00db52a3e89
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548470530 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown.2548470530
Directory /workspace/3.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_stress_all.3896741284
Short name T5
Test name
Test status
Simulation time 4233170189 ps
CPU time 20.79 seconds
Started Jul 29 04:34:01 PM PDT 24
Finished Jul 29 04:34:22 PM PDT 24
Peak memory 198900 kb
Host smart-858d636c-12d9-457c-950e-0204f667cd1e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896741284 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.g
pio_stress_all.3896741284
Directory /workspace/3.gpio_stress_all/latest

Test location /workspace/coverage/default/30.gpio_alert_test.3225331704
Short name T683
Test name
Test status
Simulation time 25791061 ps
CPU time 0.58 seconds
Started Jul 29 04:34:45 PM PDT 24
Finished Jul 29 04:34:45 PM PDT 24
Peak memory 195204 kb
Host smart-23646fe2-f40b-4166-a447-c478a41800ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225331704 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_alert_test.3225331704
Directory /workspace/30.gpio_alert_test/latest

Test location /workspace/coverage/default/30.gpio_dout_din_regs_random_rw.1451027389
Short name T58
Test name
Test status
Simulation time 24688952 ps
CPU time 0.7 seconds
Started Jul 29 04:34:35 PM PDT 24
Finished Jul 29 04:34:36 PM PDT 24
Peak memory 194456 kb
Host smart-bbbd79a1-2117-43f1-beb4-6ae24d2c5c1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1451027389 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_dout_din_regs_random_rw.1451027389
Directory /workspace/30.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/30.gpio_filter_stress.4038489327
Short name T574
Test name
Test status
Simulation time 826230781 ps
CPU time 12.43 seconds
Started Jul 29 04:34:50 PM PDT 24
Finished Jul 29 04:35:02 PM PDT 24
Peak memory 197196 kb
Host smart-8ac2e9ba-354f-4306-9741-0c7aba110c14
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038489327 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_filter_stre
ss.4038489327
Directory /workspace/30.gpio_filter_stress/latest

Test location /workspace/coverage/default/30.gpio_full_random.268856788
Short name T460
Test name
Test status
Simulation time 940006734 ps
CPU time 1.1 seconds
Started Jul 29 04:34:45 PM PDT 24
Finished Jul 29 04:34:46 PM PDT 24
Peak memory 196892 kb
Host smart-aa73c586-be9e-4771-8615-4b537836cb53
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268856788 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_full_random.268856788
Directory /workspace/30.gpio_full_random/latest

Test location /workspace/coverage/default/30.gpio_intr_rand_pgm.708323588
Short name T172
Test name
Test status
Simulation time 129896373 ps
CPU time 1.14 seconds
Started Jul 29 04:34:46 PM PDT 24
Finished Jul 29 04:34:47 PM PDT 24
Peak memory 197060 kb
Host smart-c6a51905-3c89-4118-ad6e-80e3ff2da2d7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708323588 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_intr_rand_pgm.708323588
Directory /workspace/30.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/30.gpio_intr_with_filter_rand_intr_event.274361610
Short name T671
Test name
Test status
Simulation time 67784754 ps
CPU time 2.67 seconds
Started Jul 29 04:34:38 PM PDT 24
Finished Jul 29 04:34:40 PM PDT 24
Peak memory 198580 kb
Host smart-940cc2db-5d2f-4f0e-96b1-8949582d71af
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274361610 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 30.gpio_intr_with_filter_rand_intr_event.274361610
Directory /workspace/30.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/30.gpio_rand_intr_trigger.199225503
Short name T109
Test name
Test status
Simulation time 89383549 ps
CPU time 1.68 seconds
Started Jul 29 04:34:33 PM PDT 24
Finished Jul 29 04:34:35 PM PDT 24
Peak memory 196220 kb
Host smart-1db54775-b3ed-4564-8756-99e0d222a201
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199225503 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_rand_intr_trigger.
199225503
Directory /workspace/30.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din.1010700534
Short name T234
Test name
Test status
Simulation time 14488765 ps
CPU time 0.69 seconds
Started Jul 29 04:34:47 PM PDT 24
Finished Jul 29 04:34:48 PM PDT 24
Peak memory 194836 kb
Host smart-590a5988-c363-4f01-b76c-5084c62eb301
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1010700534 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din.1010700534
Directory /workspace/30.gpio_random_dout_din/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din_no_pullup_pulldown.3929756012
Short name T531
Test name
Test status
Simulation time 113189159 ps
CPU time 1.05 seconds
Started Jul 29 04:34:47 PM PDT 24
Finished Jul 29 04:34:49 PM PDT 24
Peak memory 196400 kb
Host smart-a6b404f9-7fdd-485b-a51c-3e3087b59d59
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929756012 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din_no_pullu
p_pulldown.3929756012
Directory /workspace/30.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_random_long_reg_writes_reg_reads.427448503
Short name T558
Test name
Test status
Simulation time 1131633210 ps
CPU time 4.55 seconds
Started Jul 29 04:34:47 PM PDT 24
Finished Jul 29 04:34:52 PM PDT 24
Peak memory 198384 kb
Host smart-5b74abbb-d0c9-4dd4-8860-df00f78ddcb7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427448503 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_ran
dom_long_reg_writes_reg_reads.427448503
Directory /workspace/30.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/30.gpio_smoke.765004763
Short name T287
Test name
Test status
Simulation time 814742991 ps
CPU time 1.04 seconds
Started Jul 29 04:34:46 PM PDT 24
Finished Jul 29 04:34:47 PM PDT 24
Peak memory 196196 kb
Host smart-dc8a21f0-6edd-43da-8c2a-aed5183879c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=765004763 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke.765004763
Directory /workspace/30.gpio_smoke/latest

Test location /workspace/coverage/default/30.gpio_smoke_no_pullup_pulldown.3453573141
Short name T213
Test name
Test status
Simulation time 128719070 ps
CPU time 1.12 seconds
Started Jul 29 04:34:40 PM PDT 24
Finished Jul 29 04:34:41 PM PDT 24
Peak memory 195964 kb
Host smart-d1a1127b-eb49-491d-afac-88ca66373351
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453573141 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown.3453573141
Directory /workspace/30.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_stress_all.2255728285
Short name T17
Test name
Test status
Simulation time 60998060095 ps
CPU time 211.76 seconds
Started Jul 29 04:34:57 PM PDT 24
Finished Jul 29 04:38:29 PM PDT 24
Peak memory 198588 kb
Host smart-be83dafb-71ff-47f7-85cc-8a07dafc9d0b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255728285 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.
gpio_stress_all.2255728285
Directory /workspace/30.gpio_stress_all/latest

Test location /workspace/coverage/default/31.gpio_alert_test.3382681179
Short name T293
Test name
Test status
Simulation time 43049980 ps
CPU time 0.56 seconds
Started Jul 29 04:34:40 PM PDT 24
Finished Jul 29 04:34:41 PM PDT 24
Peak memory 194368 kb
Host smart-0837b29f-c9ff-464b-9836-3f2a8134b2dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382681179 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_alert_test.3382681179
Directory /workspace/31.gpio_alert_test/latest

Test location /workspace/coverage/default/31.gpio_dout_din_regs_random_rw.582241172
Short name T477
Test name
Test status
Simulation time 43397791 ps
CPU time 0.88 seconds
Started Jul 29 04:34:42 PM PDT 24
Finished Jul 29 04:34:43 PM PDT 24
Peak memory 196848 kb
Host smart-871c177e-67f9-4639-8dc3-c3abe8151d78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=582241172 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_dout_din_regs_random_rw.582241172
Directory /workspace/31.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/31.gpio_filter_stress.670337432
Short name T518
Test name
Test status
Simulation time 232499700 ps
CPU time 5.85 seconds
Started Jul 29 04:34:40 PM PDT 24
Finished Jul 29 04:34:46 PM PDT 24
Peak memory 197384 kb
Host smart-9699b53b-06f3-4091-a80a-627d6cbb22f6
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670337432 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_filter_stres
s.670337432
Directory /workspace/31.gpio_filter_stress/latest

Test location /workspace/coverage/default/31.gpio_full_random.711729404
Short name T383
Test name
Test status
Simulation time 36058408 ps
CPU time 0.62 seconds
Started Jul 29 04:34:41 PM PDT 24
Finished Jul 29 04:34:42 PM PDT 24
Peak memory 194736 kb
Host smart-b04b0b30-b038-4dc0-8106-ceb1505f2e01
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711729404 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_full_random.711729404
Directory /workspace/31.gpio_full_random/latest

Test location /workspace/coverage/default/31.gpio_intr_rand_pgm.4261073146
Short name T265
Test name
Test status
Simulation time 177848504 ps
CPU time 0.9 seconds
Started Jul 29 04:34:45 PM PDT 24
Finished Jul 29 04:34:47 PM PDT 24
Peak memory 196912 kb
Host smart-abc7a9df-8c08-45f5-b8f8-bea7d65960e8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261073146 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_intr_rand_pgm.4261073146
Directory /workspace/31.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/31.gpio_intr_with_filter_rand_intr_event.1768145975
Short name T402
Test name
Test status
Simulation time 99229766 ps
CPU time 1.76 seconds
Started Jul 29 04:34:40 PM PDT 24
Finished Jul 29 04:34:42 PM PDT 24
Peak memory 198524 kb
Host smart-4aef4792-3f63-4b6e-afd7-32efcafdabfd
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768145975 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 31.gpio_intr_with_filter_rand_intr_event.1768145975
Directory /workspace/31.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/31.gpio_rand_intr_trigger.1163829219
Short name T525
Test name
Test status
Simulation time 103981844 ps
CPU time 1.06 seconds
Started Jul 29 04:34:43 PM PDT 24
Finished Jul 29 04:34:45 PM PDT 24
Peak memory 196720 kb
Host smart-4d9410cc-a9bf-4e8a-8916-063ec41d372b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163829219 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_rand_intr_trigger
.1163829219
Directory /workspace/31.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din.2827863243
Short name T575
Test name
Test status
Simulation time 34638087 ps
CPU time 0.89 seconds
Started Jul 29 04:34:45 PM PDT 24
Finished Jul 29 04:34:46 PM PDT 24
Peak memory 197084 kb
Host smart-c359a21a-adc1-4002-a15b-bd5f5405a60f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2827863243 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din.2827863243
Directory /workspace/31.gpio_random_dout_din/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din_no_pullup_pulldown.3147754759
Short name T551
Test name
Test status
Simulation time 66081847 ps
CPU time 0.89 seconds
Started Jul 29 04:34:43 PM PDT 24
Finished Jul 29 04:34:44 PM PDT 24
Peak memory 196848 kb
Host smart-8132f9ed-6275-4add-adb0-686f2cb7d867
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147754759 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din_no_pullu
p_pulldown.3147754759
Directory /workspace/31.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_random_long_reg_writes_reg_reads.127080647
Short name T700
Test name
Test status
Simulation time 329968724 ps
CPU time 5.35 seconds
Started Jul 29 04:34:41 PM PDT 24
Finished Jul 29 04:34:46 PM PDT 24
Peak memory 198316 kb
Host smart-421b3506-982d-47a4-9003-151b35206d87
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127080647 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_ran
dom_long_reg_writes_reg_reads.127080647
Directory /workspace/31.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/31.gpio_smoke.1996655729
Short name T378
Test name
Test status
Simulation time 137838117 ps
CPU time 0.98 seconds
Started Jul 29 04:34:43 PM PDT 24
Finished Jul 29 04:34:45 PM PDT 24
Peak memory 196824 kb
Host smart-4eb8bb45-d520-4f5b-82bd-30a70decd8d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1996655729 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke.1996655729
Directory /workspace/31.gpio_smoke/latest

Test location /workspace/coverage/default/31.gpio_smoke_no_pullup_pulldown.862399212
Short name T306
Test name
Test status
Simulation time 96604198 ps
CPU time 1.33 seconds
Started Jul 29 04:34:52 PM PDT 24
Finished Jul 29 04:34:53 PM PDT 24
Peak memory 197132 kb
Host smart-c597d31c-2e71-48b4-b6fb-931ca9c76451
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862399212 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown.862399212
Directory /workspace/31.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_stress_all.3495441791
Short name T524
Test name
Test status
Simulation time 12881707592 ps
CPU time 141.51 seconds
Started Jul 29 04:34:48 PM PDT 24
Finished Jul 29 04:37:09 PM PDT 24
Peak memory 198536 kb
Host smart-7e58c607-e5b5-4bb6-835a-ba5d34cb45ed
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495441791 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.
gpio_stress_all.3495441791
Directory /workspace/31.gpio_stress_all/latest

Test location /workspace/coverage/default/32.gpio_alert_test.2470849910
Short name T667
Test name
Test status
Simulation time 64766359 ps
CPU time 0.58 seconds
Started Jul 29 04:34:42 PM PDT 24
Finished Jul 29 04:34:42 PM PDT 24
Peak memory 194236 kb
Host smart-7aac8b29-22cf-4688-8c82-f90bc2d032fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470849910 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_alert_test.2470849910
Directory /workspace/32.gpio_alert_test/latest

Test location /workspace/coverage/default/32.gpio_dout_din_regs_random_rw.4246426209
Short name T699
Test name
Test status
Simulation time 17375851 ps
CPU time 0.69 seconds
Started Jul 29 04:34:41 PM PDT 24
Finished Jul 29 04:34:42 PM PDT 24
Peak memory 194444 kb
Host smart-ed4b118c-b468-481b-a44d-df87efffe4f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4246426209 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_dout_din_regs_random_rw.4246426209
Directory /workspace/32.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/32.gpio_filter_stress.1959622341
Short name T366
Test name
Test status
Simulation time 2762018627 ps
CPU time 22.8 seconds
Started Jul 29 04:34:55 PM PDT 24
Finished Jul 29 04:35:18 PM PDT 24
Peak memory 197596 kb
Host smart-6b79f45b-82c7-4672-a4e1-0c916059c741
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959622341 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_filter_stre
ss.1959622341
Directory /workspace/32.gpio_filter_stress/latest

Test location /workspace/coverage/default/32.gpio_full_random.847599082
Short name T714
Test name
Test status
Simulation time 255900312 ps
CPU time 1.08 seconds
Started Jul 29 04:34:49 PM PDT 24
Finished Jul 29 04:34:50 PM PDT 24
Peak memory 197196 kb
Host smart-a6555431-973d-428a-a99e-b73536176cbb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847599082 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_full_random.847599082
Directory /workspace/32.gpio_full_random/latest

Test location /workspace/coverage/default/32.gpio_intr_rand_pgm.3115399073
Short name T438
Test name
Test status
Simulation time 72381090 ps
CPU time 1.07 seconds
Started Jul 29 04:34:52 PM PDT 24
Finished Jul 29 04:34:53 PM PDT 24
Peak memory 196896 kb
Host smart-a5f80f31-4735-40cc-a821-5d9aac87215c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115399073 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_intr_rand_pgm.3115399073
Directory /workspace/32.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/32.gpio_intr_with_filter_rand_intr_event.3617734961
Short name T514
Test name
Test status
Simulation time 62996710 ps
CPU time 2.42 seconds
Started Jul 29 04:34:44 PM PDT 24
Finished Jul 29 04:34:46 PM PDT 24
Peak memory 196848 kb
Host smart-ac975007-931a-4831-b9d8-f5565b840f49
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617734961 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 32.gpio_intr_with_filter_rand_intr_event.3617734961
Directory /workspace/32.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/32.gpio_rand_intr_trigger.561206167
Short name T96
Test name
Test status
Simulation time 929908777 ps
CPU time 2.84 seconds
Started Jul 29 04:34:48 PM PDT 24
Finished Jul 29 04:34:51 PM PDT 24
Peak memory 198300 kb
Host smart-5176cfbb-ecc8-46f9-beef-bd2412f97c72
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561206167 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_rand_intr_trigger.
561206167
Directory /workspace/32.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din.2993855161
Short name T253
Test name
Test status
Simulation time 82364552 ps
CPU time 0.95 seconds
Started Jul 29 04:34:40 PM PDT 24
Finished Jul 29 04:34:41 PM PDT 24
Peak memory 196292 kb
Host smart-7f519cd4-926a-4e85-b2ac-dc1937afb5d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2993855161 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din.2993855161
Directory /workspace/32.gpio_random_dout_din/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din_no_pullup_pulldown.768908178
Short name T363
Test name
Test status
Simulation time 97840809 ps
CPU time 1.24 seconds
Started Jul 29 04:34:37 PM PDT 24
Finished Jul 29 04:34:38 PM PDT 24
Peak memory 197476 kb
Host smart-89891390-f2d2-4c97-ac9e-8a0508cb21a0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768908178 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din_no_pullup
_pulldown.768908178
Directory /workspace/32.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_random_long_reg_writes_reg_reads.2589818972
Short name T300
Test name
Test status
Simulation time 352827918 ps
CPU time 5.87 seconds
Started Jul 29 04:34:54 PM PDT 24
Finished Jul 29 04:35:00 PM PDT 24
Peak memory 198308 kb
Host smart-c56ce7ab-40d8-47d5-84ea-0222f1f65f36
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589818972 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_ra
ndom_long_reg_writes_reg_reads.2589818972
Directory /workspace/32.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/32.gpio_smoke.2343561711
Short name T299
Test name
Test status
Simulation time 178781472 ps
CPU time 1.35 seconds
Started Jul 29 04:34:50 PM PDT 24
Finished Jul 29 04:34:52 PM PDT 24
Peak memory 198432 kb
Host smart-bfe1f812-d0df-418c-b7a6-ba78c2a2c700
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2343561711 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke.2343561711
Directory /workspace/32.gpio_smoke/latest

Test location /workspace/coverage/default/32.gpio_smoke_no_pullup_pulldown.3699330506
Short name T675
Test name
Test status
Simulation time 41065879 ps
CPU time 0.88 seconds
Started Jul 29 04:34:49 PM PDT 24
Finished Jul 29 04:34:50 PM PDT 24
Peak memory 195772 kb
Host smart-f51b2b93-2169-486c-9026-ef5df2e4101b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699330506 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown.3699330506
Directory /workspace/32.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_stress_all.3939524989
Short name T429
Test name
Test status
Simulation time 14894924972 ps
CPU time 172.61 seconds
Started Jul 29 04:34:49 PM PDT 24
Finished Jul 29 04:37:42 PM PDT 24
Peak memory 198500 kb
Host smart-e8de89cc-e98a-4a5b-bf35-439cbca4d6b7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939524989 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.
gpio_stress_all.3939524989
Directory /workspace/32.gpio_stress_all/latest

Test location /workspace/coverage/default/32.gpio_stress_all_with_rand_reset.2559044027
Short name T672
Test name
Test status
Simulation time 127008236566 ps
CPU time 261.93 seconds
Started Jul 29 04:34:47 PM PDT 24
Finished Jul 29 04:39:09 PM PDT 24
Peak memory 198668 kb
Host smart-e5416d0b-eb4a-41c3-bc9b-f3bc7fe228d6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2559044027 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_stress_all_with_rand_reset.2559044027
Directory /workspace/32.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.gpio_alert_test.1818314718
Short name T165
Test name
Test status
Simulation time 17743594 ps
CPU time 0.56 seconds
Started Jul 29 04:34:44 PM PDT 24
Finished Jul 29 04:34:45 PM PDT 24
Peak memory 195008 kb
Host smart-32f63adc-960b-4225-9900-d3bd6aa4c951
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818314718 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_alert_test.1818314718
Directory /workspace/33.gpio_alert_test/latest

Test location /workspace/coverage/default/33.gpio_dout_din_regs_random_rw.1070282451
Short name T601
Test name
Test status
Simulation time 76237397 ps
CPU time 0.81 seconds
Started Jul 29 04:34:44 PM PDT 24
Finished Jul 29 04:34:45 PM PDT 24
Peak memory 195608 kb
Host smart-03e0c3b7-d945-461c-8841-03527e42621d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1070282451 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_dout_din_regs_random_rw.1070282451
Directory /workspace/33.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/33.gpio_filter_stress.1238413725
Short name T618
Test name
Test status
Simulation time 134704823 ps
CPU time 7.11 seconds
Started Jul 29 04:34:47 PM PDT 24
Finished Jul 29 04:34:54 PM PDT 24
Peak memory 198372 kb
Host smart-780021f5-b95a-45bf-9958-f11af2507051
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238413725 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_filter_stre
ss.1238413725
Directory /workspace/33.gpio_filter_stress/latest

Test location /workspace/coverage/default/33.gpio_full_random.281860047
Short name T32
Test name
Test status
Simulation time 861160229 ps
CPU time 1.04 seconds
Started Jul 29 04:34:49 PM PDT 24
Finished Jul 29 04:34:51 PM PDT 24
Peak memory 198272 kb
Host smart-85704a92-44f7-4798-867b-d71f10848647
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281860047 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_full_random.281860047
Directory /workspace/33.gpio_full_random/latest

Test location /workspace/coverage/default/33.gpio_intr_rand_pgm.2169378532
Short name T240
Test name
Test status
Simulation time 50249556 ps
CPU time 1.27 seconds
Started Jul 29 04:34:52 PM PDT 24
Finished Jul 29 04:34:53 PM PDT 24
Peak memory 197536 kb
Host smart-b821f293-cfcf-422d-91c7-371e56385619
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169378532 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_intr_rand_pgm.2169378532
Directory /workspace/33.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/33.gpio_intr_with_filter_rand_intr_event.3266202374
Short name T14
Test name
Test status
Simulation time 176600260 ps
CPU time 1.77 seconds
Started Jul 29 04:34:50 PM PDT 24
Finished Jul 29 04:34:52 PM PDT 24
Peak memory 197624 kb
Host smart-e1d9b552-3115-4a6e-b804-ef579f924b67
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266202374 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 33.gpio_intr_with_filter_rand_intr_event.3266202374
Directory /workspace/33.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/33.gpio_rand_intr_trigger.2456743513
Short name T446
Test name
Test status
Simulation time 142593321 ps
CPU time 2.2 seconds
Started Jul 29 04:34:52 PM PDT 24
Finished Jul 29 04:34:54 PM PDT 24
Peak memory 197528 kb
Host smart-d7938a1b-3d55-445e-97cf-236d182f1071
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456743513 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_rand_intr_trigger
.2456743513
Directory /workspace/33.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din.1340752342
Short name T709
Test name
Test status
Simulation time 91029020 ps
CPU time 0.96 seconds
Started Jul 29 04:34:52 PM PDT 24
Finished Jul 29 04:34:53 PM PDT 24
Peak memory 196264 kb
Host smart-8817904f-de32-463b-8bb4-ef6c591d0262
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1340752342 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din.1340752342
Directory /workspace/33.gpio_random_dout_din/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din_no_pullup_pulldown.3005803655
Short name T382
Test name
Test status
Simulation time 49105368 ps
CPU time 0.98 seconds
Started Jul 29 04:34:31 PM PDT 24
Finished Jul 29 04:34:32 PM PDT 24
Peak memory 196452 kb
Host smart-4270df3a-de3e-482e-895d-4e4709561bc3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005803655 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din_no_pullu
p_pulldown.3005803655
Directory /workspace/33.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_random_long_reg_writes_reg_reads.2525102602
Short name T532
Test name
Test status
Simulation time 107006350 ps
CPU time 4.82 seconds
Started Jul 29 04:34:52 PM PDT 24
Finished Jul 29 04:34:57 PM PDT 24
Peak memory 198380 kb
Host smart-7c8642d8-3c23-47fc-8b33-f7fd3d3b2d50
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525102602 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_ra
ndom_long_reg_writes_reg_reads.2525102602
Directory /workspace/33.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/33.gpio_smoke.3733763433
Short name T660
Test name
Test status
Simulation time 165422570 ps
CPU time 0.98 seconds
Started Jul 29 04:34:43 PM PDT 24
Finished Jul 29 04:34:44 PM PDT 24
Peak memory 196864 kb
Host smart-1d4b3ed3-23c4-4628-bed6-dc4150139d24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3733763433 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke.3733763433
Directory /workspace/33.gpio_smoke/latest

Test location /workspace/coverage/default/33.gpio_smoke_no_pullup_pulldown.3153764821
Short name T695
Test name
Test status
Simulation time 312925986 ps
CPU time 1.08 seconds
Started Jul 29 04:34:50 PM PDT 24
Finished Jul 29 04:34:52 PM PDT 24
Peak memory 195944 kb
Host smart-93d28b07-667b-4afb-8076-57206f547e83
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153764821 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown.3153764821
Directory /workspace/33.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_stress_all.3793278725
Short name T623
Test name
Test status
Simulation time 9274013390 ps
CPU time 37.73 seconds
Started Jul 29 04:34:56 PM PDT 24
Finished Jul 29 04:35:34 PM PDT 24
Peak memory 198564 kb
Host smart-55088987-6971-4321-a7be-b23eb8ffe285
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793278725 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.
gpio_stress_all.3793278725
Directory /workspace/33.gpio_stress_all/latest

Test location /workspace/coverage/default/33.gpio_stress_all_with_rand_reset.2342567137
Short name T555
Test name
Test status
Simulation time 90788336682 ps
CPU time 884.61 seconds
Started Jul 29 04:34:46 PM PDT 24
Finished Jul 29 04:49:31 PM PDT 24
Peak memory 198692 kb
Host smart-f12dafb1-4e98-4733-a700-1a47db60e3dd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2342567137 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_stress_all_with_rand_reset.2342567137
Directory /workspace/33.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.gpio_alert_test.1188931328
Short name T496
Test name
Test status
Simulation time 19879980 ps
CPU time 0.62 seconds
Started Jul 29 04:34:54 PM PDT 24
Finished Jul 29 04:34:54 PM PDT 24
Peak memory 194276 kb
Host smart-e39cbf42-8a1e-460e-a292-040699a516da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188931328 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_alert_test.1188931328
Directory /workspace/34.gpio_alert_test/latest

Test location /workspace/coverage/default/34.gpio_dout_din_regs_random_rw.3245533361
Short name T267
Test name
Test status
Simulation time 45968528 ps
CPU time 0.86 seconds
Started Jul 29 04:34:50 PM PDT 24
Finished Jul 29 04:34:51 PM PDT 24
Peak memory 196864 kb
Host smart-a26766b2-d7b0-451d-889e-d8d1615f20ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3245533361 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_dout_din_regs_random_rw.3245533361
Directory /workspace/34.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/34.gpio_filter_stress.1598509805
Short name T144
Test name
Test status
Simulation time 306040133 ps
CPU time 6.95 seconds
Started Jul 29 04:34:45 PM PDT 24
Finished Jul 29 04:34:52 PM PDT 24
Peak memory 198356 kb
Host smart-56e040c8-b709-4260-9e26-374b1a03862a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598509805 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_filter_stre
ss.1598509805
Directory /workspace/34.gpio_filter_stress/latest

Test location /workspace/coverage/default/34.gpio_full_random.3188372407
Short name T653
Test name
Test status
Simulation time 71146062 ps
CPU time 1.02 seconds
Started Jul 29 04:34:48 PM PDT 24
Finished Jul 29 04:34:49 PM PDT 24
Peak memory 196944 kb
Host smart-fbf7bae6-fc1c-4ac5-b150-3d43326ce4ee
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188372407 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_full_random.3188372407
Directory /workspace/34.gpio_full_random/latest

Test location /workspace/coverage/default/34.gpio_intr_rand_pgm.549349276
Short name T420
Test name
Test status
Simulation time 46228268 ps
CPU time 0.96 seconds
Started Jul 29 04:35:04 PM PDT 24
Finished Jul 29 04:35:06 PM PDT 24
Peak memory 197760 kb
Host smart-d9dc9e25-4e41-4118-a930-e48c7e2f8cb2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549349276 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_intr_rand_pgm.549349276
Directory /workspace/34.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/34.gpio_intr_with_filter_rand_intr_event.2757910662
Short name T604
Test name
Test status
Simulation time 50835993 ps
CPU time 1.07 seconds
Started Jul 29 04:34:56 PM PDT 24
Finished Jul 29 04:34:57 PM PDT 24
Peak memory 197572 kb
Host smart-7b8852aa-84ba-4f97-ba17-7908c1745537
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757910662 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.gpio_intr_with_filter_rand_intr_event.2757910662
Directory /workspace/34.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/34.gpio_rand_intr_trigger.2259393897
Short name T697
Test name
Test status
Simulation time 213935406 ps
CPU time 1.4 seconds
Started Jul 29 04:35:01 PM PDT 24
Finished Jul 29 04:35:03 PM PDT 24
Peak memory 196208 kb
Host smart-48d9d53d-d5cd-487a-ac8e-16ce7bb7437e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259393897 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_rand_intr_trigger
.2259393897
Directory /workspace/34.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din.816036626
Short name T59
Test name
Test status
Simulation time 46169520 ps
CPU time 1.02 seconds
Started Jul 29 04:34:54 PM PDT 24
Finished Jul 29 04:34:55 PM PDT 24
Peak memory 196456 kb
Host smart-ebf0dd98-0496-463d-93e1-8f62ac100644
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=816036626 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din.816036626
Directory /workspace/34.gpio_random_dout_din/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din_no_pullup_pulldown.2178870718
Short name T224
Test name
Test status
Simulation time 71860305 ps
CPU time 1.22 seconds
Started Jul 29 04:34:47 PM PDT 24
Finished Jul 29 04:34:49 PM PDT 24
Peak memory 196256 kb
Host smart-be004443-160b-40e9-b228-85673dbd8e9e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178870718 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din_no_pullu
p_pulldown.2178870718
Directory /workspace/34.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_random_long_reg_writes_reg_reads.4128010628
Short name T579
Test name
Test status
Simulation time 218599518 ps
CPU time 1.66 seconds
Started Jul 29 04:34:48 PM PDT 24
Finished Jul 29 04:34:50 PM PDT 24
Peak memory 198380 kb
Host smart-1a06417a-d4f2-4919-bc5a-8918e4101d5c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128010628 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_ra
ndom_long_reg_writes_reg_reads.4128010628
Directory /workspace/34.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/34.gpio_smoke.1809266141
Short name T95
Test name
Test status
Simulation time 146595777 ps
CPU time 1.2 seconds
Started Jul 29 04:34:51 PM PDT 24
Finished Jul 29 04:34:53 PM PDT 24
Peak memory 195820 kb
Host smart-bf6d2996-3da6-45aa-8911-ad41b458464a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1809266141 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke.1809266141
Directory /workspace/34.gpio_smoke/latest

Test location /workspace/coverage/default/34.gpio_smoke_no_pullup_pulldown.3152766615
Short name T279
Test name
Test status
Simulation time 56303803 ps
CPU time 1.1 seconds
Started Jul 29 04:34:50 PM PDT 24
Finished Jul 29 04:34:51 PM PDT 24
Peak memory 195980 kb
Host smart-d037e7ec-73c6-4791-b582-ab33927fe909
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152766615 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown.3152766615
Directory /workspace/34.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_stress_all.2560851140
Short name T269
Test name
Test status
Simulation time 68787002522 ps
CPU time 238.5 seconds
Started Jul 29 04:34:55 PM PDT 24
Finished Jul 29 04:38:53 PM PDT 24
Peak memory 198564 kb
Host smart-c85f0268-6be9-4ca7-bfbf-6af6b37c527e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560851140 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.
gpio_stress_all.2560851140
Directory /workspace/34.gpio_stress_all/latest

Test location /workspace/coverage/default/35.gpio_alert_test.688691325
Short name T544
Test name
Test status
Simulation time 36582078 ps
CPU time 0.55 seconds
Started Jul 29 04:34:56 PM PDT 24
Finished Jul 29 04:34:57 PM PDT 24
Peak memory 194224 kb
Host smart-5a15b75b-a16d-4653-82f1-032a3b0d4257
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688691325 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_alert_test.688691325
Directory /workspace/35.gpio_alert_test/latest

Test location /workspace/coverage/default/35.gpio_dout_din_regs_random_rw.3656265339
Short name T24
Test name
Test status
Simulation time 84379322 ps
CPU time 0.71 seconds
Started Jul 29 04:35:09 PM PDT 24
Finished Jul 29 04:35:10 PM PDT 24
Peak memory 194500 kb
Host smart-d2483908-f81b-4e08-8269-6822a824626f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3656265339 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_dout_din_regs_random_rw.3656265339
Directory /workspace/35.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/35.gpio_filter_stress.1193112906
Short name T488
Test name
Test status
Simulation time 1529604986 ps
CPU time 18.98 seconds
Started Jul 29 04:34:50 PM PDT 24
Finished Jul 29 04:35:09 PM PDT 24
Peak memory 195944 kb
Host smart-4fcb0f91-6a21-4b1e-ab2d-173eadcc9a45
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193112906 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_filter_stre
ss.1193112906
Directory /workspace/35.gpio_filter_stress/latest

Test location /workspace/coverage/default/35.gpio_full_random.82136354
Short name T398
Test name
Test status
Simulation time 179166918 ps
CPU time 0.77 seconds
Started Jul 29 04:35:01 PM PDT 24
Finished Jul 29 04:35:01 PM PDT 24
Peak memory 196288 kb
Host smart-9bf3273f-4c44-4038-86e9-df12e56f48d4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82136354 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_full_random.82136354
Directory /workspace/35.gpio_full_random/latest

Test location /workspace/coverage/default/35.gpio_intr_rand_pgm.1620489173
Short name T137
Test name
Test status
Simulation time 101017344 ps
CPU time 1.37 seconds
Started Jul 29 04:34:52 PM PDT 24
Finished Jul 29 04:34:53 PM PDT 24
Peak memory 197488 kb
Host smart-030fbe58-9841-469d-afea-ec777f5e93d1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620489173 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_intr_rand_pgm.1620489173
Directory /workspace/35.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/35.gpio_intr_with_filter_rand_intr_event.1076549332
Short name T599
Test name
Test status
Simulation time 169837101 ps
CPU time 1.95 seconds
Started Jul 29 04:34:56 PM PDT 24
Finished Jul 29 04:34:58 PM PDT 24
Peak memory 196688 kb
Host smart-bb9f47cf-2904-4f7e-96a5-36cdfc9d77a0
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076549332 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 35.gpio_intr_with_filter_rand_intr_event.1076549332
Directory /workspace/35.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/35.gpio_rand_intr_trigger.1968767179
Short name T459
Test name
Test status
Simulation time 181133696 ps
CPU time 3.47 seconds
Started Jul 29 04:35:08 PM PDT 24
Finished Jul 29 04:35:12 PM PDT 24
Peak memory 197560 kb
Host smart-8a22bcc0-1c0d-4e16-bee1-6f0cb831d036
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968767179 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_rand_intr_trigger
.1968767179
Directory /workspace/35.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din.2309863262
Short name T275
Test name
Test status
Simulation time 57875720 ps
CPU time 1.12 seconds
Started Jul 29 04:35:03 PM PDT 24
Finished Jul 29 04:35:04 PM PDT 24
Peak memory 196192 kb
Host smart-a47152ba-3aad-4fc1-b346-f717067ee08e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309863262 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din.2309863262
Directory /workspace/35.gpio_random_dout_din/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din_no_pullup_pulldown.3389460729
Short name T160
Test name
Test status
Simulation time 46935524 ps
CPU time 1.09 seconds
Started Jul 29 04:34:48 PM PDT 24
Finished Jul 29 04:34:49 PM PDT 24
Peak memory 196752 kb
Host smart-fa4eebe5-7b76-4022-94ab-55954b2dc9ce
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389460729 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din_no_pullu
p_pulldown.3389460729
Directory /workspace/35.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_random_long_reg_writes_reg_reads.3587294493
Short name T569
Test name
Test status
Simulation time 95824630 ps
CPU time 4.16 seconds
Started Jul 29 04:34:55 PM PDT 24
Finished Jul 29 04:34:59 PM PDT 24
Peak memory 198364 kb
Host smart-04e42de3-9576-450d-93f5-7f25706a7a7b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587294493 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_ra
ndom_long_reg_writes_reg_reads.3587294493
Directory /workspace/35.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/35.gpio_smoke.308819992
Short name T581
Test name
Test status
Simulation time 304990896 ps
CPU time 1.1 seconds
Started Jul 29 04:34:55 PM PDT 24
Finished Jul 29 04:34:56 PM PDT 24
Peak memory 196132 kb
Host smart-1e9d983c-94cf-4556-9a18-560e782057a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=308819992 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke.308819992
Directory /workspace/35.gpio_smoke/latest

Test location /workspace/coverage/default/35.gpio_smoke_no_pullup_pulldown.3396764991
Short name T563
Test name
Test status
Simulation time 77560989 ps
CPU time 1.19 seconds
Started Jul 29 04:34:45 PM PDT 24
Finished Jul 29 04:34:47 PM PDT 24
Peak memory 196168 kb
Host smart-765199d6-2da2-4782-b00c-73c79f286b3f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396764991 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown.3396764991
Directory /workspace/35.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_stress_all.3487197318
Short name T20
Test name
Test status
Simulation time 69388127289 ps
CPU time 61.56 seconds
Started Jul 29 04:34:48 PM PDT 24
Finished Jul 29 04:35:50 PM PDT 24
Peak memory 198596 kb
Host smart-e025d8f4-dec5-4aee-b56b-2eded453ce63
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487197318 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.
gpio_stress_all.3487197318
Directory /workspace/35.gpio_stress_all/latest

Test location /workspace/coverage/default/35.gpio_stress_all_with_rand_reset.3190028786
Short name T36
Test name
Test status
Simulation time 19188267536 ps
CPU time 563.67 seconds
Started Jul 29 04:34:55 PM PDT 24
Finished Jul 29 04:44:19 PM PDT 24
Peak memory 198708 kb
Host smart-76cea886-bfc0-4c78-9b1f-e564c4586af0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3190028786 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_stress_all_with_rand_reset.3190028786
Directory /workspace/35.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.gpio_alert_test.4188487784
Short name T707
Test name
Test status
Simulation time 77912519 ps
CPU time 0.57 seconds
Started Jul 29 04:34:52 PM PDT 24
Finished Jul 29 04:34:53 PM PDT 24
Peak memory 194952 kb
Host smart-a590a1e5-8f98-44c2-a138-f7551a8b6ccf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188487784 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_alert_test.4188487784
Directory /workspace/36.gpio_alert_test/latest

Test location /workspace/coverage/default/36.gpio_dout_din_regs_random_rw.748689704
Short name T219
Test name
Test status
Simulation time 61516433 ps
CPU time 0.74 seconds
Started Jul 29 04:34:56 PM PDT 24
Finished Jul 29 04:34:57 PM PDT 24
Peak memory 195684 kb
Host smart-4a22159a-de97-4043-ae65-27d0ba8e4460
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=748689704 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_dout_din_regs_random_rw.748689704
Directory /workspace/36.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/36.gpio_filter_stress.472077858
Short name T201
Test name
Test status
Simulation time 1961823585 ps
CPU time 14.71 seconds
Started Jul 29 04:34:53 PM PDT 24
Finished Jul 29 04:35:08 PM PDT 24
Peak memory 195940 kb
Host smart-27cf61c5-9505-4c9a-b73f-a5f51f35fa3b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472077858 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_filter_stres
s.472077858
Directory /workspace/36.gpio_filter_stress/latest

Test location /workspace/coverage/default/36.gpio_full_random.3916053969
Short name T541
Test name
Test status
Simulation time 124453432 ps
CPU time 0.67 seconds
Started Jul 29 04:34:55 PM PDT 24
Finished Jul 29 04:34:56 PM PDT 24
Peak memory 195088 kb
Host smart-f13c4c8a-7320-406c-93a1-64e1658d3b73
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916053969 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_full_random.3916053969
Directory /workspace/36.gpio_full_random/latest

Test location /workspace/coverage/default/36.gpio_intr_rand_pgm.3509482831
Short name T474
Test name
Test status
Simulation time 39447109 ps
CPU time 0.78 seconds
Started Jul 29 04:34:49 PM PDT 24
Finished Jul 29 04:34:50 PM PDT 24
Peak memory 195968 kb
Host smart-b8b05b2e-3c03-4c1c-ba9a-ea3bc13a54f5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509482831 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_intr_rand_pgm.3509482831
Directory /workspace/36.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/36.gpio_intr_with_filter_rand_intr_event.2300384796
Short name T204
Test name
Test status
Simulation time 63604552 ps
CPU time 2.29 seconds
Started Jul 29 04:34:45 PM PDT 24
Finished Jul 29 04:34:48 PM PDT 24
Peak memory 198380 kb
Host smart-1acc4b88-9d39-450f-badb-44ab939b5b77
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300384796 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 36.gpio_intr_with_filter_rand_intr_event.2300384796
Directory /workspace/36.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/36.gpio_rand_intr_trigger.923554243
Short name T641
Test name
Test status
Simulation time 103604272 ps
CPU time 2.06 seconds
Started Jul 29 04:35:01 PM PDT 24
Finished Jul 29 04:35:03 PM PDT 24
Peak memory 196184 kb
Host smart-4393c809-7c76-42cb-937d-4503f28cb617
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923554243 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_rand_intr_trigger.
923554243
Directory /workspace/36.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din.1041139307
Short name T146
Test name
Test status
Simulation time 232522931 ps
CPU time 1.22 seconds
Started Jul 29 04:34:52 PM PDT 24
Finished Jul 29 04:34:53 PM PDT 24
Peak memory 197396 kb
Host smart-7f1596d3-e57c-4a18-ae50-2004a4c0b7a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1041139307 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din.1041139307
Directory /workspace/36.gpio_random_dout_din/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din_no_pullup_pulldown.1491060153
Short name T720
Test name
Test status
Simulation time 51994670 ps
CPU time 1.03 seconds
Started Jul 29 04:34:49 PM PDT 24
Finished Jul 29 04:34:50 PM PDT 24
Peak memory 196340 kb
Host smart-fc253a5e-1f57-4844-b6a9-f76b5641c9ec
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491060153 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din_no_pullu
p_pulldown.1491060153
Directory /workspace/36.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_random_long_reg_writes_reg_reads.139082873
Short name T399
Test name
Test status
Simulation time 368196305 ps
CPU time 3.12 seconds
Started Jul 29 04:34:58 PM PDT 24
Finished Jul 29 04:35:01 PM PDT 24
Peak memory 198532 kb
Host smart-af100356-c70d-4ecd-a0c7-f5fc8a4420bf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139082873 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_ran
dom_long_reg_writes_reg_reads.139082873
Directory /workspace/36.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/36.gpio_smoke.3503070298
Short name T125
Test name
Test status
Simulation time 76042465 ps
CPU time 1.21 seconds
Started Jul 29 04:34:57 PM PDT 24
Finished Jul 29 04:34:58 PM PDT 24
Peak memory 196192 kb
Host smart-f66d4b51-d358-468b-9dbb-7dbfe7b0d22c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503070298 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke.3503070298
Directory /workspace/36.gpio_smoke/latest

Test location /workspace/coverage/default/36.gpio_smoke_no_pullup_pulldown.220094715
Short name T657
Test name
Test status
Simulation time 242884466 ps
CPU time 1.28 seconds
Started Jul 29 04:34:49 PM PDT 24
Finished Jul 29 04:34:50 PM PDT 24
Peak memory 197020 kb
Host smart-afe0deba-063e-4b31-9c4e-48f8ab119dd8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220094715 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown.220094715
Directory /workspace/36.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_stress_all.4207249292
Short name T428
Test name
Test status
Simulation time 20411555281 ps
CPU time 216.96 seconds
Started Jul 29 04:34:55 PM PDT 24
Finished Jul 29 04:38:32 PM PDT 24
Peak memory 198524 kb
Host smart-190dbfb9-689f-46d2-a438-c6aa3fde3f73
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207249292 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.
gpio_stress_all.4207249292
Directory /workspace/36.gpio_stress_all/latest

Test location /workspace/coverage/default/36.gpio_stress_all_with_rand_reset.1714343708
Short name T412
Test name
Test status
Simulation time 274409157265 ps
CPU time 2300.96 seconds
Started Jul 29 04:34:53 PM PDT 24
Finished Jul 29 05:13:15 PM PDT 24
Peak memory 198688 kb
Host smart-36213a09-29d2-41d5-a107-9ee7a8087ffd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1714343708 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_stress_all_with_rand_reset.1714343708
Directory /workspace/36.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.gpio_alert_test.3363648346
Short name T307
Test name
Test status
Simulation time 11858864 ps
CPU time 0.56 seconds
Started Jul 29 04:35:01 PM PDT 24
Finished Jul 29 04:35:02 PM PDT 24
Peak memory 194336 kb
Host smart-995764d8-ac92-4653-b49a-a1865a8a9c2c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363648346 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_alert_test.3363648346
Directory /workspace/37.gpio_alert_test/latest

Test location /workspace/coverage/default/37.gpio_dout_din_regs_random_rw.4141796213
Short name T101
Test name
Test status
Simulation time 147694025 ps
CPU time 0.93 seconds
Started Jul 29 04:34:54 PM PDT 24
Finished Jul 29 04:34:55 PM PDT 24
Peak memory 197208 kb
Host smart-a97e4998-c779-4c6f-b879-f8d03892d1c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4141796213 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_dout_din_regs_random_rw.4141796213
Directory /workspace/37.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/37.gpio_filter_stress.260180938
Short name T486
Test name
Test status
Simulation time 828306335 ps
CPU time 6.09 seconds
Started Jul 29 04:35:00 PM PDT 24
Finished Jul 29 04:35:12 PM PDT 24
Peak memory 198492 kb
Host smart-343a349e-4454-4ae8-b365-1509332e92f8
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260180938 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_filter_stres
s.260180938
Directory /workspace/37.gpio_filter_stress/latest

Test location /workspace/coverage/default/37.gpio_full_random.3767468159
Short name T237
Test name
Test status
Simulation time 30591824 ps
CPU time 0.63 seconds
Started Jul 29 04:34:54 PM PDT 24
Finished Jul 29 04:34:54 PM PDT 24
Peak memory 195528 kb
Host smart-9dab3708-33ba-4d0d-9ca9-2600cf7efbd2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767468159 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_full_random.3767468159
Directory /workspace/37.gpio_full_random/latest

Test location /workspace/coverage/default/37.gpio_intr_rand_pgm.888675678
Short name T156
Test name
Test status
Simulation time 262894697 ps
CPU time 1.13 seconds
Started Jul 29 04:34:57 PM PDT 24
Finished Jul 29 04:34:58 PM PDT 24
Peak memory 196304 kb
Host smart-89e62a95-959b-4abc-a5ed-2d9ff30307c1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888675678 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_intr_rand_pgm.888675678
Directory /workspace/37.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/37.gpio_intr_with_filter_rand_intr_event.1174441441
Short name T154
Test name
Test status
Simulation time 24516327 ps
CPU time 0.94 seconds
Started Jul 29 04:34:50 PM PDT 24
Finished Jul 29 04:34:51 PM PDT 24
Peak memory 196532 kb
Host smart-7c1f9fdc-2016-4943-a037-f3976ccebda3
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174441441 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 37.gpio_intr_with_filter_rand_intr_event.1174441441
Directory /workspace/37.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/37.gpio_rand_intr_trigger.205148389
Short name T171
Test name
Test status
Simulation time 259079740 ps
CPU time 2.04 seconds
Started Jul 29 04:35:00 PM PDT 24
Finished Jul 29 04:35:02 PM PDT 24
Peak memory 197116 kb
Host smart-3c5e642f-d824-413e-82c1-4de4a0dba3c3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205148389 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_rand_intr_trigger.
205148389
Directory /workspace/37.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din.1084540915
Short name T241
Test name
Test status
Simulation time 50199103 ps
CPU time 0.79 seconds
Started Jul 29 04:35:01 PM PDT 24
Finished Jul 29 04:35:02 PM PDT 24
Peak memory 196540 kb
Host smart-be2f5971-8aae-48a1-86d0-b9f04ead8739
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1084540915 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din.1084540915
Directory /workspace/37.gpio_random_dout_din/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din_no_pullup_pulldown.1890914519
Short name T140
Test name
Test status
Simulation time 142039817 ps
CPU time 1.25 seconds
Started Jul 29 04:34:51 PM PDT 24
Finished Jul 29 04:34:53 PM PDT 24
Peak memory 197396 kb
Host smart-a81ce1e0-07aa-41c6-b654-518d62aa52cd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890914519 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din_no_pullu
p_pulldown.1890914519
Directory /workspace/37.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_random_long_reg_writes_reg_reads.3591086067
Short name T679
Test name
Test status
Simulation time 130537973 ps
CPU time 3.27 seconds
Started Jul 29 04:34:53 PM PDT 24
Finished Jul 29 04:34:56 PM PDT 24
Peak memory 198368 kb
Host smart-a15d0278-41d5-4ff7-b98c-c4a8848f6b5a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591086067 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_ra
ndom_long_reg_writes_reg_reads.3591086067
Directory /workspace/37.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/37.gpio_smoke.1364184106
Short name T374
Test name
Test status
Simulation time 28723931 ps
CPU time 0.89 seconds
Started Jul 29 04:35:01 PM PDT 24
Finished Jul 29 04:35:02 PM PDT 24
Peak memory 196100 kb
Host smart-d0751bcb-b6f5-4785-b726-82a203fc85e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1364184106 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke.1364184106
Directory /workspace/37.gpio_smoke/latest

Test location /workspace/coverage/default/37.gpio_smoke_no_pullup_pulldown.1208580378
Short name T650
Test name
Test status
Simulation time 73825322 ps
CPU time 1.07 seconds
Started Jul 29 04:34:53 PM PDT 24
Finished Jul 29 04:34:54 PM PDT 24
Peak memory 195940 kb
Host smart-a462fbcf-3f62-4cda-8821-67848909c6d4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208580378 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown.1208580378
Directory /workspace/37.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_stress_all.870478087
Short name T628
Test name
Test status
Simulation time 11674044616 ps
CPU time 144.18 seconds
Started Jul 29 04:34:55 PM PDT 24
Finished Jul 29 04:37:20 PM PDT 24
Peak memory 198636 kb
Host smart-2a9064cb-d78e-4663-bcbb-2a1f5941cf84
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870478087 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.g
pio_stress_all.870478087
Directory /workspace/37.gpio_stress_all/latest

Test location /workspace/coverage/default/37.gpio_stress_all_with_rand_reset.681964864
Short name T687
Test name
Test status
Simulation time 28359240965 ps
CPU time 396.85 seconds
Started Jul 29 04:34:56 PM PDT 24
Finished Jul 29 04:41:33 PM PDT 24
Peak memory 198740 kb
Host smart-4b6e62d3-6347-4ab6-8019-15a6bfcdf4be
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=681964864 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_stress_all_with_rand_reset.681964864
Directory /workspace/37.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.gpio_alert_test.4099980507
Short name T719
Test name
Test status
Simulation time 14819288 ps
CPU time 0.62 seconds
Started Jul 29 04:34:58 PM PDT 24
Finished Jul 29 04:34:59 PM PDT 24
Peak memory 194492 kb
Host smart-2d6bc74a-653a-4f88-8dbb-bcc1dae9d62c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099980507 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_alert_test.4099980507
Directory /workspace/38.gpio_alert_test/latest

Test location /workspace/coverage/default/38.gpio_dout_din_regs_random_rw.600491713
Short name T658
Test name
Test status
Simulation time 19343528 ps
CPU time 0.67 seconds
Started Jul 29 04:34:58 PM PDT 24
Finished Jul 29 04:34:59 PM PDT 24
Peak memory 194424 kb
Host smart-c05cd161-de81-46b6-995b-dbd1cf0a7f20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600491713 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_dout_din_regs_random_rw.600491713
Directory /workspace/38.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/38.gpio_filter_stress.778702891
Short name T501
Test name
Test status
Simulation time 323940854 ps
CPU time 4.45 seconds
Started Jul 29 04:35:07 PM PDT 24
Finished Jul 29 04:35:12 PM PDT 24
Peak memory 196912 kb
Host smart-68e13904-c022-433e-a1d0-c1ca111a5afd
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778702891 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_filter_stres
s.778702891
Directory /workspace/38.gpio_filter_stress/latest

Test location /workspace/coverage/default/38.gpio_full_random.1663250436
Short name T395
Test name
Test status
Simulation time 59083403 ps
CPU time 0.88 seconds
Started Jul 29 04:35:02 PM PDT 24
Finished Jul 29 04:35:03 PM PDT 24
Peak memory 197040 kb
Host smart-9653ddde-5d4f-4cad-aaf6-70212a51a58f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663250436 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_full_random.1663250436
Directory /workspace/38.gpio_full_random/latest

Test location /workspace/coverage/default/38.gpio_intr_rand_pgm.1339633261
Short name T208
Test name
Test status
Simulation time 22143703 ps
CPU time 0.79 seconds
Started Jul 29 04:34:55 PM PDT 24
Finished Jul 29 04:34:56 PM PDT 24
Peak memory 195912 kb
Host smart-74faf29f-fb10-42bb-ac96-5faf240be6e4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339633261 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_intr_rand_pgm.1339633261
Directory /workspace/38.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/38.gpio_intr_with_filter_rand_intr_event.3932511552
Short name T620
Test name
Test status
Simulation time 306881354 ps
CPU time 2.97 seconds
Started Jul 29 04:35:02 PM PDT 24
Finished Jul 29 04:35:05 PM PDT 24
Peak memory 198648 kb
Host smart-77527290-523b-4ea1-aab4-54d1ec491ec3
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932511552 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 38.gpio_intr_with_filter_rand_intr_event.3932511552
Directory /workspace/38.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/38.gpio_rand_intr_trigger.3311745750
Short name T304
Test name
Test status
Simulation time 314071997 ps
CPU time 1.83 seconds
Started Jul 29 04:34:53 PM PDT 24
Finished Jul 29 04:34:55 PM PDT 24
Peak memory 196824 kb
Host smart-5bf313df-711a-49c3-aaf2-23c02c56ed83
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311745750 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_rand_intr_trigger
.3311745750
Directory /workspace/38.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din.1235782129
Short name T542
Test name
Test status
Simulation time 101740359 ps
CPU time 1.05 seconds
Started Jul 29 04:35:02 PM PDT 24
Finished Jul 29 04:35:04 PM PDT 24
Peak memory 196908 kb
Host smart-769e5bd7-e59c-45b0-872c-b0f7c18711c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235782129 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din.1235782129
Directory /workspace/38.gpio_random_dout_din/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din_no_pullup_pulldown.3388503187
Short name T715
Test name
Test status
Simulation time 39870534 ps
CPU time 1.07 seconds
Started Jul 29 04:34:56 PM PDT 24
Finished Jul 29 04:34:57 PM PDT 24
Peak memory 196460 kb
Host smart-3df7deaf-88c9-4125-ac69-e3eee7ee071f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388503187 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din_no_pullu
p_pulldown.3388503187
Directory /workspace/38.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_random_long_reg_writes_reg_reads.268221927
Short name T27
Test name
Test status
Simulation time 2963528183 ps
CPU time 6.28 seconds
Started Jul 29 04:35:01 PM PDT 24
Finished Jul 29 04:35:13 PM PDT 24
Peak memory 198460 kb
Host smart-8cbf06ed-470a-4e9d-8862-cdb49fbf0553
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268221927 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_ran
dom_long_reg_writes_reg_reads.268221927
Directory /workspace/38.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/38.gpio_smoke.1409824888
Short name T565
Test name
Test status
Simulation time 66231123 ps
CPU time 1.3 seconds
Started Jul 29 04:34:58 PM PDT 24
Finished Jul 29 04:34:59 PM PDT 24
Peak memory 198332 kb
Host smart-53d5c242-dc84-49ec-84b2-24a89f9a4f8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1409824888 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke.1409824888
Directory /workspace/38.gpio_smoke/latest

Test location /workspace/coverage/default/38.gpio_smoke_no_pullup_pulldown.2300334050
Short name T200
Test name
Test status
Simulation time 48346441 ps
CPU time 1.29 seconds
Started Jul 29 04:34:58 PM PDT 24
Finished Jul 29 04:35:00 PM PDT 24
Peak memory 197320 kb
Host smart-4bb1c5e7-a1ef-4316-8e89-2683fc083b6d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300334050 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown.2300334050
Directory /workspace/38.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_stress_all.3399565725
Short name T336
Test name
Test status
Simulation time 65004371087 ps
CPU time 179.11 seconds
Started Jul 29 04:35:00 PM PDT 24
Finished Jul 29 04:38:00 PM PDT 24
Peak memory 198620 kb
Host smart-c0461b5d-9a37-4571-8d8a-c12c7af9e5e5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399565725 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.
gpio_stress_all.3399565725
Directory /workspace/38.gpio_stress_all/latest

Test location /workspace/coverage/default/38.gpio_stress_all_with_rand_reset.3570997456
Short name T65
Test name
Test status
Simulation time 35314178144 ps
CPU time 581.71 seconds
Started Jul 29 04:34:54 PM PDT 24
Finished Jul 29 04:44:36 PM PDT 24
Peak memory 198824 kb
Host smart-125bbe85-2ff3-47ee-b7a4-f31adf9c50d6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3570997456 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_stress_all_with_rand_reset.3570997456
Directory /workspace/38.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.gpio_alert_test.2614198050
Short name T162
Test name
Test status
Simulation time 54228980 ps
CPU time 0.63 seconds
Started Jul 29 04:35:04 PM PDT 24
Finished Jul 29 04:35:05 PM PDT 24
Peak memory 194892 kb
Host smart-9376d1af-1251-4c86-aed2-67440fd953f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614198050 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_alert_test.2614198050
Directory /workspace/39.gpio_alert_test/latest

Test location /workspace/coverage/default/39.gpio_dout_din_regs_random_rw.450104645
Short name T703
Test name
Test status
Simulation time 52188215 ps
CPU time 0.71 seconds
Started Jul 29 04:34:52 PM PDT 24
Finished Jul 29 04:34:53 PM PDT 24
Peak memory 194348 kb
Host smart-0b8119d1-d1eb-4b14-bb06-8868fbb962e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=450104645 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_dout_din_regs_random_rw.450104645
Directory /workspace/39.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/39.gpio_filter_stress.3215242557
Short name T509
Test name
Test status
Simulation time 276293388 ps
CPU time 9.78 seconds
Started Jul 29 04:34:59 PM PDT 24
Finished Jul 29 04:35:09 PM PDT 24
Peak memory 198364 kb
Host smart-728fae46-6a25-4236-a8c2-5414b638e47a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215242557 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_filter_stre
ss.3215242557
Directory /workspace/39.gpio_filter_stress/latest

Test location /workspace/coverage/default/39.gpio_full_random.2103784537
Short name T170
Test name
Test status
Simulation time 44371937 ps
CPU time 0.8 seconds
Started Jul 29 04:35:09 PM PDT 24
Finished Jul 29 04:35:10 PM PDT 24
Peak memory 196200 kb
Host smart-fbe09e5c-7159-4a47-908a-7aab75f2132f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103784537 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_full_random.2103784537
Directory /workspace/39.gpio_full_random/latest

Test location /workspace/coverage/default/39.gpio_intr_rand_pgm.1790856190
Short name T673
Test name
Test status
Simulation time 53420107 ps
CPU time 1.31 seconds
Started Jul 29 04:34:53 PM PDT 24
Finished Jul 29 04:34:55 PM PDT 24
Peak memory 198412 kb
Host smart-91128da0-4f04-4cc7-b855-36dc834fb0d9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790856190 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_intr_rand_pgm.1790856190
Directory /workspace/39.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/39.gpio_intr_with_filter_rand_intr_event.2982746926
Short name T285
Test name
Test status
Simulation time 169415125 ps
CPU time 3.53 seconds
Started Jul 29 04:34:59 PM PDT 24
Finished Jul 29 04:35:02 PM PDT 24
Peak memory 198608 kb
Host smart-674ab3ee-4289-4782-90f3-d2b6956ff151
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982746926 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 39.gpio_intr_with_filter_rand_intr_event.2982746926
Directory /workspace/39.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/39.gpio_rand_intr_trigger.3075577471
Short name T314
Test name
Test status
Simulation time 57398307 ps
CPU time 1.48 seconds
Started Jul 29 04:34:54 PM PDT 24
Finished Jul 29 04:34:56 PM PDT 24
Peak memory 196460 kb
Host smart-16c0e90b-cb2c-4fbb-b2b6-440cb66835f6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075577471 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_rand_intr_trigger
.3075577471
Directory /workspace/39.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din.2144890016
Short name T150
Test name
Test status
Simulation time 97263714 ps
CPU time 0.86 seconds
Started Jul 29 04:35:04 PM PDT 24
Finished Jul 29 04:35:06 PM PDT 24
Peak memory 197720 kb
Host smart-dc899007-1070-4f39-80e9-365360246b24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2144890016 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din.2144890016
Directory /workspace/39.gpio_random_dout_din/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din_no_pullup_pulldown.3266220485
Short name T333
Test name
Test status
Simulation time 20038843 ps
CPU time 0.79 seconds
Started Jul 29 04:34:56 PM PDT 24
Finished Jul 29 04:34:57 PM PDT 24
Peak memory 196908 kb
Host smart-55ad4d2e-b9dc-451e-8e63-aebf35ba0ce7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266220485 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din_no_pullu
p_pulldown.3266220485
Directory /workspace/39.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_random_long_reg_writes_reg_reads.2453477778
Short name T422
Test name
Test status
Simulation time 141140392 ps
CPU time 3.74 seconds
Started Jul 29 04:34:55 PM PDT 24
Finished Jul 29 04:34:59 PM PDT 24
Peak memory 198288 kb
Host smart-20353aa9-036f-4efb-9e75-c4a1e23a0516
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453477778 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_ra
ndom_long_reg_writes_reg_reads.2453477778
Directory /workspace/39.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/39.gpio_smoke.1119675106
Short name T337
Test name
Test status
Simulation time 256593783 ps
CPU time 0.7 seconds
Started Jul 29 04:34:57 PM PDT 24
Finished Jul 29 04:34:58 PM PDT 24
Peak memory 194556 kb
Host smart-9785d8d4-2d65-4a9a-bb81-229449bfbab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1119675106 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke.1119675106
Directory /workspace/39.gpio_smoke/latest

Test location /workspace/coverage/default/39.gpio_smoke_no_pullup_pulldown.2079658691
Short name T291
Test name
Test status
Simulation time 98098928 ps
CPU time 1.28 seconds
Started Jul 29 04:34:49 PM PDT 24
Finished Jul 29 04:34:50 PM PDT 24
Peak memory 197216 kb
Host smart-ab36afd0-336e-4792-9008-d388344ef634
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079658691 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown.2079658691
Directory /workspace/39.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_stress_all.3323066335
Short name T655
Test name
Test status
Simulation time 61880371310 ps
CPU time 223.04 seconds
Started Jul 29 04:35:01 PM PDT 24
Finished Jul 29 04:38:44 PM PDT 24
Peak memory 198552 kb
Host smart-ab0407d2-3e77-44a8-bca7-b3bb12febe12
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323066335 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.
gpio_stress_all.3323066335
Directory /workspace/39.gpio_stress_all/latest

Test location /workspace/coverage/default/4.gpio_alert_test.1423221434
Short name T589
Test name
Test status
Simulation time 11819924 ps
CPU time 0.57 seconds
Started Jul 29 04:33:48 PM PDT 24
Finished Jul 29 04:33:49 PM PDT 24
Peak memory 194340 kb
Host smart-95f91934-4ef5-435c-acf6-33a06dba3856
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423221434 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_alert_test.1423221434
Directory /workspace/4.gpio_alert_test/latest

Test location /workspace/coverage/default/4.gpio_dout_din_regs_random_rw.3068668805
Short name T464
Test name
Test status
Simulation time 81115428 ps
CPU time 0.62 seconds
Started Jul 29 04:33:32 PM PDT 24
Finished Jul 29 04:33:33 PM PDT 24
Peak memory 194468 kb
Host smart-9f4ea427-8f47-4a3a-826f-7bff834fcee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3068668805 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_dout_din_regs_random_rw.3068668805
Directory /workspace/4.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/4.gpio_filter_stress.3222133846
Short name T330
Test name
Test status
Simulation time 747970167 ps
CPU time 25.42 seconds
Started Jul 29 04:33:32 PM PDT 24
Finished Jul 29 04:33:57 PM PDT 24
Peak memory 198344 kb
Host smart-6cf8e7b6-67a8-4bde-a1ca-ac12f85b131f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222133846 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_filter_stres
s.3222133846
Directory /workspace/4.gpio_filter_stress/latest

Test location /workspace/coverage/default/4.gpio_full_random.985463474
Short name T31
Test name
Test status
Simulation time 85952510 ps
CPU time 1.06 seconds
Started Jul 29 04:33:48 PM PDT 24
Finished Jul 29 04:33:49 PM PDT 24
Peak memory 196828 kb
Host smart-8202e287-0018-4d4f-b801-e4cc2a51640c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985463474 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_full_random.985463474
Directory /workspace/4.gpio_full_random/latest

Test location /workspace/coverage/default/4.gpio_intr_rand_pgm.2810411385
Short name T678
Test name
Test status
Simulation time 110243451 ps
CPU time 1.34 seconds
Started Jul 29 04:33:46 PM PDT 24
Finished Jul 29 04:33:47 PM PDT 24
Peak memory 197428 kb
Host smart-6b362439-487f-4499-a358-e7e74d28aeea
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810411385 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_intr_rand_pgm.2810411385
Directory /workspace/4.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/4.gpio_intr_with_filter_rand_intr_event.3396997955
Short name T220
Test name
Test status
Simulation time 42601464 ps
CPU time 1.04 seconds
Started Jul 29 04:33:40 PM PDT 24
Finished Jul 29 04:33:41 PM PDT 24
Peak memory 197228 kb
Host smart-f8f322ca-aedf-4904-ba05-5fa85626d792
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396997955 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.gpio_intr_with_filter_rand_intr_event.3396997955
Directory /workspace/4.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/4.gpio_rand_intr_trigger.2220044575
Short name T468
Test name
Test status
Simulation time 235558285 ps
CPU time 1.5 seconds
Started Jul 29 04:33:32 PM PDT 24
Finished Jul 29 04:33:34 PM PDT 24
Peak memory 196196 kb
Host smart-35fa27af-168e-493e-8188-45724c8aea93
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220044575 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_rand_intr_trigger.
2220044575
Directory /workspace/4.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din.1155115591
Short name T206
Test name
Test status
Simulation time 62343968 ps
CPU time 1.14 seconds
Started Jul 29 04:33:41 PM PDT 24
Finished Jul 29 04:33:42 PM PDT 24
Peak memory 197196 kb
Host smart-cfa4109e-012e-4e5f-bf48-bb932c307589
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1155115591 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din.1155115591
Directory /workspace/4.gpio_random_dout_din/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din_no_pullup_pulldown.2146799116
Short name T288
Test name
Test status
Simulation time 276094940 ps
CPU time 0.86 seconds
Started Jul 29 04:33:48 PM PDT 24
Finished Jul 29 04:33:49 PM PDT 24
Peak memory 197040 kb
Host smart-de7ea2ac-b447-4e93-9ff4-0d11bbc3f7bb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146799116 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din_no_pullup
_pulldown.2146799116
Directory /workspace/4.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_random_long_reg_writes_reg_reads.2462393345
Short name T454
Test name
Test status
Simulation time 110108690 ps
CPU time 1.17 seconds
Started Jul 29 04:33:46 PM PDT 24
Finished Jul 29 04:33:47 PM PDT 24
Peak memory 198092 kb
Host smart-07f99b14-5cac-47a2-8c6d-eee88de9572c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462393345 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_ran
dom_long_reg_writes_reg_reads.2462393345
Directory /workspace/4.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/4.gpio_sec_cm.152212949
Short name T42
Test name
Test status
Simulation time 49140386 ps
CPU time 0.78 seconds
Started Jul 29 04:33:45 PM PDT 24
Finished Jul 29 04:33:46 PM PDT 24
Peak memory 214228 kb
Host smart-05712950-2690-4736-898b-f568a958af88
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152212949 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_sec_cm.152212949
Directory /workspace/4.gpio_sec_cm/latest

Test location /workspace/coverage/default/4.gpio_smoke.1858251061
Short name T54
Test name
Test status
Simulation time 347526499 ps
CPU time 1.18 seconds
Started Jul 29 04:33:37 PM PDT 24
Finished Jul 29 04:33:39 PM PDT 24
Peak memory 198456 kb
Host smart-34fd187c-e4d6-450b-a584-adbf2b0c636b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1858251061 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke.1858251061
Directory /workspace/4.gpio_smoke/latest

Test location /workspace/coverage/default/4.gpio_smoke_no_pullup_pulldown.2659626336
Short name T625
Test name
Test status
Simulation time 63419776 ps
CPU time 0.78 seconds
Started Jul 29 04:33:33 PM PDT 24
Finished Jul 29 04:33:34 PM PDT 24
Peak memory 195712 kb
Host smart-956d1713-db6c-442a-ad62-e414aa5e3576
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659626336 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown.2659626336
Directory /workspace/4.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_stress_all.2979668359
Short name T308
Test name
Test status
Simulation time 5895486341 ps
CPU time 144.23 seconds
Started Jul 29 04:33:47 PM PDT 24
Finished Jul 29 04:36:11 PM PDT 24
Peak memory 198588 kb
Host smart-6659c264-7ec4-4a69-8751-4f3e9228309b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979668359 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.g
pio_stress_all.2979668359
Directory /workspace/4.gpio_stress_all/latest

Test location /workspace/coverage/default/40.gpio_alert_test.3982634060
Short name T627
Test name
Test status
Simulation time 30855852 ps
CPU time 0.58 seconds
Started Jul 29 04:34:55 PM PDT 24
Finished Jul 29 04:34:56 PM PDT 24
Peak memory 194252 kb
Host smart-7b7ee9b0-f36a-4dae-99c4-aeb46e121780
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982634060 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_alert_test.3982634060
Directory /workspace/40.gpio_alert_test/latest

Test location /workspace/coverage/default/40.gpio_dout_din_regs_random_rw.975284899
Short name T661
Test name
Test status
Simulation time 174842699 ps
CPU time 0.94 seconds
Started Jul 29 04:34:54 PM PDT 24
Finished Jul 29 04:34:55 PM PDT 24
Peak memory 196920 kb
Host smart-f3a50df9-0dbd-4653-b7eb-ecc4448d4699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=975284899 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_dout_din_regs_random_rw.975284899
Directory /workspace/40.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/40.gpio_filter_stress.4220769342
Short name T180
Test name
Test status
Simulation time 2344865902 ps
CPU time 11.98 seconds
Started Jul 29 04:35:01 PM PDT 24
Finished Jul 29 04:35:13 PM PDT 24
Peak memory 197536 kb
Host smart-e66acb94-cc22-4295-83a2-301facdce494
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220769342 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_filter_stre
ss.4220769342
Directory /workspace/40.gpio_filter_stress/latest

Test location /workspace/coverage/default/40.gpio_full_random.3390821024
Short name T465
Test name
Test status
Simulation time 42107411 ps
CPU time 0.63 seconds
Started Jul 29 04:34:58 PM PDT 24
Finished Jul 29 04:34:58 PM PDT 24
Peak memory 194828 kb
Host smart-603ae46d-dc66-46ad-8716-146c019ba865
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390821024 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_full_random.3390821024
Directory /workspace/40.gpio_full_random/latest

Test location /workspace/coverage/default/40.gpio_intr_rand_pgm.1244217700
Short name T617
Test name
Test status
Simulation time 134449918 ps
CPU time 0.8 seconds
Started Jul 29 04:35:00 PM PDT 24
Finished Jul 29 04:35:01 PM PDT 24
Peak memory 195988 kb
Host smart-52f72ee3-141d-4547-ae8e-04e62de21386
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244217700 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_intr_rand_pgm.1244217700
Directory /workspace/40.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/40.gpio_intr_with_filter_rand_intr_event.3741082124
Short name T367
Test name
Test status
Simulation time 182606246 ps
CPU time 1.93 seconds
Started Jul 29 04:34:59 PM PDT 24
Finished Jul 29 04:35:01 PM PDT 24
Peak memory 198508 kb
Host smart-fe5b9078-ca87-4acb-bf90-e3db19fd7389
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741082124 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 40.gpio_intr_with_filter_rand_intr_event.3741082124
Directory /workspace/40.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/40.gpio_rand_intr_trigger.1085161661
Short name T425
Test name
Test status
Simulation time 100776428 ps
CPU time 1.04 seconds
Started Jul 29 04:35:06 PM PDT 24
Finished Jul 29 04:35:07 PM PDT 24
Peak memory 195984 kb
Host smart-e0d5ef2d-b973-4fef-bb03-c8d9b237ff2f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085161661 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_rand_intr_trigger
.1085161661
Directory /workspace/40.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din.781635025
Short name T15
Test name
Test status
Simulation time 174898094 ps
CPU time 1.33 seconds
Started Jul 29 04:34:55 PM PDT 24
Finished Jul 29 04:34:56 PM PDT 24
Peak memory 197404 kb
Host smart-46be420c-2679-4943-9e0d-678843da6288
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=781635025 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din.781635025
Directory /workspace/40.gpio_random_dout_din/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din_no_pullup_pulldown.3022080970
Short name T523
Test name
Test status
Simulation time 25567924 ps
CPU time 0.75 seconds
Started Jul 29 04:35:01 PM PDT 24
Finished Jul 29 04:35:02 PM PDT 24
Peak memory 195916 kb
Host smart-99d6638e-a9a4-4061-a1bc-9fff0c26f666
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022080970 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din_no_pullu
p_pulldown.3022080970
Directory /workspace/40.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_random_long_reg_writes_reg_reads.2747735876
Short name T295
Test name
Test status
Simulation time 1405302401 ps
CPU time 5.46 seconds
Started Jul 29 04:34:57 PM PDT 24
Finished Jul 29 04:35:02 PM PDT 24
Peak memory 198396 kb
Host smart-76001ee1-f7b4-423a-a183-7a0cbda8e3bd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747735876 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_ra
ndom_long_reg_writes_reg_reads.2747735876
Directory /workspace/40.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/40.gpio_smoke.3452254666
Short name T274
Test name
Test status
Simulation time 57716461 ps
CPU time 1.02 seconds
Started Jul 29 04:34:53 PM PDT 24
Finished Jul 29 04:34:54 PM PDT 24
Peak memory 196652 kb
Host smart-b53d21a3-60a4-4075-8e2e-629b17c320b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3452254666 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke.3452254666
Directory /workspace/40.gpio_smoke/latest

Test location /workspace/coverage/default/40.gpio_smoke_no_pullup_pulldown.1448533952
Short name T278
Test name
Test status
Simulation time 111601009 ps
CPU time 0.94 seconds
Started Jul 29 04:34:52 PM PDT 24
Finished Jul 29 04:34:53 PM PDT 24
Peak memory 196696 kb
Host smart-c2d76ba3-c939-473f-a23d-ab4784ec98f9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448533952 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown.1448533952
Directory /workspace/40.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_stress_all.3923182407
Short name T29
Test name
Test status
Simulation time 2214632209 ps
CPU time 29.39 seconds
Started Jul 29 04:34:57 PM PDT 24
Finished Jul 29 04:35:27 PM PDT 24
Peak memory 198536 kb
Host smart-ed601b7b-2b43-4218-9d55-519d1f04b611
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923182407 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.
gpio_stress_all.3923182407
Directory /workspace/40.gpio_stress_all/latest

Test location /workspace/coverage/default/41.gpio_alert_test.4002132313
Short name T16
Test name
Test status
Simulation time 12405013 ps
CPU time 0.57 seconds
Started Jul 29 04:34:58 PM PDT 24
Finished Jul 29 04:34:58 PM PDT 24
Peak memory 194308 kb
Host smart-f902d459-5e02-4ee4-8b07-f7fe0daa4a68
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002132313 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_alert_test.4002132313
Directory /workspace/41.gpio_alert_test/latest

Test location /workspace/coverage/default/41.gpio_dout_din_regs_random_rw.2505866204
Short name T235
Test name
Test status
Simulation time 88793557 ps
CPU time 0.62 seconds
Started Jul 29 04:35:03 PM PDT 24
Finished Jul 29 04:35:04 PM PDT 24
Peak memory 194288 kb
Host smart-78cfab12-3013-4297-8eae-fe7f99aa1a5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505866204 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_dout_din_regs_random_rw.2505866204
Directory /workspace/41.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/41.gpio_filter_stress.2211348399
Short name T202
Test name
Test status
Simulation time 9156650731 ps
CPU time 14.9 seconds
Started Jul 29 04:34:59 PM PDT 24
Finished Jul 29 04:35:14 PM PDT 24
Peak memory 198600 kb
Host smart-15671bbb-a766-473a-b3f7-a5770dc58dad
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211348399 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_filter_stre
ss.2211348399
Directory /workspace/41.gpio_filter_stress/latest

Test location /workspace/coverage/default/41.gpio_full_random.3565049503
Short name T585
Test name
Test status
Simulation time 144841829 ps
CPU time 0.98 seconds
Started Jul 29 04:34:47 PM PDT 24
Finished Jul 29 04:34:48 PM PDT 24
Peak memory 196704 kb
Host smart-bee0025c-8062-4670-91ac-9535b63f04d3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565049503 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_full_random.3565049503
Directory /workspace/41.gpio_full_random/latest

Test location /workspace/coverage/default/41.gpio_intr_rand_pgm.2535967387
Short name T340
Test name
Test status
Simulation time 73435548 ps
CPU time 1.2 seconds
Started Jul 29 04:35:01 PM PDT 24
Finished Jul 29 04:35:03 PM PDT 24
Peak memory 196532 kb
Host smart-a05001aa-a641-4507-b82f-d2c179828f94
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535967387 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_intr_rand_pgm.2535967387
Directory /workspace/41.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/41.gpio_intr_with_filter_rand_intr_event.3149191944
Short name T301
Test name
Test status
Simulation time 381981033 ps
CPU time 3.57 seconds
Started Jul 29 04:35:14 PM PDT 24
Finished Jul 29 04:35:17 PM PDT 24
Peak memory 198568 kb
Host smart-1470f916-2260-4200-b9e1-3212102837c1
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149191944 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 41.gpio_intr_with_filter_rand_intr_event.3149191944
Directory /workspace/41.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/41.gpio_rand_intr_trigger.3995557258
Short name T436
Test name
Test status
Simulation time 54807303 ps
CPU time 0.86 seconds
Started Jul 29 04:35:02 PM PDT 24
Finished Jul 29 04:35:03 PM PDT 24
Peak memory 194932 kb
Host smart-97bc5a3a-e9e4-45b2-887a-52e56f7f5af6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995557258 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_rand_intr_trigger
.3995557258
Directory /workspace/41.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din.346569364
Short name T571
Test name
Test status
Simulation time 38074845 ps
CPU time 1.18 seconds
Started Jul 29 04:34:57 PM PDT 24
Finished Jul 29 04:34:59 PM PDT 24
Peak memory 196948 kb
Host smart-7c95e03a-81ce-4c35-baf5-083aceedf99c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=346569364 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din.346569364
Directory /workspace/41.gpio_random_dout_din/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din_no_pullup_pulldown.2277701108
Short name T406
Test name
Test status
Simulation time 59884924 ps
CPU time 1.33 seconds
Started Jul 29 04:34:51 PM PDT 24
Finished Jul 29 04:34:53 PM PDT 24
Peak memory 197440 kb
Host smart-c167f627-67a8-42d4-a5b2-a3cd8b20090e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277701108 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din_no_pullu
p_pulldown.2277701108
Directory /workspace/41.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_random_long_reg_writes_reg_reads.1650629773
Short name T550
Test name
Test status
Simulation time 640594912 ps
CPU time 4.95 seconds
Started Jul 29 04:35:14 PM PDT 24
Finished Jul 29 04:35:19 PM PDT 24
Peak memory 198368 kb
Host smart-8106e2ed-7c4e-49c5-8485-c74106075c76
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650629773 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_ra
ndom_long_reg_writes_reg_reads.1650629773
Directory /workspace/41.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/41.gpio_smoke.2567135200
Short name T184
Test name
Test status
Simulation time 202222211 ps
CPU time 1.03 seconds
Started Jul 29 04:34:59 PM PDT 24
Finished Jul 29 04:35:00 PM PDT 24
Peak memory 196856 kb
Host smart-3e3001d2-37db-41d6-a1bf-12401785cef9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567135200 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke.2567135200
Directory /workspace/41.gpio_smoke/latest

Test location /workspace/coverage/default/41.gpio_smoke_no_pullup_pulldown.3970368017
Short name T183
Test name
Test status
Simulation time 498924733 ps
CPU time 0.91 seconds
Started Jul 29 04:34:58 PM PDT 24
Finished Jul 29 04:34:59 PM PDT 24
Peak memory 196828 kb
Host smart-bad6ebe0-e56e-4fc9-816d-a13afb0aae07
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970368017 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown.3970368017
Directory /workspace/41.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_stress_all.3853860535
Short name T326
Test name
Test status
Simulation time 41651528731 ps
CPU time 161.06 seconds
Started Jul 29 04:34:59 PM PDT 24
Finished Jul 29 04:37:40 PM PDT 24
Peak memory 198564 kb
Host smart-3786c382-830f-472b-9b22-761a07b5f1f1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853860535 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.
gpio_stress_all.3853860535
Directory /workspace/41.gpio_stress_all/latest

Test location /workspace/coverage/default/41.gpio_stress_all_with_rand_reset.406655405
Short name T505
Test name
Test status
Simulation time 107650313178 ps
CPU time 840.06 seconds
Started Jul 29 04:35:03 PM PDT 24
Finished Jul 29 04:49:03 PM PDT 24
Peak memory 198708 kb
Host smart-78c591fc-feb6-49f9-ac9d-a8feca47144b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=406655405 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_stress_all_with_rand_reset.406655405
Directory /workspace/41.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.gpio_alert_test.2029249654
Short name T591
Test name
Test status
Simulation time 12484047 ps
CPU time 0.53 seconds
Started Jul 29 04:35:08 PM PDT 24
Finished Jul 29 04:35:09 PM PDT 24
Peak memory 193116 kb
Host smart-2a9f31a4-4e54-4e2f-b311-3c7886ed65a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029249654 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_alert_test.2029249654
Directory /workspace/42.gpio_alert_test/latest

Test location /workspace/coverage/default/42.gpio_dout_din_regs_random_rw.329657756
Short name T176
Test name
Test status
Simulation time 55571552 ps
CPU time 0.67 seconds
Started Jul 29 04:34:57 PM PDT 24
Finished Jul 29 04:34:58 PM PDT 24
Peak memory 195156 kb
Host smart-f3bf2dbc-4596-4c33-a1de-21acdd5209ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=329657756 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_dout_din_regs_random_rw.329657756
Directory /workspace/42.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/42.gpio_filter_stress.3765360421
Short name T167
Test name
Test status
Simulation time 220397705 ps
CPU time 9.13 seconds
Started Jul 29 04:34:54 PM PDT 24
Finished Jul 29 04:35:08 PM PDT 24
Peak memory 195900 kb
Host smart-d8949a7e-1e3f-455e-8c1a-4aa666d14b38
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765360421 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_filter_stre
ss.3765360421
Directory /workspace/42.gpio_filter_stress/latest

Test location /workspace/coverage/default/42.gpio_full_random.1955251761
Short name T244
Test name
Test status
Simulation time 267737625 ps
CPU time 1.05 seconds
Started Jul 29 04:35:01 PM PDT 24
Finished Jul 29 04:35:02 PM PDT 24
Peak memory 196840 kb
Host smart-cf0cbeeb-235b-49f3-a2a1-292499a0f7d8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955251761 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_full_random.1955251761
Directory /workspace/42.gpio_full_random/latest

Test location /workspace/coverage/default/42.gpio_intr_rand_pgm.2691832122
Short name T161
Test name
Test status
Simulation time 168656483 ps
CPU time 1.22 seconds
Started Jul 29 04:35:05 PM PDT 24
Finished Jul 29 04:35:07 PM PDT 24
Peak memory 196576 kb
Host smart-0b7159dd-2469-4893-a925-89f7ae5d8b7c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691832122 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_intr_rand_pgm.2691832122
Directory /workspace/42.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/42.gpio_intr_with_filter_rand_intr_event.2716107351
Short name T480
Test name
Test status
Simulation time 162935034 ps
CPU time 3.07 seconds
Started Jul 29 04:35:01 PM PDT 24
Finished Jul 29 04:35:04 PM PDT 24
Peak memory 196724 kb
Host smart-172c211d-46ff-4805-af9f-d122c053dfc6
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716107351 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 42.gpio_intr_with_filter_rand_intr_event.2716107351
Directory /workspace/42.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/42.gpio_rand_intr_trigger.2144632435
Short name T470
Test name
Test status
Simulation time 331110386 ps
CPU time 1.81 seconds
Started Jul 29 04:34:57 PM PDT 24
Finished Jul 29 04:34:59 PM PDT 24
Peak memory 196460 kb
Host smart-5d094554-64ca-4d7e-bb5c-5875fba9e3cf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144632435 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_rand_intr_trigger
.2144632435
Directory /workspace/42.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din.2261258257
Short name T281
Test name
Test status
Simulation time 133471350 ps
CPU time 1.24 seconds
Started Jul 29 04:34:59 PM PDT 24
Finished Jul 29 04:35:00 PM PDT 24
Peak memory 197244 kb
Host smart-f0eac5d9-48d1-4c16-85a5-154a38497fec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2261258257 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din.2261258257
Directory /workspace/42.gpio_random_dout_din/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din_no_pullup_pulldown.2765230608
Short name T546
Test name
Test status
Simulation time 56033845 ps
CPU time 0.82 seconds
Started Jul 29 04:34:53 PM PDT 24
Finished Jul 29 04:34:54 PM PDT 24
Peak memory 195900 kb
Host smart-80ee301b-2786-4261-a013-778f358ecf54
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765230608 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din_no_pullu
p_pulldown.2765230608
Directory /workspace/42.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_random_long_reg_writes_reg_reads.2840392006
Short name T115
Test name
Test status
Simulation time 121090011 ps
CPU time 5.64 seconds
Started Jul 29 04:35:04 PM PDT 24
Finished Jul 29 04:35:10 PM PDT 24
Peak memory 198328 kb
Host smart-92eeef0e-6644-40aa-beab-d59bbf1da387
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840392006 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_ra
ndom_long_reg_writes_reg_reads.2840392006
Directory /workspace/42.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/42.gpio_smoke.2924878743
Short name T268
Test name
Test status
Simulation time 144262094 ps
CPU time 1.22 seconds
Started Jul 29 04:35:02 PM PDT 24
Finished Jul 29 04:35:03 PM PDT 24
Peak memory 198384 kb
Host smart-e0e51092-5dc0-42fe-b19f-e486ac498d49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2924878743 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke.2924878743
Directory /workspace/42.gpio_smoke/latest

Test location /workspace/coverage/default/42.gpio_smoke_no_pullup_pulldown.3140548798
Short name T566
Test name
Test status
Simulation time 88876451 ps
CPU time 1.2 seconds
Started Jul 29 04:35:02 PM PDT 24
Finished Jul 29 04:35:03 PM PDT 24
Peak memory 196160 kb
Host smart-7b1b809f-ac57-49cd-bcde-f2277cfec9a0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140548798 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown.3140548798
Directory /workspace/42.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_stress_all.2061904774
Short name T522
Test name
Test status
Simulation time 6732151214 ps
CPU time 91.36 seconds
Started Jul 29 04:35:03 PM PDT 24
Finished Jul 29 04:36:34 PM PDT 24
Peak memory 198592 kb
Host smart-91ece946-12da-407f-baca-496f834a373c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061904774 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.
gpio_stress_all.2061904774
Directory /workspace/42.gpio_stress_all/latest

Test location /workspace/coverage/default/42.gpio_stress_all_with_rand_reset.2338305587
Short name T60
Test name
Test status
Simulation time 39945720134 ps
CPU time 820.56 seconds
Started Jul 29 04:35:08 PM PDT 24
Finished Jul 29 04:48:49 PM PDT 24
Peak memory 198692 kb
Host smart-34fae358-3d3c-4992-910d-233463d4e17e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2338305587 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_stress_all_with_rand_reset.2338305587
Directory /workspace/42.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.gpio_alert_test.999452449
Short name T516
Test name
Test status
Simulation time 36745223 ps
CPU time 0.57 seconds
Started Jul 29 04:35:03 PM PDT 24
Finished Jul 29 04:35:03 PM PDT 24
Peak memory 195016 kb
Host smart-a3a0a6a7-501d-4b5e-b6ea-9c067c5c9948
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999452449 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_alert_test.999452449
Directory /workspace/43.gpio_alert_test/latest

Test location /workspace/coverage/default/43.gpio_dout_din_regs_random_rw.3897985962
Short name T218
Test name
Test status
Simulation time 370211078 ps
CPU time 0.73 seconds
Started Jul 29 04:35:04 PM PDT 24
Finished Jul 29 04:35:05 PM PDT 24
Peak memory 195652 kb
Host smart-d30b9353-242a-4d19-9df3-349865d04b2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3897985962 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_dout_din_regs_random_rw.3897985962
Directory /workspace/43.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/43.gpio_filter_stress.1317382722
Short name T174
Test name
Test status
Simulation time 753322787 ps
CPU time 6.39 seconds
Started Jul 29 04:34:55 PM PDT 24
Finished Jul 29 04:35:01 PM PDT 24
Peak memory 197100 kb
Host smart-3abfb8a1-31ac-4247-91e4-047ababa2e27
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317382722 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_filter_stre
ss.1317382722
Directory /workspace/43.gpio_filter_stress/latest

Test location /workspace/coverage/default/43.gpio_full_random.3700468862
Short name T110
Test name
Test status
Simulation time 190013907 ps
CPU time 0.9 seconds
Started Jul 29 04:34:58 PM PDT 24
Finished Jul 29 04:34:59 PM PDT 24
Peak memory 198292 kb
Host smart-11314a81-8fbb-4f08-845b-0a4589807a56
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700468862 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_full_random.3700468862
Directory /workspace/43.gpio_full_random/latest

Test location /workspace/coverage/default/43.gpio_intr_rand_pgm.4018024303
Short name T639
Test name
Test status
Simulation time 121954965 ps
CPU time 0.89 seconds
Started Jul 29 04:35:18 PM PDT 24
Finished Jul 29 04:35:19 PM PDT 24
Peak memory 197008 kb
Host smart-ec4c3be0-ffb4-4ecf-af61-b1640d889f58
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018024303 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_intr_rand_pgm.4018024303
Directory /workspace/43.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/43.gpio_intr_with_filter_rand_intr_event.1997089939
Short name T362
Test name
Test status
Simulation time 41582697 ps
CPU time 1.28 seconds
Started Jul 29 04:35:03 PM PDT 24
Finished Jul 29 04:35:04 PM PDT 24
Peak memory 197112 kb
Host smart-7dc878aa-9608-4298-ab1a-3f59e3227e5f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997089939 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 43.gpio_intr_with_filter_rand_intr_event.1997089939
Directory /workspace/43.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/43.gpio_rand_intr_trigger.1192392047
Short name T616
Test name
Test status
Simulation time 109459783 ps
CPU time 2.42 seconds
Started Jul 29 04:35:03 PM PDT 24
Finished Jul 29 04:35:05 PM PDT 24
Peak memory 198444 kb
Host smart-a44f0b3f-4cf6-4ed3-9c6c-40d5dc5a7826
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192392047 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_rand_intr_trigger
.1192392047
Directory /workspace/43.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din.3935645536
Short name T245
Test name
Test status
Simulation time 60097164 ps
CPU time 1.27 seconds
Started Jul 29 04:35:08 PM PDT 24
Finished Jul 29 04:35:09 PM PDT 24
Peak memory 196860 kb
Host smart-c542346d-7b46-40a3-a20e-97ef3d7e8e8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3935645536 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din.3935645536
Directory /workspace/43.gpio_random_dout_din/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din_no_pullup_pulldown.1789355817
Short name T506
Test name
Test status
Simulation time 147663754 ps
CPU time 1.42 seconds
Started Jul 29 04:35:06 PM PDT 24
Finished Jul 29 04:35:07 PM PDT 24
Peak memory 197352 kb
Host smart-20334a85-136a-498c-a156-0a3ad0dde1ae
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789355817 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din_no_pullu
p_pulldown.1789355817
Directory /workspace/43.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_random_long_reg_writes_reg_reads.605988683
Short name T3
Test name
Test status
Simulation time 103619121 ps
CPU time 1.67 seconds
Started Jul 29 04:35:01 PM PDT 24
Finished Jul 29 04:35:03 PM PDT 24
Peak memory 198192 kb
Host smart-f0ef2e1c-fc4d-4ca0-ae50-2603e39f3d0c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605988683 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_ran
dom_long_reg_writes_reg_reads.605988683
Directory /workspace/43.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/43.gpio_smoke.222529308
Short name T247
Test name
Test status
Simulation time 99937515 ps
CPU time 1.28 seconds
Started Jul 29 04:35:03 PM PDT 24
Finished Jul 29 04:35:04 PM PDT 24
Peak memory 196672 kb
Host smart-ac4f86f2-b302-4854-86b5-dad5720455c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=222529308 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke.222529308
Directory /workspace/43.gpio_smoke/latest

Test location /workspace/coverage/default/43.gpio_smoke_no_pullup_pulldown.2606949213
Short name T225
Test name
Test status
Simulation time 116245240 ps
CPU time 1.24 seconds
Started Jul 29 04:35:02 PM PDT 24
Finished Jul 29 04:35:03 PM PDT 24
Peak memory 197320 kb
Host smart-59e12621-b02f-41fc-9077-c36551d425d4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606949213 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown.2606949213
Directory /workspace/43.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_stress_all.4179961213
Short name T134
Test name
Test status
Simulation time 7561546749 ps
CPU time 183.77 seconds
Started Jul 29 04:35:06 PM PDT 24
Finished Jul 29 04:38:10 PM PDT 24
Peak memory 198700 kb
Host smart-cadd049e-58ee-4e0d-9a40-5d4a8f041c57
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179961213 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.
gpio_stress_all.4179961213
Directory /workspace/43.gpio_stress_all/latest

Test location /workspace/coverage/default/44.gpio_alert_test.789759403
Short name T370
Test name
Test status
Simulation time 22532850 ps
CPU time 0.63 seconds
Started Jul 29 04:35:13 PM PDT 24
Finished Jul 29 04:35:14 PM PDT 24
Peak memory 195240 kb
Host smart-aa5e521e-1593-417d-8cc4-e67692ad52cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789759403 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_alert_test.789759403
Directory /workspace/44.gpio_alert_test/latest

Test location /workspace/coverage/default/44.gpio_dout_din_regs_random_rw.2875483278
Short name T652
Test name
Test status
Simulation time 74687260 ps
CPU time 0.75 seconds
Started Jul 29 04:35:04 PM PDT 24
Finished Jul 29 04:35:05 PM PDT 24
Peak memory 194564 kb
Host smart-a0d35630-dcc0-40b5-9afe-fb2747aca8cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2875483278 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_dout_din_regs_random_rw.2875483278
Directory /workspace/44.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/44.gpio_filter_stress.2040093671
Short name T605
Test name
Test status
Simulation time 1859968994 ps
CPU time 24.09 seconds
Started Jul 29 04:35:04 PM PDT 24
Finished Jul 29 04:35:29 PM PDT 24
Peak memory 197428 kb
Host smart-edfd13df-113d-40ba-9a8a-707b46df97e3
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040093671 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_filter_stre
ss.2040093671
Directory /workspace/44.gpio_filter_stress/latest

Test location /workspace/coverage/default/44.gpio_full_random.821236256
Short name T6
Test name
Test status
Simulation time 27032490 ps
CPU time 0.67 seconds
Started Jul 29 04:35:04 PM PDT 24
Finished Jul 29 04:35:05 PM PDT 24
Peak memory 195128 kb
Host smart-121b8842-1809-460d-9dde-ca5d81422c1a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821236256 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_full_random.821236256
Directory /workspace/44.gpio_full_random/latest

Test location /workspace/coverage/default/44.gpio_intr_rand_pgm.1741322448
Short name T587
Test name
Test status
Simulation time 167544401 ps
CPU time 1.09 seconds
Started Jul 29 04:35:02 PM PDT 24
Finished Jul 29 04:35:04 PM PDT 24
Peak memory 196140 kb
Host smart-cdcc2092-2f9c-49ac-b5a4-903b088b334f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741322448 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_intr_rand_pgm.1741322448
Directory /workspace/44.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/44.gpio_intr_with_filter_rand_intr_event.346230516
Short name T681
Test name
Test status
Simulation time 120741640 ps
CPU time 2.38 seconds
Started Jul 29 04:35:03 PM PDT 24
Finished Jul 29 04:35:06 PM PDT 24
Peak memory 198432 kb
Host smart-f1d57c62-c5f8-4e5f-b630-de04569eb691
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346230516 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 44.gpio_intr_with_filter_rand_intr_event.346230516
Directory /workspace/44.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/44.gpio_rand_intr_trigger.4083151419
Short name T368
Test name
Test status
Simulation time 38832200 ps
CPU time 1.27 seconds
Started Jul 29 04:35:10 PM PDT 24
Finished Jul 29 04:35:12 PM PDT 24
Peak memory 197824 kb
Host smart-835b11cb-70ef-4796-9969-a45317a6c540
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083151419 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_rand_intr_trigger
.4083151419
Directory /workspace/44.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din.875582279
Short name T586
Test name
Test status
Simulation time 174038332 ps
CPU time 0.89 seconds
Started Jul 29 04:34:58 PM PDT 24
Finished Jul 29 04:34:59 PM PDT 24
Peak memory 196160 kb
Host smart-7da0b0ea-109c-4a34-a806-50203305dfb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=875582279 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din.875582279
Directory /workspace/44.gpio_random_dout_din/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din_no_pullup_pulldown.3935975787
Short name T511
Test name
Test status
Simulation time 244960310 ps
CPU time 1.21 seconds
Started Jul 29 04:35:21 PM PDT 24
Finished Jul 29 04:35:22 PM PDT 24
Peak memory 196932 kb
Host smart-abffe10e-66dc-4faa-973e-ffbd9935d508
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935975787 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din_no_pullu
p_pulldown.3935975787
Directory /workspace/44.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_random_long_reg_writes_reg_reads.2418645092
Short name T717
Test name
Test status
Simulation time 349583151 ps
CPU time 5.57 seconds
Started Jul 29 04:35:02 PM PDT 24
Finished Jul 29 04:35:08 PM PDT 24
Peak memory 198412 kb
Host smart-997178cd-4f17-4049-868c-bc651f5966a1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418645092 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_ra
ndom_long_reg_writes_reg_reads.2418645092
Directory /workspace/44.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/44.gpio_smoke.542689049
Short name T129
Test name
Test status
Simulation time 166084444 ps
CPU time 1.03 seconds
Started Jul 29 04:34:58 PM PDT 24
Finished Jul 29 04:35:00 PM PDT 24
Peak memory 196092 kb
Host smart-79222c55-af94-4b24-9505-4aa8a74532e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=542689049 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke.542689049
Directory /workspace/44.gpio_smoke/latest

Test location /workspace/coverage/default/44.gpio_smoke_no_pullup_pulldown.132869903
Short name T389
Test name
Test status
Simulation time 517644252 ps
CPU time 1.04 seconds
Started Jul 29 04:35:00 PM PDT 24
Finished Jul 29 04:35:01 PM PDT 24
Peak memory 196936 kb
Host smart-881d4d57-e6d7-4e43-84b6-e22ee7076962
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132869903 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown.132869903
Directory /workspace/44.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_stress_all.3412791845
Short name T10
Test name
Test status
Simulation time 58468909303 ps
CPU time 166.85 seconds
Started Jul 29 04:35:09 PM PDT 24
Finished Jul 29 04:37:56 PM PDT 24
Peak memory 198540 kb
Host smart-8942225d-387b-444c-b589-95a3902b5026
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412791845 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.
gpio_stress_all.3412791845
Directory /workspace/44.gpio_stress_all/latest

Test location /workspace/coverage/default/45.gpio_alert_test.1692748444
Short name T510
Test name
Test status
Simulation time 12037643 ps
CPU time 0.59 seconds
Started Jul 29 04:35:03 PM PDT 24
Finished Jul 29 04:35:04 PM PDT 24
Peak memory 194292 kb
Host smart-87753a18-d689-476a-89eb-08c55a95a4ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692748444 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_alert_test.1692748444
Directory /workspace/45.gpio_alert_test/latest

Test location /workspace/coverage/default/45.gpio_dout_din_regs_random_rw.3205144148
Short name T458
Test name
Test status
Simulation time 70870327 ps
CPU time 0.84 seconds
Started Jul 29 04:35:02 PM PDT 24
Finished Jul 29 04:35:03 PM PDT 24
Peak memory 195660 kb
Host smart-fb24cdb9-a0a4-4c59-b235-6de188933d3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3205144148 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_dout_din_regs_random_rw.3205144148
Directory /workspace/45.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/45.gpio_filter_stress.3650982890
Short name T415
Test name
Test status
Simulation time 455690545 ps
CPU time 6.06 seconds
Started Jul 29 04:35:03 PM PDT 24
Finished Jul 29 04:35:10 PM PDT 24
Peak memory 197352 kb
Host smart-02747bba-8b70-425b-b86e-22728f3ed791
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650982890 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_filter_stre
ss.3650982890
Directory /workspace/45.gpio_filter_stress/latest

Test location /workspace/coverage/default/45.gpio_full_random.1246385267
Short name T386
Test name
Test status
Simulation time 151001620 ps
CPU time 0.74 seconds
Started Jul 29 04:35:02 PM PDT 24
Finished Jul 29 04:35:03 PM PDT 24
Peak memory 195160 kb
Host smart-5936ccc2-8d83-4d75-bf01-a1aa83a5459e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246385267 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_full_random.1246385267
Directory /workspace/45.gpio_full_random/latest

Test location /workspace/coverage/default/45.gpio_intr_rand_pgm.3820049019
Short name T135
Test name
Test status
Simulation time 42651143 ps
CPU time 1.16 seconds
Started Jul 29 04:35:04 PM PDT 24
Finished Jul 29 04:35:05 PM PDT 24
Peak memory 197332 kb
Host smart-98d6c7a2-ef0c-4b2c-be02-3b201a2b49ba
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820049019 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_intr_rand_pgm.3820049019
Directory /workspace/45.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/45.gpio_intr_with_filter_rand_intr_event.1764264564
Short name T310
Test name
Test status
Simulation time 105093626 ps
CPU time 1.22 seconds
Started Jul 29 04:35:25 PM PDT 24
Finished Jul 29 04:35:26 PM PDT 24
Peak memory 196844 kb
Host smart-5378576e-3c9c-474e-b37c-34c140fc00f0
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764264564 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 45.gpio_intr_with_filter_rand_intr_event.1764264564
Directory /workspace/45.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/45.gpio_rand_intr_trigger.1003003758
Short name T483
Test name
Test status
Simulation time 385735953 ps
CPU time 3.3 seconds
Started Jul 29 04:35:12 PM PDT 24
Finished Jul 29 04:35:15 PM PDT 24
Peak memory 197532 kb
Host smart-6d7b8bbe-31db-45b9-bf2e-6c56bb30ef5f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003003758 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_rand_intr_trigger
.1003003758
Directory /workspace/45.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din.2167227601
Short name T619
Test name
Test status
Simulation time 222915569 ps
CPU time 1.21 seconds
Started Jul 29 04:35:09 PM PDT 24
Finished Jul 29 04:35:10 PM PDT 24
Peak memory 197308 kb
Host smart-e139a2af-27be-4d0a-8d26-0115c1575a6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2167227601 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din.2167227601
Directory /workspace/45.gpio_random_dout_din/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din_no_pullup_pulldown.4178132067
Short name T117
Test name
Test status
Simulation time 119754113 ps
CPU time 0.91 seconds
Started Jul 29 04:35:12 PM PDT 24
Finished Jul 29 04:35:13 PM PDT 24
Peak memory 196564 kb
Host smart-9a8c04bf-cc8f-4808-951a-fe38c7248cbd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178132067 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din_no_pullu
p_pulldown.4178132067
Directory /workspace/45.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_random_long_reg_writes_reg_reads.3254665951
Short name T22
Test name
Test status
Simulation time 616883681 ps
CPU time 2.29 seconds
Started Jul 29 04:35:18 PM PDT 24
Finished Jul 29 04:35:20 PM PDT 24
Peak memory 198396 kb
Host smart-20aa4768-c8eb-43e6-aabd-a9df815114bb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254665951 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_ra
ndom_long_reg_writes_reg_reads.3254665951
Directory /workspace/45.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/45.gpio_smoke.2451859597
Short name T521
Test name
Test status
Simulation time 1420789362 ps
CPU time 1.37 seconds
Started Jul 29 04:35:15 PM PDT 24
Finished Jul 29 04:35:17 PM PDT 24
Peak memory 197204 kb
Host smart-73ba290a-0618-4ae2-be40-dc31bfe633a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2451859597 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke.2451859597
Directory /workspace/45.gpio_smoke/latest

Test location /workspace/coverage/default/45.gpio_smoke_no_pullup_pulldown.418439530
Short name T481
Test name
Test status
Simulation time 35726922 ps
CPU time 0.93 seconds
Started Jul 29 04:35:01 PM PDT 24
Finished Jul 29 04:35:02 PM PDT 24
Peak memory 196780 kb
Host smart-88affb46-2f4c-4ef4-a8d0-def123952eef
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418439530 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown.418439530
Directory /workspace/45.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_stress_all.1970245990
Short name T303
Test name
Test status
Simulation time 22607285283 ps
CPU time 146.7 seconds
Started Jul 29 04:35:00 PM PDT 24
Finished Jul 29 04:37:27 PM PDT 24
Peak memory 198532 kb
Host smart-0710f1ea-f6a3-45e0-8b95-99add5dfb73b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970245990 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.
gpio_stress_all.1970245990
Directory /workspace/45.gpio_stress_all/latest

Test location /workspace/coverage/default/46.gpio_alert_test.2999832341
Short name T554
Test name
Test status
Simulation time 13580440 ps
CPU time 0.56 seconds
Started Jul 29 04:35:11 PM PDT 24
Finished Jul 29 04:35:12 PM PDT 24
Peak memory 194292 kb
Host smart-b77a4929-6b24-4aab-bbb4-b3bad7b704d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999832341 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_alert_test.2999832341
Directory /workspace/46.gpio_alert_test/latest

Test location /workspace/coverage/default/46.gpio_dout_din_regs_random_rw.2353206351
Short name T688
Test name
Test status
Simulation time 103960001 ps
CPU time 0.77 seconds
Started Jul 29 04:35:18 PM PDT 24
Finished Jul 29 04:35:19 PM PDT 24
Peak memory 195660 kb
Host smart-d2f0b98c-7c93-4c85-b582-ae513555ed76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2353206351 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_dout_din_regs_random_rw.2353206351
Directory /workspace/46.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/46.gpio_filter_stress.1517867404
Short name T212
Test name
Test status
Simulation time 235569794 ps
CPU time 11.37 seconds
Started Jul 29 04:34:58 PM PDT 24
Finished Jul 29 04:35:10 PM PDT 24
Peak memory 195936 kb
Host smart-22592897-1554-49f4-9cf0-f71426ba270e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517867404 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_filter_stre
ss.1517867404
Directory /workspace/46.gpio_filter_stress/latest

Test location /workspace/coverage/default/46.gpio_full_random.559372076
Short name T629
Test name
Test status
Simulation time 494211342 ps
CPU time 0.93 seconds
Started Jul 29 04:35:05 PM PDT 24
Finished Jul 29 04:35:06 PM PDT 24
Peak memory 197524 kb
Host smart-e64f2db6-c0d1-4089-8cc4-83d3355707d8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559372076 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_full_random.559372076
Directory /workspace/46.gpio_full_random/latest

Test location /workspace/coverage/default/46.gpio_intr_rand_pgm.2604208179
Short name T149
Test name
Test status
Simulation time 268067122 ps
CPU time 1.2 seconds
Started Jul 29 04:35:12 PM PDT 24
Finished Jul 29 04:35:13 PM PDT 24
Peak memory 196528 kb
Host smart-570cbadb-ce26-4c78-b0c2-ef5898e95b10
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604208179 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_intr_rand_pgm.2604208179
Directory /workspace/46.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/46.gpio_intr_with_filter_rand_intr_event.4056149644
Short name T552
Test name
Test status
Simulation time 117590594 ps
CPU time 2.49 seconds
Started Jul 29 04:35:04 PM PDT 24
Finished Jul 29 04:35:07 PM PDT 24
Peak memory 198388 kb
Host smart-ede3ffd3-500c-4738-b06b-67ecd6d8c6b8
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056149644 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 46.gpio_intr_with_filter_rand_intr_event.4056149644
Directory /workspace/46.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/46.gpio_rand_intr_trigger.1914029691
Short name T12
Test name
Test status
Simulation time 41195466 ps
CPU time 1.41 seconds
Started Jul 29 04:35:05 PM PDT 24
Finished Jul 29 04:35:06 PM PDT 24
Peak memory 196356 kb
Host smart-1db9b53a-3b8c-4e08-b05e-8a5e379534f2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914029691 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_rand_intr_trigger
.1914029691
Directory /workspace/46.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din.3571402820
Short name T469
Test name
Test status
Simulation time 34721047 ps
CPU time 1.08 seconds
Started Jul 29 04:35:04 PM PDT 24
Finished Jul 29 04:35:05 PM PDT 24
Peak memory 197540 kb
Host smart-c61bba93-74c6-4808-bab4-e0452fb1e71c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3571402820 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din.3571402820
Directory /workspace/46.gpio_random_dout_din/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din_no_pullup_pulldown.1320865093
Short name T292
Test name
Test status
Simulation time 58817884 ps
CPU time 1.32 seconds
Started Jul 29 04:35:13 PM PDT 24
Finished Jul 29 04:35:14 PM PDT 24
Peak memory 196204 kb
Host smart-e06e65e4-126f-40b2-ab0d-a45ac2a361b6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320865093 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din_no_pullu
p_pulldown.1320865093
Directory /workspace/46.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_random_long_reg_writes_reg_reads.1603024427
Short name T350
Test name
Test status
Simulation time 705156426 ps
CPU time 3.15 seconds
Started Jul 29 04:35:07 PM PDT 24
Finished Jul 29 04:35:10 PM PDT 24
Peak memory 198416 kb
Host smart-0a8fb6ed-0a73-4e1d-b0a4-06669d536e80
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603024427 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_ra
ndom_long_reg_writes_reg_reads.1603024427
Directory /workspace/46.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/46.gpio_smoke.2125411419
Short name T357
Test name
Test status
Simulation time 55626628 ps
CPU time 1.4 seconds
Started Jul 29 04:35:05 PM PDT 24
Finished Jul 29 04:35:06 PM PDT 24
Peak memory 196060 kb
Host smart-f600096c-afd6-4d6b-ab59-f51e855f22ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2125411419 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke.2125411419
Directory /workspace/46.gpio_smoke/latest

Test location /workspace/coverage/default/46.gpio_smoke_no_pullup_pulldown.2977171744
Short name T360
Test name
Test status
Simulation time 120514445 ps
CPU time 1.12 seconds
Started Jul 29 04:35:17 PM PDT 24
Finished Jul 29 04:35:18 PM PDT 24
Peak memory 196608 kb
Host smart-7c815996-b3f2-47ab-90fd-8887670aadc1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977171744 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown.2977171744
Directory /workspace/46.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_stress_all.1509761973
Short name T352
Test name
Test status
Simulation time 4614207705 ps
CPU time 63.2 seconds
Started Jul 29 04:35:20 PM PDT 24
Finished Jul 29 04:36:23 PM PDT 24
Peak memory 198496 kb
Host smart-5f67f9fa-7177-4d4e-bca3-11fc094aa6ad
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509761973 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.
gpio_stress_all.1509761973
Directory /workspace/46.gpio_stress_all/latest

Test location /workspace/coverage/default/47.gpio_alert_test.2645446029
Short name T440
Test name
Test status
Simulation time 41931776 ps
CPU time 0.56 seconds
Started Jul 29 04:35:14 PM PDT 24
Finished Jul 29 04:35:14 PM PDT 24
Peak memory 195980 kb
Host smart-24ce0711-8541-4414-8ab2-68162b37a03c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645446029 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_alert_test.2645446029
Directory /workspace/47.gpio_alert_test/latest

Test location /workspace/coverage/default/47.gpio_dout_din_regs_random_rw.4005734681
Short name T444
Test name
Test status
Simulation time 68755438 ps
CPU time 0.91 seconds
Started Jul 29 04:35:21 PM PDT 24
Finished Jul 29 04:35:22 PM PDT 24
Peak memory 197156 kb
Host smart-f16fc9f7-592e-4e27-99b5-fbdb54d2616b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4005734681 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_dout_din_regs_random_rw.4005734681
Directory /workspace/47.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/47.gpio_filter_stress.3459730623
Short name T97
Test name
Test status
Simulation time 581260687 ps
CPU time 16.65 seconds
Started Jul 29 04:35:05 PM PDT 24
Finished Jul 29 04:35:22 PM PDT 24
Peak memory 195888 kb
Host smart-a4d3a605-106f-4e97-9786-20433aea2256
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459730623 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_filter_stre
ss.3459730623
Directory /workspace/47.gpio_filter_stress/latest

Test location /workspace/coverage/default/47.gpio_full_random.277947171
Short name T185
Test name
Test status
Simulation time 24243031 ps
CPU time 0.69 seconds
Started Jul 29 04:35:08 PM PDT 24
Finished Jul 29 04:35:09 PM PDT 24
Peak memory 195528 kb
Host smart-ddb61f70-b6f2-4463-a69c-31f6217c44c4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277947171 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_full_random.277947171
Directory /workspace/47.gpio_full_random/latest

Test location /workspace/coverage/default/47.gpio_intr_rand_pgm.332115062
Short name T668
Test name
Test status
Simulation time 154067288 ps
CPU time 1.33 seconds
Started Jul 29 04:35:00 PM PDT 24
Finished Jul 29 04:35:06 PM PDT 24
Peak memory 196928 kb
Host smart-30a450e6-7be5-42cc-bb55-f2b116edc5b9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332115062 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_intr_rand_pgm.332115062
Directory /workspace/47.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/47.gpio_intr_with_filter_rand_intr_event.2566056462
Short name T166
Test name
Test status
Simulation time 103131193 ps
CPU time 2.05 seconds
Started Jul 29 04:35:07 PM PDT 24
Finished Jul 29 04:35:09 PM PDT 24
Peak memory 198336 kb
Host smart-47d80d44-a9c7-4cb4-8c62-f0f03cea09ff
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566056462 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 47.gpio_intr_with_filter_rand_intr_event.2566056462
Directory /workspace/47.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/47.gpio_rand_intr_trigger.1361218116
Short name T128
Test name
Test status
Simulation time 89572800 ps
CPU time 1.97 seconds
Started Jul 29 04:35:07 PM PDT 24
Finished Jul 29 04:35:09 PM PDT 24
Peak memory 196536 kb
Host smart-26222a66-92ed-4ab1-87b9-0c1876c86dd5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361218116 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_rand_intr_trigger
.1361218116
Directory /workspace/47.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din.134813514
Short name T561
Test name
Test status
Simulation time 116929189 ps
CPU time 1.01 seconds
Started Jul 29 04:35:05 PM PDT 24
Finished Jul 29 04:35:06 PM PDT 24
Peak memory 196320 kb
Host smart-40b48eb2-dfeb-40ff-8e08-130d6d757282
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=134813514 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din.134813514
Directory /workspace/47.gpio_random_dout_din/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din_no_pullup_pulldown.2510783264
Short name T434
Test name
Test status
Simulation time 203085523 ps
CPU time 1.13 seconds
Started Jul 29 04:35:12 PM PDT 24
Finished Jul 29 04:35:13 PM PDT 24
Peak memory 196344 kb
Host smart-e90c5d65-6a3b-40a7-897c-bc09beb6a6aa
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510783264 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din_no_pullu
p_pulldown.2510783264
Directory /workspace/47.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_random_long_reg_writes_reg_reads.759680138
Short name T349
Test name
Test status
Simulation time 459407310 ps
CPU time 5.03 seconds
Started Jul 29 04:35:09 PM PDT 24
Finished Jul 29 04:35:15 PM PDT 24
Peak memory 198324 kb
Host smart-38c94d6b-e697-4111-8020-1a89cf7c37c0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759680138 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_ran
dom_long_reg_writes_reg_reads.759680138
Directory /workspace/47.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/47.gpio_smoke.522487839
Short name T100
Test name
Test status
Simulation time 133837925 ps
CPU time 1.02 seconds
Started Jul 29 04:35:14 PM PDT 24
Finished Jul 29 04:35:15 PM PDT 24
Peak memory 195928 kb
Host smart-8bc106ff-5b46-474a-8518-7b3a98d6c9d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=522487839 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke.522487839
Directory /workspace/47.gpio_smoke/latest

Test location /workspace/coverage/default/47.gpio_smoke_no_pullup_pulldown.2783125467
Short name T487
Test name
Test status
Simulation time 48390308 ps
CPU time 0.74 seconds
Started Jul 29 04:35:04 PM PDT 24
Finished Jul 29 04:35:04 PM PDT 24
Peak memory 196232 kb
Host smart-5763435b-d5ed-4186-9bfc-6e9433dfb0bf
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783125467 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown.2783125467
Directory /workspace/47.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_stress_all.3289764543
Short name T536
Test name
Test status
Simulation time 15981069336 ps
CPU time 188.37 seconds
Started Jul 29 04:35:04 PM PDT 24
Finished Jul 29 04:38:18 PM PDT 24
Peak memory 198584 kb
Host smart-331eb6fe-26e3-411b-b5d2-9842a8c07e16
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289764543 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.
gpio_stress_all.3289764543
Directory /workspace/47.gpio_stress_all/latest

Test location /workspace/coverage/default/47.gpio_stress_all_with_rand_reset.208298091
Short name T696
Test name
Test status
Simulation time 30953918547 ps
CPU time 467.64 seconds
Started Jul 29 04:35:06 PM PDT 24
Finished Jul 29 04:42:54 PM PDT 24
Peak memory 198716 kb
Host smart-c4cecf5b-06eb-4216-a0a3-49bcb03bc56a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=208298091 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_stress_all_with_rand_reset.208298091
Directory /workspace/47.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.gpio_alert_test.991560860
Short name T229
Test name
Test status
Simulation time 12537391 ps
CPU time 0.63 seconds
Started Jul 29 04:35:04 PM PDT 24
Finished Jul 29 04:35:05 PM PDT 24
Peak memory 195164 kb
Host smart-a728e69f-d8fa-4a94-8afb-c196353b274f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991560860 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_alert_test.991560860
Directory /workspace/48.gpio_alert_test/latest

Test location /workspace/coverage/default/48.gpio_dout_din_regs_random_rw.714530590
Short name T651
Test name
Test status
Simulation time 38967844 ps
CPU time 0.67 seconds
Started Jul 29 04:35:06 PM PDT 24
Finished Jul 29 04:35:07 PM PDT 24
Peak memory 195164 kb
Host smart-7b2591e4-b2ac-4cc0-999f-b2584f3cc3c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=714530590 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_dout_din_regs_random_rw.714530590
Directory /workspace/48.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/48.gpio_filter_stress.1610809428
Short name T155
Test name
Test status
Simulation time 165849031 ps
CPU time 4.65 seconds
Started Jul 29 04:35:06 PM PDT 24
Finished Jul 29 04:35:11 PM PDT 24
Peak memory 195912 kb
Host smart-0708085e-9ba3-4d8a-9045-bc0943255e3d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610809428 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_filter_stre
ss.1610809428
Directory /workspace/48.gpio_filter_stress/latest

Test location /workspace/coverage/default/48.gpio_full_random.227368856
Short name T670
Test name
Test status
Simulation time 349321623 ps
CPU time 1.06 seconds
Started Jul 29 04:35:06 PM PDT 24
Finished Jul 29 04:35:07 PM PDT 24
Peak memory 198348 kb
Host smart-74d5bc93-4176-4314-a9a0-c80dcde6dac2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227368856 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_full_random.227368856
Directory /workspace/48.gpio_full_random/latest

Test location /workspace/coverage/default/48.gpio_intr_rand_pgm.1374633899
Short name T107
Test name
Test status
Simulation time 46346126 ps
CPU time 0.78 seconds
Started Jul 29 04:35:05 PM PDT 24
Finished Jul 29 04:35:06 PM PDT 24
Peak memory 195960 kb
Host smart-ac2a64f4-ef4e-40c5-976b-46367302ce81
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374633899 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_intr_rand_pgm.1374633899
Directory /workspace/48.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/48.gpio_intr_with_filter_rand_intr_event.240571049
Short name T173
Test name
Test status
Simulation time 71623428 ps
CPU time 2.78 seconds
Started Jul 29 04:35:09 PM PDT 24
Finished Jul 29 04:35:12 PM PDT 24
Peak memory 198380 kb
Host smart-7ae21a58-67d0-4009-b1b9-663d9bcc5f04
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240571049 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 48.gpio_intr_with_filter_rand_intr_event.240571049
Directory /workspace/48.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/48.gpio_rand_intr_trigger.2811550103
Short name T381
Test name
Test status
Simulation time 163796176 ps
CPU time 1.39 seconds
Started Jul 29 04:35:05 PM PDT 24
Finished Jul 29 04:35:06 PM PDT 24
Peak memory 196564 kb
Host smart-2dcb891e-fb36-4297-9b0d-891eefb30bec
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811550103 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_rand_intr_trigger
.2811550103
Directory /workspace/48.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din.1177203575
Short name T163
Test name
Test status
Simulation time 38612886 ps
CPU time 0.91 seconds
Started Jul 29 04:35:04 PM PDT 24
Finished Jul 29 04:35:05 PM PDT 24
Peak memory 197032 kb
Host smart-d9005c7b-5114-44ff-ab18-1f721608147f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177203575 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din.1177203575
Directory /workspace/48.gpio_random_dout_din/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din_no_pullup_pulldown.3797600347
Short name T99
Test name
Test status
Simulation time 287783514 ps
CPU time 0.85 seconds
Started Jul 29 04:35:11 PM PDT 24
Finished Jul 29 04:35:12 PM PDT 24
Peak memory 197592 kb
Host smart-fec13821-42ac-4527-b6f3-494da6b79068
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797600347 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din_no_pullu
p_pulldown.3797600347
Directory /workspace/48.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_random_long_reg_writes_reg_reads.782628539
Short name T680
Test name
Test status
Simulation time 239340618 ps
CPU time 4.13 seconds
Started Jul 29 04:35:08 PM PDT 24
Finished Jul 29 04:35:12 PM PDT 24
Peak memory 198324 kb
Host smart-53cad864-c934-4e50-a1c1-80857c858cc0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782628539 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_ran
dom_long_reg_writes_reg_reads.782628539
Directory /workspace/48.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/48.gpio_smoke.3250364057
Short name T609
Test name
Test status
Simulation time 151728696 ps
CPU time 1.29 seconds
Started Jul 29 04:35:09 PM PDT 24
Finished Jul 29 04:35:10 PM PDT 24
Peak memory 196976 kb
Host smart-7edc320c-99be-480c-a479-c3254eae9cee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3250364057 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke.3250364057
Directory /workspace/48.gpio_smoke/latest

Test location /workspace/coverage/default/48.gpio_smoke_no_pullup_pulldown.200426929
Short name T276
Test name
Test status
Simulation time 236820840 ps
CPU time 1.27 seconds
Started Jul 29 04:35:03 PM PDT 24
Finished Jul 29 04:35:05 PM PDT 24
Peak memory 198368 kb
Host smart-5b796119-4a25-45f7-a3d2-7098fc6713bb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200426929 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown.200426929
Directory /workspace/48.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_stress_all.2626959265
Short name T654
Test name
Test status
Simulation time 57898970429 ps
CPU time 218 seconds
Started Jul 29 04:35:14 PM PDT 24
Finished Jul 29 04:38:52 PM PDT 24
Peak memory 198580 kb
Host smart-74da0974-52f3-4d5c-ba77-f38354bc505e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626959265 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.
gpio_stress_all.2626959265
Directory /workspace/48.gpio_stress_all/latest

Test location /workspace/coverage/default/49.gpio_alert_test.1644344062
Short name T23
Test name
Test status
Simulation time 30349256 ps
CPU time 0.56 seconds
Started Jul 29 04:35:20 PM PDT 24
Finished Jul 29 04:35:21 PM PDT 24
Peak memory 194276 kb
Host smart-0a8e11ff-b004-4ccc-96d5-254505e67315
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644344062 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_alert_test.1644344062
Directory /workspace/49.gpio_alert_test/latest

Test location /workspace/coverage/default/49.gpio_dout_din_regs_random_rw.3672569035
Short name T452
Test name
Test status
Simulation time 72689146 ps
CPU time 0.63 seconds
Started Jul 29 04:35:04 PM PDT 24
Finished Jul 29 04:35:05 PM PDT 24
Peak memory 194660 kb
Host smart-8f677f51-8a54-43f5-a27a-c6b72559bf04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672569035 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_dout_din_regs_random_rw.3672569035
Directory /workspace/49.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/49.gpio_filter_stress.472047917
Short name T403
Test name
Test status
Simulation time 2038974159 ps
CPU time 26.35 seconds
Started Jul 29 04:35:11 PM PDT 24
Finished Jul 29 04:35:37 PM PDT 24
Peak memory 197484 kb
Host smart-49853423-d2ef-44f5-9c9a-155f68b1fe16
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472047917 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_filter_stres
s.472047917
Directory /workspace/49.gpio_filter_stress/latest

Test location /workspace/coverage/default/49.gpio_full_random.789064849
Short name T348
Test name
Test status
Simulation time 39266646 ps
CPU time 0.64 seconds
Started Jul 29 04:35:09 PM PDT 24
Finished Jul 29 04:35:09 PM PDT 24
Peak memory 194860 kb
Host smart-6ac3f762-bf08-401a-ad51-0bc4c6ff887a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789064849 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_full_random.789064849
Directory /workspace/49.gpio_full_random/latest

Test location /workspace/coverage/default/49.gpio_intr_rand_pgm.1258367046
Short name T530
Test name
Test status
Simulation time 79214862 ps
CPU time 0.83 seconds
Started Jul 29 04:35:17 PM PDT 24
Finished Jul 29 04:35:18 PM PDT 24
Peak memory 196792 kb
Host smart-ef39f46d-0f7a-4670-8749-3a0969c901c2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258367046 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_intr_rand_pgm.1258367046
Directory /workspace/49.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/49.gpio_intr_with_filter_rand_intr_event.3766596871
Short name T230
Test name
Test status
Simulation time 86069816 ps
CPU time 3.19 seconds
Started Jul 29 04:35:13 PM PDT 24
Finished Jul 29 04:35:17 PM PDT 24
Peak memory 198648 kb
Host smart-92a530f3-e475-43eb-a4b4-f1c754fdab9b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766596871 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 49.gpio_intr_with_filter_rand_intr_event.3766596871
Directory /workspace/49.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/49.gpio_rand_intr_trigger.3247082423
Short name T543
Test name
Test status
Simulation time 163046506 ps
CPU time 3.22 seconds
Started Jul 29 04:35:08 PM PDT 24
Finished Jul 29 04:35:11 PM PDT 24
Peak memory 197536 kb
Host smart-63513e58-fb7f-44bc-861d-024312d9dbd1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247082423 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_rand_intr_trigger
.3247082423
Directory /workspace/49.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din.3290839043
Short name T405
Test name
Test status
Simulation time 48653226 ps
CPU time 0.94 seconds
Started Jul 29 04:35:09 PM PDT 24
Finished Jul 29 04:35:10 PM PDT 24
Peak memory 196528 kb
Host smart-db3f59ec-c831-4ae3-85ec-8ff0e29385c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3290839043 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din.3290839043
Directory /workspace/49.gpio_random_dout_din/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din_no_pullup_pulldown.3844168350
Short name T690
Test name
Test status
Simulation time 61928480 ps
CPU time 0.86 seconds
Started Jul 29 04:35:06 PM PDT 24
Finished Jul 29 04:35:07 PM PDT 24
Peak memory 197512 kb
Host smart-6985c141-8ebd-4991-8212-250d82440aac
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844168350 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din_no_pullu
p_pulldown.3844168350
Directory /workspace/49.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_random_long_reg_writes_reg_reads.4179998817
Short name T559
Test name
Test status
Simulation time 1132028461 ps
CPU time 4.55 seconds
Started Jul 29 04:35:06 PM PDT 24
Finished Jul 29 04:35:11 PM PDT 24
Peak memory 198488 kb
Host smart-8f5d72c1-e034-425f-aded-131eed12cbe1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179998817 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_ra
ndom_long_reg_writes_reg_reads.4179998817
Directory /workspace/49.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/49.gpio_smoke.1008435534
Short name T493
Test name
Test status
Simulation time 138022261 ps
CPU time 1.16 seconds
Started Jul 29 04:35:05 PM PDT 24
Finished Jul 29 04:35:06 PM PDT 24
Peak memory 197204 kb
Host smart-7f9223d3-3122-496b-b85b-eea58509224e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1008435534 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke.1008435534
Directory /workspace/49.gpio_smoke/latest

Test location /workspace/coverage/default/49.gpio_smoke_no_pullup_pulldown.153843442
Short name T556
Test name
Test status
Simulation time 120289926 ps
CPU time 1.14 seconds
Started Jul 29 04:35:12 PM PDT 24
Finished Jul 29 04:35:13 PM PDT 24
Peak memory 197232 kb
Host smart-5c812e01-c6fe-4453-b64e-cc52f634eea3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153843442 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown.153843442
Directory /workspace/49.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_stress_all.2222767657
Short name T686
Test name
Test status
Simulation time 6182543524 ps
CPU time 35.67 seconds
Started Jul 29 04:35:20 PM PDT 24
Finished Jul 29 04:35:56 PM PDT 24
Peak memory 198956 kb
Host smart-d0458a4b-d15c-4a8e-807e-f90e5a95a3b0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222767657 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.
gpio_stress_all.2222767657
Directory /workspace/49.gpio_stress_all/latest

Test location /workspace/coverage/default/49.gpio_stress_all_with_rand_reset.965964816
Short name T646
Test name
Test status
Simulation time 255616843329 ps
CPU time 1243.03 seconds
Started Jul 29 04:35:14 PM PDT 24
Finished Jul 29 04:55:58 PM PDT 24
Peak memory 198756 kb
Host smart-a59a2947-cac7-4ab3-98d0-9eced98a8689
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=965964816 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_stress_all_with_rand_reset.965964816
Directory /workspace/49.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.gpio_alert_test.302141095
Short name T277
Test name
Test status
Simulation time 12311238 ps
CPU time 0.53 seconds
Started Jul 29 04:33:39 PM PDT 24
Finished Jul 29 04:33:40 PM PDT 24
Peak memory 193132 kb
Host smart-f32c09c3-c259-45a4-94be-a99badd17fec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302141095 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_alert_test.302141095
Directory /workspace/5.gpio_alert_test/latest

Test location /workspace/coverage/default/5.gpio_dout_din_regs_random_rw.2444099702
Short name T255
Test name
Test status
Simulation time 34434436 ps
CPU time 0.8 seconds
Started Jul 29 04:33:38 PM PDT 24
Finished Jul 29 04:33:39 PM PDT 24
Peak memory 195676 kb
Host smart-74078bf2-e45e-401d-9b0e-80d32802c520
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2444099702 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_dout_din_regs_random_rw.2444099702
Directory /workspace/5.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/5.gpio_filter_stress.1279338793
Short name T390
Test name
Test status
Simulation time 2924198118 ps
CPU time 26.46 seconds
Started Jul 29 04:33:49 PM PDT 24
Finished Jul 29 04:34:15 PM PDT 24
Peak memory 198608 kb
Host smart-597e2c8c-9815-49f4-9061-8f2ec54297fa
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279338793 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_filter_stres
s.1279338793
Directory /workspace/5.gpio_filter_stress/latest

Test location /workspace/coverage/default/5.gpio_full_random.2722126842
Short name T635
Test name
Test status
Simulation time 292866301 ps
CPU time 0.99 seconds
Started Jul 29 04:33:46 PM PDT 24
Finished Jul 29 04:33:47 PM PDT 24
Peak memory 198252 kb
Host smart-b4cc78eb-e67e-465c-b936-2281c736e84d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722126842 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_full_random.2722126842
Directory /workspace/5.gpio_full_random/latest

Test location /workspace/coverage/default/5.gpio_intr_rand_pgm.1145771417
Short name T242
Test name
Test status
Simulation time 295987442 ps
CPU time 1.29 seconds
Started Jul 29 04:33:49 PM PDT 24
Finished Jul 29 04:33:51 PM PDT 24
Peak memory 198492 kb
Host smart-c26c16cd-6c54-4e08-b58d-f82367268406
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145771417 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_intr_rand_pgm.1145771417
Directory /workspace/5.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/5.gpio_intr_with_filter_rand_intr_event.1745491770
Short name T553
Test name
Test status
Simulation time 129351119 ps
CPU time 2.52 seconds
Started Jul 29 04:33:47 PM PDT 24
Finished Jul 29 04:33:49 PM PDT 24
Peak memory 198612 kb
Host smart-908d73aa-ac70-4160-8e85-340ea8e96cd7
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745491770 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.gpio_intr_with_filter_rand_intr_event.1745491770
Directory /workspace/5.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/5.gpio_rand_intr_trigger.3226184905
Short name T209
Test name
Test status
Simulation time 153614948 ps
CPU time 2.05 seconds
Started Jul 29 04:33:57 PM PDT 24
Finished Jul 29 04:33:59 PM PDT 24
Peak memory 196480 kb
Host smart-6cbf6cef-c536-4193-b0b4-5715bd7167d3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226184905 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_rand_intr_trigger.
3226184905
Directory /workspace/5.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din.943606478
Short name T55
Test name
Test status
Simulation time 379164496 ps
CPU time 0.93 seconds
Started Jul 29 04:33:49 PM PDT 24
Finished Jul 29 04:33:50 PM PDT 24
Peak memory 197152 kb
Host smart-4dba160b-5bfe-401d-afae-54b5ceff636a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943606478 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din.943606478
Directory /workspace/5.gpio_random_dout_din/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din_no_pullup_pulldown.3739945300
Short name T596
Test name
Test status
Simulation time 62225330 ps
CPU time 0.79 seconds
Started Jul 29 04:33:40 PM PDT 24
Finished Jul 29 04:33:45 PM PDT 24
Peak memory 196772 kb
Host smart-0fe6c91d-bc1b-43e9-bd60-7c32b7bcec70
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739945300 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din_no_pullup
_pulldown.3739945300
Directory /workspace/5.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_random_long_reg_writes_reg_reads.2004325971
Short name T4
Test name
Test status
Simulation time 668572412 ps
CPU time 3.29 seconds
Started Jul 29 04:33:51 PM PDT 24
Finished Jul 29 04:33:55 PM PDT 24
Peak memory 198356 kb
Host smart-022acb2c-9b9b-472d-89cc-eb4e2085c2ec
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004325971 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_ran
dom_long_reg_writes_reg_reads.2004325971
Directory /workspace/5.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/5.gpio_smoke.687934231
Short name T315
Test name
Test status
Simulation time 73719656 ps
CPU time 1.33 seconds
Started Jul 29 04:33:50 PM PDT 24
Finished Jul 29 04:33:52 PM PDT 24
Peak memory 198356 kb
Host smart-4ca61d83-a7de-4a0f-8e2a-b0fb70e7c8ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687934231 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke.687934231
Directory /workspace/5.gpio_smoke/latest

Test location /workspace/coverage/default/5.gpio_smoke_no_pullup_pulldown.3105636247
Short name T25
Test name
Test status
Simulation time 242023473 ps
CPU time 1.09 seconds
Started Jul 29 04:34:00 PM PDT 24
Finished Jul 29 04:34:02 PM PDT 24
Peak memory 196016 kb
Host smart-6daaed7d-44ba-49ae-b716-7ce0791eb502
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105636247 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown.3105636247
Directory /workspace/5.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_stress_all.1458245490
Short name T666
Test name
Test status
Simulation time 6372103016 ps
CPU time 95.18 seconds
Started Jul 29 04:33:47 PM PDT 24
Finished Jul 29 04:35:22 PM PDT 24
Peak memory 198488 kb
Host smart-c0136830-52f0-4789-84f4-b3961b669df3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458245490 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.g
pio_stress_all.1458245490
Directory /workspace/5.gpio_stress_all/latest

Test location /workspace/coverage/default/5.gpio_stress_all_with_rand_reset.1044276441
Short name T61
Test name
Test status
Simulation time 11146323747 ps
CPU time 366.95 seconds
Started Jul 29 04:33:49 PM PDT 24
Finished Jul 29 04:39:56 PM PDT 24
Peak memory 198724 kb
Host smart-afd30467-2833-4f41-904a-0b626d554c60
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1044276441 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_stress_all_with_rand_reset.1044276441
Directory /workspace/5.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.gpio_alert_test.4290082857
Short name T358
Test name
Test status
Simulation time 45746071 ps
CPU time 0.57 seconds
Started Jul 29 04:33:56 PM PDT 24
Finished Jul 29 04:33:57 PM PDT 24
Peak memory 194292 kb
Host smart-544f6c0d-9fc2-4bb0-b901-604ae2b95e70
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290082857 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_alert_test.4290082857
Directory /workspace/6.gpio_alert_test/latest

Test location /workspace/coverage/default/6.gpio_dout_din_regs_random_rw.2300872470
Short name T214
Test name
Test status
Simulation time 20290433 ps
CPU time 0.67 seconds
Started Jul 29 04:33:49 PM PDT 24
Finished Jul 29 04:33:50 PM PDT 24
Peak memory 194400 kb
Host smart-eb697564-1647-4a3d-ba9f-5aaf80a09333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300872470 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_dout_din_regs_random_rw.2300872470
Directory /workspace/6.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/6.gpio_filter_stress.708507795
Short name T141
Test name
Test status
Simulation time 136296307 ps
CPU time 4.5 seconds
Started Jul 29 04:33:48 PM PDT 24
Finished Jul 29 04:33:53 PM PDT 24
Peak memory 196956 kb
Host smart-e12d1bf3-ff7e-4a6a-8380-5db051622ea7
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708507795 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_filter_stress
.708507795
Directory /workspace/6.gpio_filter_stress/latest

Test location /workspace/coverage/default/6.gpio_full_random.2401050854
Short name T384
Test name
Test status
Simulation time 68284370 ps
CPU time 0.93 seconds
Started Jul 29 04:33:42 PM PDT 24
Finished Jul 29 04:33:43 PM PDT 24
Peak memory 197596 kb
Host smart-21fb9906-3adb-4d45-8c51-ceafc32b04e7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401050854 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_full_random.2401050854
Directory /workspace/6.gpio_full_random/latest

Test location /workspace/coverage/default/6.gpio_intr_rand_pgm.885948084
Short name T119
Test name
Test status
Simulation time 100492392 ps
CPU time 0.83 seconds
Started Jul 29 04:33:54 PM PDT 24
Finished Jul 29 04:33:55 PM PDT 24
Peak memory 196812 kb
Host smart-2d6c391c-8352-46d9-9a46-9b0cf53c4249
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885948084 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_intr_rand_pgm.885948084
Directory /workspace/6.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/6.gpio_intr_with_filter_rand_intr_event.97800646
Short name T529
Test name
Test status
Simulation time 178603789 ps
CPU time 3.79 seconds
Started Jul 29 04:33:52 PM PDT 24
Finished Jul 29 04:33:56 PM PDT 24
Peak memory 198328 kb
Host smart-75f123d2-e7c2-4fc4-9ffd-2c496cdcc1c7
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97800646 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 6.gpio_intr_with_filter_rand_intr_event.97800646
Directory /workspace/6.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/6.gpio_rand_intr_trigger.90255168
Short name T246
Test name
Test status
Simulation time 502213975 ps
CPU time 2.47 seconds
Started Jul 29 04:33:51 PM PDT 24
Finished Jul 29 04:33:54 PM PDT 24
Peak memory 196236 kb
Host smart-d58943d7-2f92-46ff-92ea-cc873cab0853
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90255168 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_rand_intr_trigger.90255168
Directory /workspace/6.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din.4089676759
Short name T34
Test name
Test status
Simulation time 149800080 ps
CPU time 1 seconds
Started Jul 29 04:33:43 PM PDT 24
Finished Jul 29 04:33:45 PM PDT 24
Peak memory 197160 kb
Host smart-fe97d5ba-9900-4b37-a973-7e7918f4f39b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4089676759 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din.4089676759
Directory /workspace/6.gpio_random_dout_din/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din_no_pullup_pulldown.3820522768
Short name T708
Test name
Test status
Simulation time 100731515 ps
CPU time 0.75 seconds
Started Jul 29 04:33:45 PM PDT 24
Finished Jul 29 04:33:46 PM PDT 24
Peak memory 196004 kb
Host smart-eb462150-7ee2-41ee-b96d-62ace142c597
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820522768 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din_no_pullup
_pulldown.3820522768
Directory /workspace/6.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_random_long_reg_writes_reg_reads.769255260
Short name T327
Test name
Test status
Simulation time 295896251 ps
CPU time 4.72 seconds
Started Jul 29 04:34:01 PM PDT 24
Finished Jul 29 04:34:05 PM PDT 24
Peak memory 198388 kb
Host smart-312518fc-a2ff-4da2-a721-cc054728ebca
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769255260 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_rand
om_long_reg_writes_reg_reads.769255260
Directory /workspace/6.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/6.gpio_smoke.3252376862
Short name T597
Test name
Test status
Simulation time 202388687 ps
CPU time 0.99 seconds
Started Jul 29 04:33:47 PM PDT 24
Finished Jul 29 04:33:48 PM PDT 24
Peak memory 196288 kb
Host smart-d171e48d-9424-4e5e-94db-440a53a49abd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3252376862 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke.3252376862
Directory /workspace/6.gpio_smoke/latest

Test location /workspace/coverage/default/6.gpio_smoke_no_pullup_pulldown.1603352079
Short name T339
Test name
Test status
Simulation time 44980183 ps
CPU time 1.33 seconds
Started Jul 29 04:33:52 PM PDT 24
Finished Jul 29 04:33:53 PM PDT 24
Peak memory 197088 kb
Host smart-664e8103-e1a0-4c1b-8e81-46b7c134e935
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603352079 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown.1603352079
Directory /workspace/6.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_stress_all.3666522206
Short name T302
Test name
Test status
Simulation time 5897427731 ps
CPU time 134.42 seconds
Started Jul 29 04:33:47 PM PDT 24
Finished Jul 29 04:36:02 PM PDT 24
Peak memory 198556 kb
Host smart-862883e0-56ea-4ac2-b2fc-a17f8bb080a0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666522206 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.g
pio_stress_all.3666522206
Directory /workspace/6.gpio_stress_all/latest

Test location /workspace/coverage/default/6.gpio_stress_all_with_rand_reset.1282291041
Short name T430
Test name
Test status
Simulation time 320399670589 ps
CPU time 1029.54 seconds
Started Jul 29 04:33:47 PM PDT 24
Finished Jul 29 04:50:57 PM PDT 24
Peak memory 198680 kb
Host smart-88bdcc76-7e45-4e90-b23a-f2ed5b70a3f8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1282291041 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_stress_all_with_rand_reset.1282291041
Directory /workspace/6.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.gpio_alert_test.1626851689
Short name T710
Test name
Test status
Simulation time 11977068 ps
CPU time 0.55 seconds
Started Jul 29 04:33:50 PM PDT 24
Finished Jul 29 04:33:50 PM PDT 24
Peak memory 194428 kb
Host smart-428bfbb0-e885-408f-a927-778b2cbd3587
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626851689 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_alert_test.1626851689
Directory /workspace/7.gpio_alert_test/latest

Test location /workspace/coverage/default/7.gpio_dout_din_regs_random_rw.1047579881
Short name T347
Test name
Test status
Simulation time 45979232 ps
CPU time 0.93 seconds
Started Jul 29 04:33:43 PM PDT 24
Finished Jul 29 04:33:44 PM PDT 24
Peak memory 196688 kb
Host smart-86258ac9-d9c9-4b95-b506-cf517cb43a39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1047579881 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_dout_din_regs_random_rw.1047579881
Directory /workspace/7.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/7.gpio_filter_stress.1205071080
Short name T662
Test name
Test status
Simulation time 182282139 ps
CPU time 8.5 seconds
Started Jul 29 04:33:52 PM PDT 24
Finished Jul 29 04:34:01 PM PDT 24
Peak memory 196696 kb
Host smart-4e4bc7fb-6d9e-480a-9567-9024b4906338
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205071080 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_filter_stres
s.1205071080
Directory /workspace/7.gpio_filter_stress/latest

Test location /workspace/coverage/default/7.gpio_full_random.709372345
Short name T706
Test name
Test status
Simulation time 344500068 ps
CPU time 1.03 seconds
Started Jul 29 04:34:00 PM PDT 24
Finished Jul 29 04:34:01 PM PDT 24
Peak memory 197028 kb
Host smart-98ab5de5-907a-4544-9d23-242c8e32f7e0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709372345 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_full_random.709372345
Directory /workspace/7.gpio_full_random/latest

Test location /workspace/coverage/default/7.gpio_intr_rand_pgm.522375441
Short name T332
Test name
Test status
Simulation time 37654419 ps
CPU time 1.03 seconds
Started Jul 29 04:33:58 PM PDT 24
Finished Jul 29 04:34:00 PM PDT 24
Peak memory 196388 kb
Host smart-c6ec8977-5f6a-4413-a5e5-0585833d6cc3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522375441 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_intr_rand_pgm.522375441
Directory /workspace/7.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/7.gpio_intr_with_filter_rand_intr_event.1823138060
Short name T498
Test name
Test status
Simulation time 121280886 ps
CPU time 1.34 seconds
Started Jul 29 04:33:54 PM PDT 24
Finished Jul 29 04:33:55 PM PDT 24
Peak memory 197288 kb
Host smart-6c798490-5ef4-4434-b666-27689db95879
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823138060 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.gpio_intr_with_filter_rand_intr_event.1823138060
Directory /workspace/7.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/7.gpio_rand_intr_trigger.1265844606
Short name T582
Test name
Test status
Simulation time 560740296 ps
CPU time 3.24 seconds
Started Jul 29 04:33:58 PM PDT 24
Finished Jul 29 04:34:02 PM PDT 24
Peak memory 197276 kb
Host smart-6b596e46-6d95-41c2-b791-cf95eeb354f1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265844606 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_rand_intr_trigger.
1265844606
Directory /workspace/7.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din.3766463750
Short name T495
Test name
Test status
Simulation time 98385907 ps
CPU time 1.16 seconds
Started Jul 29 04:33:59 PM PDT 24
Finished Jul 29 04:34:00 PM PDT 24
Peak memory 196460 kb
Host smart-b1973d0d-929c-40cf-a8d8-9fd916ade7a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766463750 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din.3766463750
Directory /workspace/7.gpio_random_dout_din/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din_no_pullup_pulldown.1417039159
Short name T232
Test name
Test status
Simulation time 28687588 ps
CPU time 1.14 seconds
Started Jul 29 04:33:51 PM PDT 24
Finished Jul 29 04:33:52 PM PDT 24
Peak memory 196468 kb
Host smart-5b94e5f2-eff1-43eb-b2dc-e11299ed09e5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417039159 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din_no_pullup
_pulldown.1417039159
Directory /workspace/7.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_random_long_reg_writes_reg_reads.699652004
Short name T177
Test name
Test status
Simulation time 173646964 ps
CPU time 1.19 seconds
Started Jul 29 04:33:59 PM PDT 24
Finished Jul 29 04:34:00 PM PDT 24
Peak memory 198328 kb
Host smart-8df87885-2004-46af-94db-39dcdc888358
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699652004 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_rand
om_long_reg_writes_reg_reads.699652004
Directory /workspace/7.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/7.gpio_smoke.999306991
Short name T130
Test name
Test status
Simulation time 37768731 ps
CPU time 1.02 seconds
Started Jul 29 04:33:53 PM PDT 24
Finished Jul 29 04:33:55 PM PDT 24
Peak memory 195908 kb
Host smart-05b103a9-dc27-48d9-86a5-93ab8c76a2a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=999306991 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke.999306991
Directory /workspace/7.gpio_smoke/latest

Test location /workspace/coverage/default/7.gpio_smoke_no_pullup_pulldown.1913024754
Short name T193
Test name
Test status
Simulation time 186503924 ps
CPU time 1.2 seconds
Started Jul 29 04:33:51 PM PDT 24
Finished Jul 29 04:33:52 PM PDT 24
Peak memory 196244 kb
Host smart-fccfd6a0-e859-4505-bd99-af83f6b7d5ba
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913024754 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown.1913024754
Directory /workspace/7.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_stress_all.209963325
Short name T317
Test name
Test status
Simulation time 3053116983 ps
CPU time 25.26 seconds
Started Jul 29 04:33:52 PM PDT 24
Finished Jul 29 04:34:17 PM PDT 24
Peak memory 198680 kb
Host smart-d5e40c2f-98b7-4380-b4b6-e8dfc79dfd4a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209963325 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gp
io_stress_all.209963325
Directory /workspace/7.gpio_stress_all/latest

Test location /workspace/coverage/default/7.gpio_stress_all_with_rand_reset.528957971
Short name T62
Test name
Test status
Simulation time 46496486090 ps
CPU time 560.82 seconds
Started Jul 29 04:33:45 PM PDT 24
Finished Jul 29 04:43:06 PM PDT 24
Peak memory 198728 kb
Host smart-402f520b-d502-4ac7-a84c-40cbc49cc646
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=528957971 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_stress_all_with_rand_reset.528957971
Directory /workspace/7.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.gpio_alert_test.1553256448
Short name T329
Test name
Test status
Simulation time 36454021 ps
CPU time 0.58 seconds
Started Jul 29 04:34:01 PM PDT 24
Finished Jul 29 04:34:01 PM PDT 24
Peak memory 194512 kb
Host smart-3318c2c4-3653-45d1-8443-61139d9f8e90
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553256448 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_alert_test.1553256448
Directory /workspace/8.gpio_alert_test/latest

Test location /workspace/coverage/default/8.gpio_dout_din_regs_random_rw.2958651092
Short name T391
Test name
Test status
Simulation time 79679624 ps
CPU time 0.89 seconds
Started Jul 29 04:34:08 PM PDT 24
Finished Jul 29 04:34:09 PM PDT 24
Peak memory 196824 kb
Host smart-0718d123-18b9-461c-a07f-ebd2c71f033e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2958651092 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_dout_din_regs_random_rw.2958651092
Directory /workspace/8.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/8.gpio_filter_stress.3500319006
Short name T611
Test name
Test status
Simulation time 629277597 ps
CPU time 8.43 seconds
Started Jul 29 04:33:49 PM PDT 24
Finished Jul 29 04:33:58 PM PDT 24
Peak memory 197240 kb
Host smart-41281e53-dfeb-4e85-ac6c-3964f4b0855b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500319006 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_filter_stres
s.3500319006
Directory /workspace/8.gpio_filter_stress/latest

Test location /workspace/coverage/default/8.gpio_full_random.2327449560
Short name T21
Test name
Test status
Simulation time 191491169 ps
CPU time 1.1 seconds
Started Jul 29 04:33:56 PM PDT 24
Finished Jul 29 04:33:57 PM PDT 24
Peak memory 198420 kb
Host smart-c952f812-f94f-4df3-9fc8-45690cef7e2e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327449560 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_full_random.2327449560
Directory /workspace/8.gpio_full_random/latest

Test location /workspace/coverage/default/8.gpio_intr_rand_pgm.409044078
Short name T401
Test name
Test status
Simulation time 286220613 ps
CPU time 1.04 seconds
Started Jul 29 04:34:05 PM PDT 24
Finished Jul 29 04:34:06 PM PDT 24
Peak memory 196344 kb
Host smart-223a8b2b-6c2c-4906-bf9f-9b53249b32bd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409044078 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_intr_rand_pgm.409044078
Directory /workspace/8.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/8.gpio_intr_with_filter_rand_intr_event.514218671
Short name T507
Test name
Test status
Simulation time 57673636 ps
CPU time 2.23 seconds
Started Jul 29 04:33:52 PM PDT 24
Finished Jul 29 04:33:54 PM PDT 24
Peak memory 198464 kb
Host smart-e3893fb2-d4dd-40eb-8648-2f8eb2002361
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514218671 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 8.gpio_intr_with_filter_rand_intr_event.514218671
Directory /workspace/8.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/8.gpio_rand_intr_trigger.4017928493
Short name T479
Test name
Test status
Simulation time 58651441 ps
CPU time 1.81 seconds
Started Jul 29 04:33:47 PM PDT 24
Finished Jul 29 04:33:49 PM PDT 24
Peak memory 196616 kb
Host smart-bfedc65f-c52c-45fb-aa02-4be4b7a7a0f2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017928493 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_rand_intr_trigger.
4017928493
Directory /workspace/8.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din.2139429521
Short name T260
Test name
Test status
Simulation time 160694187 ps
CPU time 1.04 seconds
Started Jul 29 04:33:54 PM PDT 24
Finished Jul 29 04:33:55 PM PDT 24
Peak memory 196464 kb
Host smart-6b728b13-e6e5-40c2-b4ab-f6977c50559a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2139429521 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din.2139429521
Directory /workspace/8.gpio_random_dout_din/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din_no_pullup_pulldown.3410826899
Short name T590
Test name
Test status
Simulation time 103413943 ps
CPU time 0.84 seconds
Started Jul 29 04:33:47 PM PDT 24
Finished Jul 29 04:33:48 PM PDT 24
Peak memory 196836 kb
Host smart-72476f85-7070-4e91-b13e-baacd019e1cb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410826899 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din_no_pullup
_pulldown.3410826899
Directory /workspace/8.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_random_long_reg_writes_reg_reads.499028448
Short name T133
Test name
Test status
Simulation time 333591201 ps
CPU time 4.07 seconds
Started Jul 29 04:33:54 PM PDT 24
Finished Jul 29 04:33:58 PM PDT 24
Peak memory 198400 kb
Host smart-658a13f2-6877-4b0f-ad8d-1b44c84ef2db
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499028448 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_rand
om_long_reg_writes_reg_reads.499028448
Directory /workspace/8.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/8.gpio_smoke.1558504077
Short name T462
Test name
Test status
Simulation time 72499815 ps
CPU time 1.16 seconds
Started Jul 29 04:34:01 PM PDT 24
Finished Jul 29 04:34:02 PM PDT 24
Peak memory 196004 kb
Host smart-dc7e8e5a-005c-49a0-ad3e-18c71b8143fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558504077 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke.1558504077
Directory /workspace/8.gpio_smoke/latest

Test location /workspace/coverage/default/8.gpio_smoke_no_pullup_pulldown.629658802
Short name T423
Test name
Test status
Simulation time 214770353 ps
CPU time 0.9 seconds
Started Jul 29 04:33:52 PM PDT 24
Finished Jul 29 04:33:53 PM PDT 24
Peak memory 196728 kb
Host smart-ac38e27b-1909-4a8e-a763-4d50195c23cf
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629658802 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown.629658802
Directory /workspace/8.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_stress_all.3404750348
Short name T387
Test name
Test status
Simulation time 12269835210 ps
CPU time 164.09 seconds
Started Jul 29 04:33:51 PM PDT 24
Finished Jul 29 04:36:35 PM PDT 24
Peak memory 198500 kb
Host smart-ffc59f53-892a-4ae1-8e71-b47c34ac2217
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404750348 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.g
pio_stress_all.3404750348
Directory /workspace/8.gpio_stress_all/latest

Test location /workspace/coverage/default/9.gpio_alert_test.522594045
Short name T560
Test name
Test status
Simulation time 23630011 ps
CPU time 0.56 seconds
Started Jul 29 04:34:01 PM PDT 24
Finished Jul 29 04:34:02 PM PDT 24
Peak memory 193836 kb
Host smart-12a6c27b-ce1c-466b-a307-8641a3414f9a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522594045 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_alert_test.522594045
Directory /workspace/9.gpio_alert_test/latest

Test location /workspace/coverage/default/9.gpio_dout_din_regs_random_rw.2086099392
Short name T256
Test name
Test status
Simulation time 109412791 ps
CPU time 0.84 seconds
Started Jul 29 04:33:51 PM PDT 24
Finished Jul 29 04:33:52 PM PDT 24
Peak memory 196824 kb
Host smart-03759c7b-0ce0-4d99-affd-79b7ad155859
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2086099392 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_dout_din_regs_random_rw.2086099392
Directory /workspace/9.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/9.gpio_filter_stress.2829589546
Short name T226
Test name
Test status
Simulation time 942382182 ps
CPU time 10.87 seconds
Started Jul 29 04:33:56 PM PDT 24
Finished Jul 29 04:34:07 PM PDT 24
Peak memory 195884 kb
Host smart-0153786e-fbda-4cb5-9ce2-f02bd70b8970
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829589546 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_filter_stres
s.2829589546
Directory /workspace/9.gpio_filter_stress/latest

Test location /workspace/coverage/default/9.gpio_full_random.3005188028
Short name T236
Test name
Test status
Simulation time 76013980 ps
CPU time 0.7 seconds
Started Jul 29 04:34:03 PM PDT 24
Finished Jul 29 04:34:04 PM PDT 24
Peak memory 194920 kb
Host smart-65b21132-b00c-4765-8324-9f608ee1ef5f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005188028 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_full_random.3005188028
Directory /workspace/9.gpio_full_random/latest

Test location /workspace/coverage/default/9.gpio_intr_rand_pgm.1703446377
Short name T257
Test name
Test status
Simulation time 107709017 ps
CPU time 0.92 seconds
Started Jul 29 04:33:58 PM PDT 24
Finished Jul 29 04:33:59 PM PDT 24
Peak memory 196496 kb
Host smart-dde43b1d-8b47-451a-901d-aa633d3a2ab3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703446377 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_intr_rand_pgm.1703446377
Directory /workspace/9.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/9.gpio_intr_with_filter_rand_intr_event.1965699823
Short name T195
Test name
Test status
Simulation time 278590150 ps
CPU time 2.96 seconds
Started Jul 29 04:33:44 PM PDT 24
Finished Jul 29 04:33:47 PM PDT 24
Peak memory 198544 kb
Host smart-15f07ef6-96c4-4e5d-b648-4c691b0d08b1
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965699823 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.gpio_intr_with_filter_rand_intr_event.1965699823
Directory /workspace/9.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/9.gpio_rand_intr_trigger.1678924745
Short name T364
Test name
Test status
Simulation time 52365836 ps
CPU time 0.98 seconds
Started Jul 29 04:33:57 PM PDT 24
Finished Jul 29 04:33:58 PM PDT 24
Peak memory 196012 kb
Host smart-a2f5aaae-386b-442d-bbd3-b4237c9992e4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678924745 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_rand_intr_trigger.
1678924745
Directory /workspace/9.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din.3382365669
Short name T138
Test name
Test status
Simulation time 71847252 ps
CPU time 1.29 seconds
Started Jul 29 04:34:05 PM PDT 24
Finished Jul 29 04:34:06 PM PDT 24
Peak memory 197384 kb
Host smart-ad85a196-761b-4575-b974-2c8ece9c3f72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3382365669 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din.3382365669
Directory /workspace/9.gpio_random_dout_din/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din_no_pullup_pulldown.3026630523
Short name T482
Test name
Test status
Simulation time 45749621 ps
CPU time 0.69 seconds
Started Jul 29 04:33:55 PM PDT 24
Finished Jul 29 04:33:56 PM PDT 24
Peak memory 194692 kb
Host smart-e447067c-2381-44d7-9d64-6c12b4c6f223
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026630523 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din_no_pullup
_pulldown.3026630523
Directory /workspace/9.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_random_long_reg_writes_reg_reads.181921020
Short name T359
Test name
Test status
Simulation time 502071214 ps
CPU time 1.78 seconds
Started Jul 29 04:34:03 PM PDT 24
Finished Jul 29 04:34:05 PM PDT 24
Peak memory 198368 kb
Host smart-762abb46-7c62-4f9a-be79-4f75b9fe8571
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181921020 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_rand
om_long_reg_writes_reg_reads.181921020
Directory /workspace/9.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/9.gpio_smoke.1937304232
Short name T139
Test name
Test status
Simulation time 30427451 ps
CPU time 0.71 seconds
Started Jul 29 04:33:53 PM PDT 24
Finished Jul 29 04:33:54 PM PDT 24
Peak memory 194564 kb
Host smart-b4e0ddbb-ae3f-45de-b03c-ee51935ad3d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1937304232 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke.1937304232
Directory /workspace/9.gpio_smoke/latest

Test location /workspace/coverage/default/9.gpio_smoke_no_pullup_pulldown.2786384693
Short name T199
Test name
Test status
Simulation time 84832823 ps
CPU time 0.87 seconds
Started Jul 29 04:33:57 PM PDT 24
Finished Jul 29 04:33:58 PM PDT 24
Peak memory 196296 kb
Host smart-4a5327b5-e96c-47ba-8f34-cca65ac01fea
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786384693 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown.2786384693
Directory /workspace/9.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_stress_all.3500408072
Short name T577
Test name
Test status
Simulation time 17312053300 ps
CPU time 230.26 seconds
Started Jul 29 04:34:05 PM PDT 24
Finished Jul 29 04:37:56 PM PDT 24
Peak memory 198532 kb
Host smart-50f1aecd-9970-4a1c-97ad-b816c7e53ab3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500408072 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.g
pio_stress_all.3500408072
Directory /workspace/9.gpio_stress_all/latest

Test location /workspace/coverage/default/9.gpio_stress_all_with_rand_reset.773339298
Short name T637
Test name
Test status
Simulation time 187225065007 ps
CPU time 1039.29 seconds
Started Jul 29 04:33:59 PM PDT 24
Finished Jul 29 04:51:19 PM PDT 24
Peak memory 198640 kb
Host smart-4940ecc0-f672-466f-bd30-5d2d22d7f552
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=773339298 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_stress_all_with_rand_reset.773339298
Directory /workspace/9.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.1608819182
Short name T928
Test name
Test status
Simulation time 24170280 ps
CPU time 0.75 seconds
Started Jul 29 04:22:33 PM PDT 24
Finished Jul 29 04:22:34 PM PDT 24
Peak memory 195268 kb
Host smart-4f699afe-0742-469c-b45f-18159a70d979
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1608819182 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_en_cdc_prim.1608819182
Directory /workspace/0.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2606745128
Short name T897
Test name
Test status
Simulation time 250657542 ps
CPU time 1.21 seconds
Started Jul 29 04:25:25 PM PDT 24
Finished Jul 29 04:25:27 PM PDT 24
Peak memory 196492 kb
Host smart-1d035009-3ba2-4856-ba93-781ca4ae59eb
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606745128 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2606745128
Directory /workspace/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.71837661
Short name T851
Test name
Test status
Simulation time 1360701007 ps
CPU time 1.36 seconds
Started Jul 29 04:25:34 PM PDT 24
Finished Jul 29 04:25:36 PM PDT 24
Peak memory 195616 kb
Host smart-0a3586a7-6ee1-4cf4-b034-9169abe35f62
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=71837661 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_en_cdc_prim.71837661
Directory /workspace/1.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3355009375
Short name T934
Test name
Test status
Simulation time 74172976 ps
CPU time 1.36 seconds
Started Jul 29 04:21:15 PM PDT 24
Finished Jul 29 04:21:17 PM PDT 24
Peak memory 196992 kb
Host smart-db2b8ec8-e024-4b01-8afa-494eca6a0d2e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355009375 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3355009375
Directory /workspace/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.1468599234
Short name T891
Test name
Test status
Simulation time 40165998 ps
CPU time 1.11 seconds
Started Jul 29 04:33:25 PM PDT 24
Finished Jul 29 04:33:26 PM PDT 24
Peak memory 195460 kb
Host smart-2edc12ab-db1e-4c0b-8c71-59cba6c0ebdc
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1468599234 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_en_cdc_prim.1468599234
Directory /workspace/10.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1664050944
Short name T920
Test name
Test status
Simulation time 375154909 ps
CPU time 1.54 seconds
Started Jul 29 04:33:28 PM PDT 24
Finished Jul 29 04:33:30 PM PDT 24
Peak memory 196556 kb
Host smart-ace13a89-dc29-48e8-86c0-26aabbaa9eac
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664050944 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1664050944
Directory /workspace/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.775198370
Short name T923
Test name
Test status
Simulation time 28240789 ps
CPU time 0.73 seconds
Started Jul 29 04:33:20 PM PDT 24
Finished Jul 29 04:33:21 PM PDT 24
Peak memory 195872 kb
Host smart-a55794eb-8a6a-42bf-81ed-0354adf40621
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=775198370 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_en_cdc_prim.775198370
Directory /workspace/11.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4277067116
Short name T919
Test name
Test status
Simulation time 61655642 ps
CPU time 1.19 seconds
Started Jul 29 04:33:29 PM PDT 24
Finished Jul 29 04:33:30 PM PDT 24
Peak memory 196580 kb
Host smart-ef89bbfb-a98a-4819-9552-e80bad134e1a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277067116 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4277067116
Directory /workspace/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.2209033287
Short name T867
Test name
Test status
Simulation time 30745823 ps
CPU time 0.91 seconds
Started Jul 29 04:33:15 PM PDT 24
Finished Jul 29 04:33:17 PM PDT 24
Peak memory 197656 kb
Host smart-f4188871-68a7-462f-8747-06be39d752cf
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2209033287 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_en_cdc_prim.2209033287
Directory /workspace/12.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3682189690
Short name T927
Test name
Test status
Simulation time 14613881 ps
CPU time 0.67 seconds
Started Jul 29 04:33:33 PM PDT 24
Finished Jul 29 04:33:34 PM PDT 24
Peak memory 194088 kb
Host smart-28fe4af7-7a22-4e56-8c21-6d614d1eecb7
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682189690 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3682189690
Directory /workspace/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.1163450658
Short name T945
Test name
Test status
Simulation time 90926053 ps
CPU time 1.17 seconds
Started Jul 29 04:33:17 PM PDT 24
Finished Jul 29 04:33:18 PM PDT 24
Peak memory 196228 kb
Host smart-c55d32d0-12a6-4d83-891b-e4eb6b778f71
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1163450658 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_en_cdc_prim.1163450658
Directory /workspace/13.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2371678561
Short name T896
Test name
Test status
Simulation time 215698297 ps
CPU time 1.25 seconds
Started Jul 29 04:33:18 PM PDT 24
Finished Jul 29 04:33:19 PM PDT 24
Peak memory 197852 kb
Host smart-fc9c522c-6724-47d7-9e24-d916eaa9a86a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371678561 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2371678561
Directory /workspace/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.2879826461
Short name T886
Test name
Test status
Simulation time 175662042 ps
CPU time 0.94 seconds
Started Jul 29 04:33:16 PM PDT 24
Finished Jul 29 04:33:17 PM PDT 24
Peak memory 196160 kb
Host smart-8fa9aef3-3c56-483c-b0b2-824a3b6504b5
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2879826461 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_en_cdc_prim.2879826461
Directory /workspace/14.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3612813980
Short name T871
Test name
Test status
Simulation time 293227167 ps
CPU time 1.25 seconds
Started Jul 29 04:33:15 PM PDT 24
Finished Jul 29 04:33:17 PM PDT 24
Peak memory 196460 kb
Host smart-a9906d33-c7ed-4462-895f-1330648bbe1a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612813980 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3612813980
Directory /workspace/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.3081437334
Short name T946
Test name
Test status
Simulation time 126361763 ps
CPU time 1.26 seconds
Started Jul 29 04:33:18 PM PDT 24
Finished Jul 29 04:33:19 PM PDT 24
Peak memory 196396 kb
Host smart-82f67958-7380-4abe-a055-7bbe38d94e07
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3081437334 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_en_cdc_prim.3081437334
Directory /workspace/15.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1703882481
Short name T914
Test name
Test status
Simulation time 42439324 ps
CPU time 1.21 seconds
Started Jul 29 04:33:18 PM PDT 24
Finished Jul 29 04:33:20 PM PDT 24
Peak memory 196540 kb
Host smart-6fdd7c17-ec95-460c-a745-62e69353423e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703882481 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1703882481
Directory /workspace/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.1103385985
Short name T942
Test name
Test status
Simulation time 158693638 ps
CPU time 0.9 seconds
Started Jul 29 04:33:14 PM PDT 24
Finished Jul 29 04:33:15 PM PDT 24
Peak memory 196316 kb
Host smart-6baba3c1-fc10-464d-a45a-0c9808d9c8a2
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1103385985 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_en_cdc_prim.1103385985
Directory /workspace/16.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3541813096
Short name T857
Test name
Test status
Simulation time 60840833 ps
CPU time 1.13 seconds
Started Jul 29 04:33:15 PM PDT 24
Finished Jul 29 04:33:16 PM PDT 24
Peak memory 196336 kb
Host smart-8d47ee50-f284-487f-9006-e985cb455494
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541813096 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3541813096
Directory /workspace/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.542087818
Short name T904
Test name
Test status
Simulation time 496612028 ps
CPU time 1.45 seconds
Started Jul 29 04:33:19 PM PDT 24
Finished Jul 29 04:33:20 PM PDT 24
Peak memory 197864 kb
Host smart-aee2b79b-de15-49bd-aa53-698fb64b64ab
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=542087818 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_en_cdc_prim.542087818
Directory /workspace/17.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4241840431
Short name T922
Test name
Test status
Simulation time 128915643 ps
CPU time 0.83 seconds
Started Jul 29 04:33:20 PM PDT 24
Finished Jul 29 04:33:21 PM PDT 24
Peak memory 195904 kb
Host smart-3e7e3d69-7779-463c-bfce-cc7c4508ab38
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241840431 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4241840431
Directory /workspace/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.3552241449
Short name T847
Test name
Test status
Simulation time 66163433 ps
CPU time 1.06 seconds
Started Jul 29 04:33:14 PM PDT 24
Finished Jul 29 04:33:16 PM PDT 24
Peak memory 196308 kb
Host smart-1a8d1d9c-b9e2-4f3b-a937-e7ba73a5109d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3552241449 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_en_cdc_prim.3552241449
Directory /workspace/18.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3694211817
Short name T873
Test name
Test status
Simulation time 198998504 ps
CPU time 1.05 seconds
Started Jul 29 04:33:17 PM PDT 24
Finished Jul 29 04:33:18 PM PDT 24
Peak memory 196460 kb
Host smart-c537d1b3-59eb-4fc8-bf71-0b025ebda0ac
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694211817 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3694211817
Directory /workspace/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.1187231920
Short name T863
Test name
Test status
Simulation time 75167234 ps
CPU time 1.37 seconds
Started Jul 29 04:33:15 PM PDT 24
Finished Jul 29 04:33:17 PM PDT 24
Peak memory 196344 kb
Host smart-1668228c-076b-4e50-83f5-55a2cde4bb22
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1187231920 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_en_cdc_prim.1187231920
Directory /workspace/19.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2554822204
Short name T876
Test name
Test status
Simulation time 42955090 ps
CPU time 0.7 seconds
Started Jul 29 04:33:26 PM PDT 24
Finished Jul 29 04:33:27 PM PDT 24
Peak memory 194092 kb
Host smart-58bb184b-fc32-4de2-a64b-7ae301c782c4
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554822204 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2554822204
Directory /workspace/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.35929646
Short name T925
Test name
Test status
Simulation time 61902524 ps
CPU time 1.02 seconds
Started Jul 29 04:21:07 PM PDT 24
Finished Jul 29 04:21:08 PM PDT 24
Peak memory 197844 kb
Host smart-6f5e778d-3248-442b-ac44-c95864fdc3d3
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=35929646 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_en_cdc_prim.35929646
Directory /workspace/2.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.646118837
Short name T881
Test name
Test status
Simulation time 178933761 ps
CPU time 1.18 seconds
Started Jul 29 04:20:51 PM PDT 24
Finished Jul 29 04:20:52 PM PDT 24
Peak memory 197132 kb
Host smart-6250b098-7e81-40a8-b2fa-2ef1bf650a09
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646118837 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.646118837
Directory /workspace/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.3803420157
Short name T906
Test name
Test status
Simulation time 38054997 ps
CPU time 1.03 seconds
Started Jul 29 04:33:27 PM PDT 24
Finished Jul 29 04:33:28 PM PDT 24
Peak memory 195728 kb
Host smart-ab55c7a8-6fe7-425f-b18c-dc816b44afc5
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3803420157 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_en_cdc_prim.3803420157
Directory /workspace/20.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.423674802
Short name T887
Test name
Test status
Simulation time 166894792 ps
CPU time 1.12 seconds
Started Jul 29 04:33:25 PM PDT 24
Finished Jul 29 04:33:26 PM PDT 24
Peak memory 196576 kb
Host smart-78b6e151-413d-400f-8b84-510d8089f36a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423674802 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.423674802
Directory /workspace/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.623261817
Short name T933
Test name
Test status
Simulation time 231750405 ps
CPU time 1.26 seconds
Started Jul 29 04:33:15 PM PDT 24
Finished Jul 29 04:33:16 PM PDT 24
Peak memory 196464 kb
Host smart-c25e1e4a-be2f-46a0-aa7a-3bb60ee43b6f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=623261817 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_en_cdc_prim.623261817
Directory /workspace/21.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2509343731
Short name T879
Test name
Test status
Simulation time 33642496 ps
CPU time 1.03 seconds
Started Jul 29 04:33:15 PM PDT 24
Finished Jul 29 04:33:16 PM PDT 24
Peak memory 196324 kb
Host smart-8f1212ca-9162-4f6b-9f6a-7edb006254e5
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509343731 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2509343731
Directory /workspace/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.1312647888
Short name T874
Test name
Test status
Simulation time 75373622 ps
CPU time 0.8 seconds
Started Jul 29 04:33:30 PM PDT 24
Finished Jul 29 04:33:31 PM PDT 24
Peak memory 195116 kb
Host smart-64785dd7-9f81-49b7-81ae-e1d99b1c76d6
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1312647888 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_en_cdc_prim.1312647888
Directory /workspace/22.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2628470839
Short name T848
Test name
Test status
Simulation time 129516605 ps
CPU time 0.84 seconds
Started Jul 29 04:33:14 PM PDT 24
Finished Jul 29 04:33:15 PM PDT 24
Peak memory 195332 kb
Host smart-43f73de8-8848-4540-a899-5d2ae2fcb1e6
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628470839 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2628470839
Directory /workspace/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.64290465
Short name T884
Test name
Test status
Simulation time 68192614 ps
CPU time 1.29 seconds
Started Jul 29 04:33:17 PM PDT 24
Finished Jul 29 04:33:18 PM PDT 24
Peak memory 195660 kb
Host smart-b6407188-2262-4c4d-a768-4f2d83c2ddf4
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=64290465 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_en_cdc_prim.64290465
Directory /workspace/23.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3356578399
Short name T937
Test name
Test status
Simulation time 149035439 ps
CPU time 1.19 seconds
Started Jul 29 04:33:28 PM PDT 24
Finished Jul 29 04:33:29 PM PDT 24
Peak memory 196264 kb
Host smart-9ac66f96-ead2-4310-b413-7f3aa61d56f8
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356578399 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3356578399
Directory /workspace/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.1553622405
Short name T911
Test name
Test status
Simulation time 197812221 ps
CPU time 0.88 seconds
Started Jul 29 04:33:14 PM PDT 24
Finished Jul 29 04:33:15 PM PDT 24
Peak memory 196384 kb
Host smart-6ba02d04-230a-4ff6-bf17-d0c27d41caea
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1553622405 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_en_cdc_prim.1553622405
Directory /workspace/24.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.768497516
Short name T872
Test name
Test status
Simulation time 211597386 ps
CPU time 1.12 seconds
Started Jul 29 04:33:15 PM PDT 24
Finished Jul 29 04:33:16 PM PDT 24
Peak memory 196348 kb
Host smart-ea70a5ff-d8f5-46aa-9390-823d8476275c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768497516 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.768497516
Directory /workspace/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.670567006
Short name T900
Test name
Test status
Simulation time 64226374 ps
CPU time 1.24 seconds
Started Jul 29 04:33:28 PM PDT 24
Finished Jul 29 04:33:30 PM PDT 24
Peak memory 197556 kb
Host smart-be2ae41a-07aa-490a-a8dc-ee92a9ad856a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=670567006 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_en_cdc_prim.670567006
Directory /workspace/25.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.591310245
Short name T924
Test name
Test status
Simulation time 279536638 ps
CPU time 0.77 seconds
Started Jul 29 04:33:15 PM PDT 24
Finished Jul 29 04:33:16 PM PDT 24
Peak memory 194864 kb
Host smart-7306c902-b820-48f0-b57b-ed825ca335af
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591310245 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.591310245
Directory /workspace/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.1000886659
Short name T861
Test name
Test status
Simulation time 137322085 ps
CPU time 1.12 seconds
Started Jul 29 04:33:16 PM PDT 24
Finished Jul 29 04:33:17 PM PDT 24
Peak memory 196308 kb
Host smart-e42859be-2801-4bd1-80d6-772b3aae0bab
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1000886659 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_en_cdc_prim.1000886659
Directory /workspace/26.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2301544516
Short name T936
Test name
Test status
Simulation time 225848729 ps
CPU time 1.16 seconds
Started Jul 29 04:33:20 PM PDT 24
Finished Jul 29 04:33:21 PM PDT 24
Peak memory 196504 kb
Host smart-d40a7afe-80e1-4df2-b18e-193cce17f1b1
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301544516 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2301544516
Directory /workspace/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.1886070900
Short name T917
Test name
Test status
Simulation time 27466495 ps
CPU time 0.72 seconds
Started Jul 29 04:33:20 PM PDT 24
Finished Jul 29 04:33:21 PM PDT 24
Peak memory 194064 kb
Host smart-545c5c42-7d93-42cd-ad5c-d4800a3f548a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1886070900 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_en_cdc_prim.1886070900
Directory /workspace/27.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.660753602
Short name T929
Test name
Test status
Simulation time 38241613 ps
CPU time 1.11 seconds
Started Jul 29 04:33:19 PM PDT 24
Finished Jul 29 04:33:21 PM PDT 24
Peak memory 197832 kb
Host smart-b752205d-4587-46be-be16-e11fac02b790
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660753602 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.660753602
Directory /workspace/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.3968884737
Short name T890
Test name
Test status
Simulation time 409715564 ps
CPU time 1.16 seconds
Started Jul 29 04:33:21 PM PDT 24
Finished Jul 29 04:33:22 PM PDT 24
Peak memory 196776 kb
Host smart-28a7db39-df9f-4f8b-96d2-b9e117054039
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3968884737 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_en_cdc_prim.3968884737
Directory /workspace/28.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.66971512
Short name T885
Test name
Test status
Simulation time 226593072 ps
CPU time 1.06 seconds
Started Jul 29 04:33:31 PM PDT 24
Finished Jul 29 04:33:33 PM PDT 24
Peak memory 197776 kb
Host smart-5835c252-6f78-45b9-bad1-c0bffcee144c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66971512 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.66971512
Directory /workspace/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.2200643987
Short name T918
Test name
Test status
Simulation time 100208749 ps
CPU time 0.78 seconds
Started Jul 29 04:33:27 PM PDT 24
Finished Jul 29 04:33:28 PM PDT 24
Peak memory 195980 kb
Host smart-00caa3ca-696f-4d30-b279-9dd74aed012b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2200643987 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_en_cdc_prim.2200643987
Directory /workspace/29.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2398460424
Short name T889
Test name
Test status
Simulation time 62915608 ps
CPU time 1.19 seconds
Started Jul 29 04:33:30 PM PDT 24
Finished Jul 29 04:33:32 PM PDT 24
Peak memory 195724 kb
Host smart-ff570a40-57d6-4abf-b0b4-dc36e05e9c49
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398460424 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2398460424
Directory /workspace/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.2650301195
Short name T865
Test name
Test status
Simulation time 59149489 ps
CPU time 1.42 seconds
Started Jul 29 04:24:46 PM PDT 24
Finished Jul 29 04:24:48 PM PDT 24
Peak memory 196256 kb
Host smart-66609229-5e12-42d3-a0a1-60ef40fd0cfd
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2650301195 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_en_cdc_prim.2650301195
Directory /workspace/3.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3872046403
Short name T859
Test name
Test status
Simulation time 115267134 ps
CPU time 0.86 seconds
Started Jul 29 04:21:25 PM PDT 24
Finished Jul 29 04:21:26 PM PDT 24
Peak memory 195308 kb
Host smart-5d4c5441-355c-4cd6-9513-f8d9dfc1261b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872046403 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3872046403
Directory /workspace/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.3825821656
Short name T893
Test name
Test status
Simulation time 29985960 ps
CPU time 0.96 seconds
Started Jul 29 04:33:31 PM PDT 24
Finished Jul 29 04:33:32 PM PDT 24
Peak memory 196300 kb
Host smart-8998c0dd-6481-401e-8e65-b0f1db8f3637
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3825821656 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_en_cdc_prim.3825821656
Directory /workspace/30.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.542335116
Short name T878
Test name
Test status
Simulation time 67409573 ps
CPU time 1.16 seconds
Started Jul 29 04:33:26 PM PDT 24
Finished Jul 29 04:33:27 PM PDT 24
Peak memory 196980 kb
Host smart-e5de328e-bcb3-4c97-b05a-7cd568d5042c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542335116 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.542335116
Directory /workspace/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.3632156995
Short name T899
Test name
Test status
Simulation time 50508321 ps
CPU time 1.29 seconds
Started Jul 29 04:33:34 PM PDT 24
Finished Jul 29 04:33:36 PM PDT 24
Peak memory 195492 kb
Host smart-b14b1994-6a0e-4b15-8f4e-16496c2d6594
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3632156995 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_en_cdc_prim.3632156995
Directory /workspace/31.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.353252986
Short name T912
Test name
Test status
Simulation time 70558184 ps
CPU time 1.23 seconds
Started Jul 29 04:33:19 PM PDT 24
Finished Jul 29 04:33:21 PM PDT 24
Peak memory 196460 kb
Host smart-bbdcbd3f-5ba8-4db9-9ed2-bba93772e943
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353252986 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.353252986
Directory /workspace/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.3278623067
Short name T862
Test name
Test status
Simulation time 27510804 ps
CPU time 0.88 seconds
Started Jul 29 04:33:31 PM PDT 24
Finished Jul 29 04:33:32 PM PDT 24
Peak memory 196192 kb
Host smart-93447ff8-5e1f-4c1d-9de8-9f50eadcee00
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3278623067 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_en_cdc_prim.3278623067
Directory /workspace/32.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3072345881
Short name T877
Test name
Test status
Simulation time 50754770 ps
CPU time 1.05 seconds
Started Jul 29 04:33:31 PM PDT 24
Finished Jul 29 04:33:32 PM PDT 24
Peak memory 197648 kb
Host smart-1b19c1a3-b9a0-4614-b0be-a44acebdafd9
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072345881 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3072345881
Directory /workspace/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.3879354581
Short name T902
Test name
Test status
Simulation time 82727757 ps
CPU time 1.38 seconds
Started Jul 29 04:33:19 PM PDT 24
Finished Jul 29 04:33:20 PM PDT 24
Peak memory 196704 kb
Host smart-773a9ac1-35e9-4ecc-b748-84b221269355
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3879354581 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_en_cdc_prim.3879354581
Directory /workspace/33.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.263078096
Short name T931
Test name
Test status
Simulation time 686576245 ps
CPU time 0.92 seconds
Started Jul 29 04:33:46 PM PDT 24
Finished Jul 29 04:33:47 PM PDT 24
Peak memory 196456 kb
Host smart-a2030a33-60b1-4eb7-b861-7ddc3dfca2d4
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263078096 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.263078096
Directory /workspace/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.2048130226
Short name T932
Test name
Test status
Simulation time 90644050 ps
CPU time 1.15 seconds
Started Jul 29 04:33:20 PM PDT 24
Finished Jul 29 04:33:22 PM PDT 24
Peak memory 196492 kb
Host smart-6230be28-84f1-41d7-8d38-b36d385ecdc7
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2048130226 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_en_cdc_prim.2048130226
Directory /workspace/34.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2712483671
Short name T935
Test name
Test status
Simulation time 352655684 ps
CPU time 1.45 seconds
Started Jul 29 04:33:19 PM PDT 24
Finished Jul 29 04:33:21 PM PDT 24
Peak memory 197748 kb
Host smart-65018c2c-7b50-470d-b337-81e669b4fcb9
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712483671 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2712483671
Directory /workspace/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.3795018293
Short name T898
Test name
Test status
Simulation time 25915488 ps
CPU time 0.89 seconds
Started Jul 29 04:33:31 PM PDT 24
Finished Jul 29 04:33:32 PM PDT 24
Peak memory 196928 kb
Host smart-9f321c23-4804-479d-8422-20d6f726b51e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3795018293 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_en_cdc_prim.3795018293
Directory /workspace/35.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1611558786
Short name T926
Test name
Test status
Simulation time 200480143 ps
CPU time 0.93 seconds
Started Jul 29 04:33:34 PM PDT 24
Finished Jul 29 04:33:35 PM PDT 24
Peak memory 195928 kb
Host smart-96e2d883-6114-4701-9d0f-a45e100d79f4
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611558786 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1611558786
Directory /workspace/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.288723811
Short name T869
Test name
Test status
Simulation time 131513404 ps
CPU time 1.01 seconds
Started Jul 29 04:33:26 PM PDT 24
Finished Jul 29 04:33:27 PM PDT 24
Peak memory 196580 kb
Host smart-7f2fdff3-d237-451f-88c4-74007012b902
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=288723811 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_en_cdc_prim.288723811
Directory /workspace/36.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2297632914
Short name T892
Test name
Test status
Simulation time 43296683 ps
CPU time 1.07 seconds
Started Jul 29 04:33:21 PM PDT 24
Finished Jul 29 04:33:22 PM PDT 24
Peak memory 195944 kb
Host smart-184c5db7-d43c-4e1e-93b6-f7aad0e46c8a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297632914 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2297632914
Directory /workspace/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.1293340119
Short name T870
Test name
Test status
Simulation time 313889212 ps
CPU time 1.26 seconds
Started Jul 29 04:33:28 PM PDT 24
Finished Jul 29 04:33:29 PM PDT 24
Peak memory 196424 kb
Host smart-66f3f1cb-c545-4378-84e2-b22ae96f6761
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1293340119 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_en_cdc_prim.1293340119
Directory /workspace/37.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2394274897
Short name T910
Test name
Test status
Simulation time 32693317 ps
CPU time 0.93 seconds
Started Jul 29 04:33:29 PM PDT 24
Finished Jul 29 04:33:30 PM PDT 24
Peak memory 197836 kb
Host smart-9d0a1b3e-a78a-464d-b261-b5f6c7c2292b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394274897 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2394274897
Directory /workspace/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.946161574
Short name T854
Test name
Test status
Simulation time 71602265 ps
CPU time 1.14 seconds
Started Jul 29 04:33:20 PM PDT 24
Finished Jul 29 04:33:21 PM PDT 24
Peak memory 196356 kb
Host smart-54fea0e0-867b-41b2-9cdf-c819dc2d8d5d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=946161574 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_en_cdc_prim.946161574
Directory /workspace/38.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.714410832
Short name T858
Test name
Test status
Simulation time 142629385 ps
CPU time 1.21 seconds
Started Jul 29 04:33:31 PM PDT 24
Finished Jul 29 04:33:32 PM PDT 24
Peak memory 196372 kb
Host smart-da601e67-bb7c-4d87-8722-ca1d16812a7e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714410832 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.714410832
Directory /workspace/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.2524822602
Short name T905
Test name
Test status
Simulation time 41775544 ps
CPU time 1.16 seconds
Started Jul 29 04:33:21 PM PDT 24
Finished Jul 29 04:33:22 PM PDT 24
Peak memory 197832 kb
Host smart-404ab409-9973-4209-94c8-6d2c478b66e3
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2524822602 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_en_cdc_prim.2524822602
Directory /workspace/39.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1502385135
Short name T894
Test name
Test status
Simulation time 55632059 ps
CPU time 1.39 seconds
Started Jul 29 04:33:21 PM PDT 24
Finished Jul 29 04:33:23 PM PDT 24
Peak memory 196620 kb
Host smart-23cadd9c-1785-43c7-a49e-188c56c8553e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502385135 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1502385135
Directory /workspace/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.4196255130
Short name T943
Test name
Test status
Simulation time 536002383 ps
CPU time 1.24 seconds
Started Jul 29 04:21:25 PM PDT 24
Finished Jul 29 04:21:26 PM PDT 24
Peak memory 196688 kb
Host smart-0d6d3163-7b50-41ea-a634-70e2685874d7
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4196255130 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_en_cdc_prim.4196255130
Directory /workspace/4.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3192296111
Short name T895
Test name
Test status
Simulation time 47837635 ps
CPU time 1.33 seconds
Started Jul 29 04:21:12 PM PDT 24
Finished Jul 29 04:21:14 PM PDT 24
Peak memory 197184 kb
Host smart-05f8b1ec-f19a-4c01-bdfa-a2df72e4de6c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192296111 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3192296111
Directory /workspace/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.3743227770
Short name T941
Test name
Test status
Simulation time 46366354 ps
CPU time 1.02 seconds
Started Jul 29 04:33:28 PM PDT 24
Finished Jul 29 04:33:29 PM PDT 24
Peak memory 197140 kb
Host smart-aeddc4e3-834c-4a0b-ac77-0d0e4e64e238
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3743227770 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_en_cdc_prim.3743227770
Directory /workspace/40.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4165262328
Short name T853
Test name
Test status
Simulation time 167552307 ps
CPU time 1.24 seconds
Started Jul 29 04:33:20 PM PDT 24
Finished Jul 29 04:33:22 PM PDT 24
Peak memory 196600 kb
Host smart-ace3e8ca-e777-4b32-b17c-3b0754885232
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165262328 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4165262328
Directory /workspace/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.2392739369
Short name T903
Test name
Test status
Simulation time 80287514 ps
CPU time 0.77 seconds
Started Jul 29 04:33:20 PM PDT 24
Finished Jul 29 04:33:21 PM PDT 24
Peak memory 195152 kb
Host smart-6ddfb5d7-c0d8-4f06-a674-1406b9fbebc6
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2392739369 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_en_cdc_prim.2392739369
Directory /workspace/41.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2999906385
Short name T888
Test name
Test status
Simulation time 191693959 ps
CPU time 1.05 seconds
Started Jul 29 04:33:22 PM PDT 24
Finished Jul 29 04:33:24 PM PDT 24
Peak memory 195404 kb
Host smart-cd2fb637-825e-4835-a995-c48be318ddc9
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999906385 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2999906385
Directory /workspace/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.3751678067
Short name T852
Test name
Test status
Simulation time 50331377 ps
CPU time 0.95 seconds
Started Jul 29 04:33:27 PM PDT 24
Finished Jul 29 04:33:28 PM PDT 24
Peak memory 196472 kb
Host smart-cf88eac2-23ae-46d6-a08e-5ea0a13907b3
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3751678067 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_en_cdc_prim.3751678067
Directory /workspace/42.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2913957834
Short name T864
Test name
Test status
Simulation time 184233690 ps
CPU time 0.93 seconds
Started Jul 29 04:33:20 PM PDT 24
Finished Jul 29 04:33:21 PM PDT 24
Peak memory 197652 kb
Host smart-68036d19-37a7-4a51-b6ff-0e316da3bb7f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913957834 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2913957834
Directory /workspace/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.3371821004
Short name T939
Test name
Test status
Simulation time 262902040 ps
CPU time 1.04 seconds
Started Jul 29 04:33:21 PM PDT 24
Finished Jul 29 04:33:22 PM PDT 24
Peak memory 196600 kb
Host smart-bdffa2b5-3eef-4668-9170-12babd2589bb
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3371821004 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_en_cdc_prim.3371821004
Directory /workspace/43.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.654858183
Short name T860
Test name
Test status
Simulation time 51746921 ps
CPU time 1.04 seconds
Started Jul 29 04:33:28 PM PDT 24
Finished Jul 29 04:33:29 PM PDT 24
Peak memory 196448 kb
Host smart-55a2c8d6-bc2b-433a-a1d7-2e132178e4c5
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654858183 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.654858183
Directory /workspace/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.2410410488
Short name T938
Test name
Test status
Simulation time 108596722 ps
CPU time 0.89 seconds
Started Jul 29 04:33:18 PM PDT 24
Finished Jul 29 04:33:19 PM PDT 24
Peak memory 196248 kb
Host smart-3a0f0d43-a592-4721-a902-ca03a13cdc96
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2410410488 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_en_cdc_prim.2410410488
Directory /workspace/44.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1286474282
Short name T907
Test name
Test status
Simulation time 50610105 ps
CPU time 0.82 seconds
Started Jul 29 04:33:19 PM PDT 24
Finished Jul 29 04:33:20 PM PDT 24
Peak memory 196432 kb
Host smart-5d7d9c11-605c-45e1-9df3-4e0557e6bc82
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286474282 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1286474282
Directory /workspace/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.2520414834
Short name T850
Test name
Test status
Simulation time 115556394 ps
CPU time 1.03 seconds
Started Jul 29 04:33:33 PM PDT 24
Finished Jul 29 04:33:35 PM PDT 24
Peak memory 196312 kb
Host smart-7f7932a4-ab5a-4650-82f7-33c6d1b94e59
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2520414834 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_en_cdc_prim.2520414834
Directory /workspace/45.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1920506061
Short name T856
Test name
Test status
Simulation time 47359575 ps
CPU time 1.29 seconds
Started Jul 29 04:33:32 PM PDT 24
Finished Jul 29 04:33:33 PM PDT 24
Peak memory 196660 kb
Host smart-9fda1598-bbb5-4b18-afd8-23efc5db618e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920506061 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1920506061
Directory /workspace/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.1479032160
Short name T901
Test name
Test status
Simulation time 68098631 ps
CPU time 1.27 seconds
Started Jul 29 04:33:42 PM PDT 24
Finished Jul 29 04:33:44 PM PDT 24
Peak memory 197780 kb
Host smart-9a780dd1-fb30-48bc-bfa5-41954f9e7051
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1479032160 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_en_cdc_prim.1479032160
Directory /workspace/46.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2649346838
Short name T849
Test name
Test status
Simulation time 204319513 ps
CPU time 1.01 seconds
Started Jul 29 04:33:22 PM PDT 24
Finished Jul 29 04:33:23 PM PDT 24
Peak memory 196260 kb
Host smart-3871b75a-8ffb-4ce7-9487-14c91c651edc
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649346838 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2649346838
Directory /workspace/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.2708037786
Short name T866
Test name
Test status
Simulation time 53133867 ps
CPU time 1.31 seconds
Started Jul 29 04:33:21 PM PDT 24
Finished Jul 29 04:33:22 PM PDT 24
Peak memory 196600 kb
Host smart-dc19a54b-7dab-48d4-b38d-c96e7b2f59ad
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2708037786 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_en_cdc_prim.2708037786
Directory /workspace/47.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1385090371
Short name T868
Test name
Test status
Simulation time 328692057 ps
CPU time 1.37 seconds
Started Jul 29 04:33:23 PM PDT 24
Finished Jul 29 04:33:24 PM PDT 24
Peak memory 197876 kb
Host smart-3e63d111-92a8-4eb8-9ea8-c4b7df1e8fa8
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385090371 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1385090371
Directory /workspace/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.2514855771
Short name T915
Test name
Test status
Simulation time 382187424 ps
CPU time 1.36 seconds
Started Jul 29 04:33:21 PM PDT 24
Finished Jul 29 04:33:23 PM PDT 24
Peak memory 196632 kb
Host smart-32b8ae18-ac08-4a3f-a4b9-9fec5fb88096
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2514855771 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_en_cdc_prim.2514855771
Directory /workspace/48.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2703899327
Short name T882
Test name
Test status
Simulation time 302436095 ps
CPU time 1.37 seconds
Started Jul 29 04:33:19 PM PDT 24
Finished Jul 29 04:33:20 PM PDT 24
Peak memory 196468 kb
Host smart-e2c7083c-a231-4fda-ac74-4f5f8c4edabd
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703899327 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2703899327
Directory /workspace/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.512227859
Short name T880
Test name
Test status
Simulation time 402648522 ps
CPU time 1.15 seconds
Started Jul 29 04:33:27 PM PDT 24
Finished Jul 29 04:33:28 PM PDT 24
Peak memory 196460 kb
Host smart-a6689cd9-f9d4-4e26-a06e-a008d4cc4143
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=512227859 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_en_cdc_prim.512227859
Directory /workspace/49.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1035621308
Short name T944
Test name
Test status
Simulation time 184363247 ps
CPU time 1.25 seconds
Started Jul 29 04:33:43 PM PDT 24
Finished Jul 29 04:33:44 PM PDT 24
Peak memory 196360 kb
Host smart-3384fdf4-6b63-4a37-99c6-f319a2f27993
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035621308 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1035621308
Directory /workspace/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.3077112703
Short name T883
Test name
Test status
Simulation time 50019389 ps
CPU time 1.29 seconds
Started Jul 29 04:33:12 PM PDT 24
Finished Jul 29 04:33:14 PM PDT 24
Peak memory 197764 kb
Host smart-fb8169ea-bd1e-46f0-8b70-440c90c8f09c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3077112703 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_en_cdc_prim.3077112703
Directory /workspace/5.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.353054331
Short name T913
Test name
Test status
Simulation time 204403389 ps
CPU time 0.91 seconds
Started Jul 29 04:33:08 PM PDT 24
Finished Jul 29 04:33:09 PM PDT 24
Peak memory 195448 kb
Host smart-8243eb1c-496e-4e50-bbd1-073f8197bb5e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353054331 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.353054331
Directory /workspace/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.3053439834
Short name T930
Test name
Test status
Simulation time 131787180 ps
CPU time 0.84 seconds
Started Jul 29 04:33:09 PM PDT 24
Finished Jul 29 04:33:10 PM PDT 24
Peak memory 195912 kb
Host smart-273056b0-168c-4867-82fb-817bd1f1fde1
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3053439834 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_en_cdc_prim.3053439834
Directory /workspace/6.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3975634778
Short name T875
Test name
Test status
Simulation time 262889924 ps
CPU time 1.3 seconds
Started Jul 29 04:33:08 PM PDT 24
Finished Jul 29 04:33:09 PM PDT 24
Peak memory 196540 kb
Host smart-fed03cf4-2a04-4e25-8c94-208e2a9af987
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975634778 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3975634778
Directory /workspace/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.943147781
Short name T921
Test name
Test status
Simulation time 89063737 ps
CPU time 0.8 seconds
Started Jul 29 04:33:10 PM PDT 24
Finished Jul 29 04:33:11 PM PDT 24
Peak memory 195296 kb
Host smart-f4c040fd-8104-44fd-adfe-814555d9386e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=943147781 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_en_cdc_prim.943147781
Directory /workspace/7.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3352196553
Short name T916
Test name
Test status
Simulation time 19083987 ps
CPU time 0.7 seconds
Started Jul 29 04:33:11 PM PDT 24
Finished Jul 29 04:33:12 PM PDT 24
Peak memory 194704 kb
Host smart-fc5f19ae-24dc-4a4b-82c7-5ccc029b4c27
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352196553 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3352196553
Directory /workspace/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.605211145
Short name T855
Test name
Test status
Simulation time 31414163 ps
CPU time 0.81 seconds
Started Jul 29 04:33:15 PM PDT 24
Finished Jul 29 04:33:16 PM PDT 24
Peak memory 195232 kb
Host smart-4c6f41bc-dab9-4f0f-8f6e-4a70859b04e9
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=605211145 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_en_cdc_prim.605211145
Directory /workspace/8.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1288930393
Short name T940
Test name
Test status
Simulation time 63483189 ps
CPU time 1.1 seconds
Started Jul 29 04:33:19 PM PDT 24
Finished Jul 29 04:33:20 PM PDT 24
Peak memory 196488 kb
Host smart-33ab0759-4e5e-4c24-9a1c-db238e404e7a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288930393 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1288930393
Directory /workspace/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.177168295
Short name T909
Test name
Test status
Simulation time 42447700 ps
CPU time 0.99 seconds
Started Jul 29 04:33:14 PM PDT 24
Finished Jul 29 04:33:15 PM PDT 24
Peak memory 196348 kb
Host smart-6d2ec6f3-150f-42ef-a231-f67e014fd6f6
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=177168295 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_en_cdc_prim.177168295
Directory /workspace/9.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.650735098
Short name T908
Test name
Test status
Simulation time 40557444 ps
CPU time 1.03 seconds
Started Jul 29 04:33:30 PM PDT 24
Finished Jul 29 04:33:32 PM PDT 24
Peak memory 195700 kb
Host smart-f5ef2f83-f7e8-4a2f-95d5-b837fee65473
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650735098 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.650735098
Directory /workspace/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest
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