Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	32	0	32	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	128	0	128	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	3910022	1			T19	199		T20	827		T21	52
all_pins[1]	3910022	1			T19	199		T20	827		T21	52
all_pins[2]	3910022	1			T19	199		T20	827		T21	52
all_pins[3]	3910022	1			T19	199		T20	827		T21	52
all_pins[4]	3910022	1			T19	199		T20	827		T21	52
all_pins[5]	3910022	1			T19	199		T20	827		T21	52
all_pins[6]	3910022	1			T19	199		T20	827		T21	52
all_pins[7]	3910022	1			T19	199		T20	827		T21	52
all_pins[8]	3910022	1			T19	199		T20	827		T21	52
all_pins[9]	3910022	1			T19	199		T20	827		T21	52
all_pins[10]	3910022	1			T19	199		T20	827		T21	52
all_pins[11]	3910022	1			T19	199		T20	827		T21	52
all_pins[12]	3910022	1			T19	199		T20	827		T21	52
all_pins[13]	3910022	1			T19	199		T20	827		T21	52
all_pins[14]	3910022	1			T19	199		T20	827		T21	52
all_pins[15]	3910022	1			T19	199		T20	827		T21	52
all_pins[16]	3910022	1			T19	199		T20	827		T21	52
all_pins[17]	3910022	1			T19	199		T20	827		T21	52
all_pins[18]	3910022	1			T19	199		T20	827		T21	52
all_pins[19]	3910022	1			T19	199		T20	827		T21	52
all_pins[20]	3910022	1			T19	199		T20	827		T21	52
all_pins[21]	3910022	1			T19	199		T20	827		T21	52
all_pins[22]	3910022	1			T19	199		T20	827		T21	52
all_pins[23]	3910022	1			T19	199		T20	827		T21	52
all_pins[24]	3910022	1			T19	199		T20	827		T21	52
all_pins[25]	3910022	1			T19	199		T20	827		T21	52
all_pins[26]	3910022	1			T19	199		T20	827		T21	52
all_pins[27]	3910022	1			T19	199		T20	827		T21	52
all_pins[28]	3910022	1			T19	199		T20	827		T21	52
all_pins[29]	3910022	1			T19	199		T20	827		T21	52
all_pins[30]	3910022	1			T19	199		T20	827		T21	52
all_pins[31]	3910022	1			T19	199		T20	827		T21	52

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	77768772	1			T19	3849		T20	16346		T21	855
values[0x1]	47351932	1			T19	2519		T20	10118		T21	809
transitions[0x0=>0x1]	28387163	1			T19	1452		T20	6021		T21	402
transitions[0x1=>0x0]	28387000	1			T19	1452		T20	6021		T21	402

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2428743	1			T19	120		T20	512		T21	28
all_pins[0]	values[0x1]	1481279	1			T19	79		T20	315		T21	24
all_pins[0]	transitions[0x0=>0x1]	915592	1			T19	45		T20	182		T21	13
all_pins[0]	transitions[0x1=>0x0]	912131	1			T19	31		T20	203		T21	12
all_pins[1]	values[0x0]	2425979	1			T19	93		T20	572		T21	21
all_pins[1]	values[0x1]	1484043	1			T19	106		T20	255		T21	31
all_pins[1]	transitions[0x0=>0x1]	885329	1			T19	63		T20	148		T21	19
all_pins[1]	transitions[0x1=>0x0]	882565	1			T19	36		T20	208		T21	12
all_pins[2]	values[0x0]	2435791	1			T19	101		T20	466		T21	30
all_pins[2]	values[0x1]	1474231	1			T19	98		T20	361		T21	22
all_pins[2]	transitions[0x0=>0x1]	880490	1			T19	37		T20	202		T21	7
all_pins[2]	transitions[0x1=>0x0]	890302	1			T19	45		T20	96		T21	16
all_pins[3]	values[0x0]	2430962	1			T19	125		T20	474		T21	31
all_pins[3]	values[0x1]	1479060	1			T19	74		T20	353		T21	21
all_pins[3]	transitions[0x0=>0x1]	889677	1			T19	24		T20	203		T21	9
all_pins[3]	transitions[0x1=>0x0]	884848	1			T19	48		T20	211		T21	10
all_pins[4]	values[0x0]	2430585	1			T19	126		T20	534		T21	23
all_pins[4]	values[0x1]	1479437	1			T19	73		T20	293		T21	29
all_pins[4]	transitions[0x0=>0x1]	887914	1			T19	39		T20	164		T21	19
all_pins[4]	transitions[0x1=>0x0]	887537	1			T19	40		T20	224		T21	11
all_pins[5]	values[0x0]	2433602	1			T19	90		T20	545		T21	21
all_pins[5]	values[0x1]	1476420	1			T19	109		T20	282		T21	31
all_pins[5]	transitions[0x0=>0x1]	883795	1			T19	67		T20	159		T21	14
all_pins[5]	transitions[0x1=>0x0]	886812	1			T19	31		T20	170		T21	12
all_pins[6]	values[0x0]	2428188	1			T19	119		T20	482		T21	29
all_pins[6]	values[0x1]	1481834	1			T19	80		T20	345		T21	23
all_pins[6]	transitions[0x0=>0x1]	888262	1			T19	39		T20	230		T21	8
all_pins[6]	transitions[0x1=>0x0]	882848	1			T19	68		T20	167		T21	16
all_pins[7]	values[0x0]	2431545	1			T19	126		T20	532		T21	26
all_pins[7]	values[0x1]	1478477	1			T19	73		T20	295		T21	26
all_pins[7]	transitions[0x0=>0x1]	885845	1			T19	59		T20	138		T21	12
all_pins[7]	transitions[0x1=>0x0]	889202	1			T19	66		T20	188		T21	9
all_pins[8]	values[0x0]	2431403	1			T19	106		T20	520		T21	18
all_pins[8]	values[0x1]	1478619	1			T19	93		T20	307		T21	34
all_pins[8]	transitions[0x0=>0x1]	885042	1			T19	56		T20	179		T21	12
all_pins[8]	transitions[0x1=>0x0]	884900	1			T19	36		T20	167		T21	4
all_pins[9]	values[0x0]	2430979	1			T19	105		T20	511		T21	29
all_pins[9]	values[0x1]	1479043	1			T19	94		T20	316		T21	23
all_pins[9]	transitions[0x0=>0x1]	885260	1			T19	55		T20	191		T21	6
all_pins[9]	transitions[0x1=>0x0]	884836	1			T19	54		T20	182		T21	17
all_pins[10]	values[0x0]	2425032	1			T19	151		T20	493		T21	22
all_pins[10]	values[0x1]	1484990	1			T19	48		T20	334		T21	30
all_pins[10]	transitions[0x0=>0x1]	888574	1			T19	27		T20	202		T21	14
all_pins[10]	transitions[0x1=>0x0]	882627	1			T19	73		T20	184		T21	7
all_pins[11]	values[0x0]	2432716	1			T19	157		T20	512		T21	28
all_pins[11]	values[0x1]	1477306	1			T19	42		T20	315		T21	24
all_pins[11]	transitions[0x0=>0x1]	881009	1			T19	24		T20	182		T21	13
all_pins[11]	transitions[0x1=>0x0]	888693	1			T19	30		T20	201		T21	19
all_pins[12]	values[0x0]	2427466	1			T19	126		T20	522		T21	26
all_pins[12]	values[0x1]	1482556	1			T19	73		T20	305		T21	26
all_pins[12]	transitions[0x0=>0x1]	887528	1			T19	52		T20	187		T21	16
all_pins[12]	transitions[0x1=>0x0]	882278	1			T19	21		T20	197		T21	14
all_pins[13]	values[0x0]	2429468	1			T19	128		T20	485		T21	22
all_pins[13]	values[0x1]	1480554	1			T19	71		T20	342		T21	30
all_pins[13]	transitions[0x0=>0x1]	886369	1			T19	39		T20	195		T21	14
all_pins[13]	transitions[0x1=>0x0]	888371	1			T19	41		T20	158		T21	10
all_pins[14]	values[0x0]	2432569	1			T19	135		T20	523		T21	30
all_pins[14]	values[0x1]	1477453	1			T19	64		T20	304		T21	22
all_pins[14]	transitions[0x0=>0x1]	882908	1			T19	44		T20	171		T21	7
all_pins[14]	transitions[0x1=>0x0]	886009	1			T19	51		T20	209		T21	15
all_pins[15]	values[0x0]	2430190	1			T19	128		T20	502		T21	32
all_pins[15]	values[0x1]	1479832	1			T19	71		T20	325		T21	20
all_pins[15]	transitions[0x0=>0x1]	886858	1			T19	50		T20	190		T21	14
all_pins[15]	transitions[0x1=>0x0]	884479	1			T19	43		T20	169		T21	16
all_pins[16]	values[0x0]	2434834	1			T19	92		T20	504		T21	27
all_pins[16]	values[0x1]	1475188	1			T19	107		T20	323		T21	25
all_pins[16]	transitions[0x0=>0x1]	883664	1			T19	74		T20	186		T21	15
all_pins[16]	transitions[0x1=>0x0]	888308	1			T19	38		T20	188		T21	10
all_pins[17]	values[0x0]	2425176	1			T19	91		T20	546		T21	25
all_pins[17]	values[0x1]	1484846	1			T19	108		T20	281		T21	27
all_pins[17]	transitions[0x0=>0x1]	890095	1			T19	47		T20	157		T21	12
all_pins[17]	transitions[0x1=>0x0]	880437	1			T19	46		T20	199		T21	10
all_pins[18]	values[0x0]	2425746	1			T19	109		T20	467		T21	25
all_pins[18]	values[0x1]	1484276	1			T19	90		T20	360		T21	27
all_pins[18]	transitions[0x0=>0x1]	887539	1			T19	36		T20	239		T21	10
all_pins[18]	transitions[0x1=>0x0]	888109	1			T19	54		T20	160		T21	10
all_pins[19]	values[0x0]	2434468	1			T19	119		T20	526		T21	30
all_pins[19]	values[0x1]	1475554	1			T19	80		T20	301		T21	22
all_pins[19]	transitions[0x0=>0x1]	881888	1			T19	35		T20	170		T21	11
all_pins[19]	transitions[0x1=>0x0]	890610	1			T19	45		T20	229		T21	16
all_pins[20]	values[0x0]	2432852	1			T19	140		T20	503		T21	24
all_pins[20]	values[0x1]	1477170	1			T19	59		T20	324		T21	28
all_pins[20]	transitions[0x0=>0x1]	883505	1			T19	31		T20	195		T21	16
all_pins[20]	transitions[0x1=>0x0]	881889	1			T19	52		T20	172		T21	10
all_pins[21]	values[0x0]	2433634	1			T19	124		T20	569		T21	29
all_pins[21]	values[0x1]	1476388	1			T19	75		T20	258		T21	23
all_pins[21]	transitions[0x0=>0x1]	882958	1			T19	56		T20	140		T21	13
all_pins[21]	transitions[0x1=>0x0]	883740	1			T19	40		T20	206		T21	18
all_pins[22]	values[0x0]	2421614	1			T19	101		T20	514		T21	25
all_pins[22]	values[0x1]	1488408	1			T19	98		T20	313		T21	27
all_pins[22]	transitions[0x0=>0x1]	894707	1			T19	56		T20	227		T21	14
all_pins[22]	transitions[0x1=>0x0]	882687	1			T19	33		T20	172		T21	10
all_pins[23]	values[0x0]	2431693	1			T19	131		T20	510		T21	31
all_pins[23]	values[0x1]	1478329	1			T19	68		T20	317		T21	21
all_pins[23]	transitions[0x0=>0x1]	881407	1			T19	41		T20	213		T21	9
all_pins[23]	transitions[0x1=>0x0]	891486	1			T19	71		T20	209		T21	15
all_pins[24]	values[0x0]	2435765	1			T19	97		T20	505		T21	25
all_pins[24]	values[0x1]	1474257	1			T19	102		T20	322		T21	27
all_pins[24]	transitions[0x0=>0x1]	882542	1			T19	60		T20	191		T21	17
all_pins[24]	transitions[0x1=>0x0]	886614	1			T19	26		T20	186		T21	11
all_pins[25]	values[0x0]	2433379	1			T19	147		T20	488		T21	26
all_pins[25]	values[0x1]	1476643	1			T19	52		T20	339		T21	26
all_pins[25]	transitions[0x0=>0x1]	890127	1			T19	30		T20	193		T21	10
all_pins[25]	transitions[0x1=>0x0]	887741	1			T19	80		T20	176		T21	11
all_pins[26]	values[0x0]	2434097	1			T19	131		T20	522		T21	28
all_pins[26]	values[0x1]	1475925	1			T19	68		T20	305		T21	24
all_pins[26]	transitions[0x0=>0x1]	887673	1			T19	51		T20	182		T21	13
all_pins[26]	transitions[0x1=>0x0]	888391	1			T19	35		T20	216		T21	15
all_pins[27]	values[0x0]	2432967	1			T19	126		T20	490		T21	32
all_pins[27]	values[0x1]	1477055	1			T19	73		T20	337		T21	20
all_pins[27]	transitions[0x0=>0x1]	887026	1			T19	41		T20	216		T21	9
all_pins[27]	transitions[0x1=>0x0]	885896	1			T19	36		T20	184		T21	13
all_pins[28]	values[0x0]	2426260	1			T19	128		T20	544		T21	24
all_pins[28]	values[0x1]	1483762	1			T19	71		T20	283		T21	28
all_pins[28]	transitions[0x0=>0x1]	889549	1			T19	38		T20	150		T21	16
all_pins[28]	transitions[0x1=>0x0]	882842	1			T19	40		T20	204		T21	8
all_pins[29]	values[0x0]	2424619	1			T19	116		T20	508		T21	27
all_pins[29]	values[0x1]	1485403	1			T19	83		T20	319		T21	25
all_pins[29]	transitions[0x0=>0x1]	890797	1			T19	54		T20	216		T21	12
all_pins[29]	transitions[0x1=>0x0]	889156	1			T19	42		T20	180		T21	15
all_pins[30]	values[0x0]	2424409	1			T19	127		T20	474		T21	32
all_pins[30]	values[0x1]	1485613	1			T19	72		T20	353		T21	20
all_pins[30]	transitions[0x0=>0x1]	887921	1			T19	42		T20	232		T21	12
all_pins[30]	transitions[0x1=>0x0]	887711	1			T19	53		T20	198		T21	17
all_pins[31]	values[0x0]	2432041	1			T19	134		T20	491		T21	29
all_pins[31]	values[0x1]	1477981	1			T19	65		T20	336		T21	23
all_pins[31]	transitions[0x0=>0x1]	885313	1			T19	40		T20	191		T21	16
all_pins[31]	transitions[0x1=>0x0]	892945	1			T19	47		T20	208		T21	13