Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
data_oe	2	0	2	100.00	100	1	1	2
data_out	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_all	192	0	192	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	13192605	1			T19	175		T20	2227		T21	946
bins_for_gpio_bits[1]	13192605	1			T19	175		T20	2227		T21	946
bins_for_gpio_bits[2]	13192605	1			T19	175		T20	2227		T21	946
bins_for_gpio_bits[3]	13192605	1			T19	175		T20	2227		T21	946
bins_for_gpio_bits[4]	13192605	1			T19	175		T20	2227		T21	946
bins_for_gpio_bits[5]	13192605	1			T19	175		T20	2227		T21	946
bins_for_gpio_bits[6]	13192605	1			T19	175		T20	2227		T21	946
bins_for_gpio_bits[7]	13192605	1			T19	175		T20	2227		T21	946
bins_for_gpio_bits[8]	13192605	1			T19	175		T20	2227		T21	946
bins_for_gpio_bits[9]	13192605	1			T19	175		T20	2227		T21	946
bins_for_gpio_bits[10]	13192605	1			T19	175		T20	2227		T21	946
bins_for_gpio_bits[11]	13192605	1			T19	175		T20	2227		T21	946
bins_for_gpio_bits[12]	13192605	1			T19	175		T20	2227		T21	946
bins_for_gpio_bits[13]	13192605	1			T19	175		T20	2227		T21	946
bins_for_gpio_bits[14]	13192605	1			T19	175		T20	2227		T21	946
bins_for_gpio_bits[15]	13192605	1			T19	175		T20	2227		T21	946
bins_for_gpio_bits[16]	13192605	1			T19	175		T20	2227		T21	946
bins_for_gpio_bits[17]	13192605	1			T19	175		T20	2227		T21	946
bins_for_gpio_bits[18]	13192605	1			T19	175		T20	2227		T21	946
bins_for_gpio_bits[19]	13192605	1			T19	175		T20	2227		T21	946
bins_for_gpio_bits[20]	13192605	1			T19	175		T20	2227		T21	946
bins_for_gpio_bits[21]	13192605	1			T19	175		T20	2227		T21	946
bins_for_gpio_bits[22]	13192605	1			T19	175		T20	2227		T21	946
bins_for_gpio_bits[23]	13192605	1			T19	175		T20	2227		T21	946
bins_for_gpio_bits[24]	13192605	1			T19	175		T20	2227		T21	946
bins_for_gpio_bits[25]	13192605	1			T19	175		T20	2227		T21	946
bins_for_gpio_bits[26]	13192605	1			T19	175		T20	2227		T21	946
bins_for_gpio_bits[27]	13192605	1			T19	175		T20	2227		T21	946
bins_for_gpio_bits[28]	13192605	1			T19	175		T20	2227		T21	946
bins_for_gpio_bits[29]	13192605	1			T19	175		T20	2227		T21	946
bins_for_gpio_bits[30]	13192605	1			T19	175		T20	2227		T21	946
bins_for_gpio_bits[31]	13192605	1			T19	175		T20	2227		T21	946

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

249801340

1

T19

2699

T20

54764

T21

15346

auto[1]

172362020

1

T19

2901

T20

16500

T21

14926

---

Summary for Variable data_oe

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_oe

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

340968507

1

T19

5600

T20

41080

T21

30272

auto[1]

81194853

1

T20

30184

T22

461

T24

3314

---

Summary for Variable data_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

316918814

1

T19

5600

T20

35082

T21

30272

auto[1]

105244546

1

T20

36182

T22

1508

T24

6580

---

Summary for Cross cp_cross_all

Samples crossed: cp_pin data_out data_oe data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_all

Bins

cp_pin	data_out	data_oe	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[0]	4928988	1			T19	87		T20	499		T21	453
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[1]	3695924	1			T19	88		T20	19		T21	493
bins_for_gpio_bits[0]	auto[0]	auto[1]	auto[0]	1274360	1			T20	433		T22	7		T24	46
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[0]	1603655	1			T20	713		T22	13		T24	15
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[1]	422617	1			T20	26		T22	8		T24	83
bins_for_gpio_bits[0]	auto[1]	auto[1]	auto[1]	1267061	1			T20	537		T22	3		T24	66
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[0]	4930602	1			T19	78		T20	520		T21	456
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[1]	3695298	1			T19	97		T20	18		T21	490
bins_for_gpio_bits[1]	auto[0]	auto[1]	auto[0]	1278595	1			T20	518		T22	12		T24	73
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[0]	1601754	1			T20	679		T22	41		T24	22
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[1]	423169	1			T20	15		T22	22		T24	113
bins_for_gpio_bits[1]	auto[1]	auto[1]	auto[1]	1263187	1			T20	477		T22	11		T24	28
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[0]	4921064	1			T19	85		T20	668		T21	504
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[1]	3705912	1			T19	90		T20	23		T21	442
bins_for_gpio_bits[2]	auto[0]	auto[1]	auto[0]	1276540	1			T20	541		T22	6		T24	55
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[0]	1603899	1			T20	614		T22	26		T24	21
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[1]	422938	1			T20	22		T22	20		T24	114
bins_for_gpio_bits[2]	auto[1]	auto[1]	auto[1]	1262252	1			T20	359		T22	8		T24	94
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[0]	4923958	1			T19	95		T20	580		T21	529
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[1]	3704948	1			T19	80		T20	22		T21	417
bins_for_gpio_bits[3]	auto[0]	auto[1]	auto[0]	1273314	1			T20	439		T22	12		T24	63
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[0]	1602738	1			T20	696		T22	25		T24	25
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[1]	422198	1			T20	33		T22	13		T24	163
bins_for_gpio_bits[3]	auto[1]	auto[1]	auto[1]	1265449	1			T20	457		T22	3		T24	39
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[0]	4929555	1			T19	72		T20	558		T21	483
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[1]	3702410	1			T19	103		T20	21		T21	463
bins_for_gpio_bits[4]	auto[0]	auto[1]	auto[0]	1278487	1			T20	474		T22	11		T24	54
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[0]	1600995	1			T20	654		T22	37		T24	17
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[1]	417062	1			T20	33		T22	20		T24	124
bins_for_gpio_bits[4]	auto[1]	auto[1]	auto[1]	1264096	1			T20	487		T22	9		T24	40
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[0]	4918777	1			T19	92		T20	651		T21	482
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[1]	3702440	1			T19	83		T20	26		T21	464
bins_for_gpio_bits[5]	auto[0]	auto[1]	auto[0]	1276367	1			T20	507		T22	6		T24	25
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[0]	1603819	1			T20	547		T22	9		T24	14
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[1]	424616	1			T20	19		T22	21		T24	170
bins_for_gpio_bits[5]	auto[1]	auto[1]	auto[1]	1266586	1			T20	477		T22	15		T24	52
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[0]	4929734	1			T19	84		T20	570		T21	470
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[1]	3699878	1			T19	91		T20	12		T21	476
bins_for_gpio_bits[6]	auto[0]	auto[1]	auto[0]	1279066	1			T20	468		T22	6		T24	45
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[0]	1604364	1			T20	647		T22	13		T24	26
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[1]	420275	1			T20	24		T22	12		T24	131
bins_for_gpio_bits[6]	auto[1]	auto[1]	auto[1]	1259288	1			T20	506		T22	3		T24	91
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[0]	4921398	1			T19	96		T20	653		T21	534
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[1]	3704060	1			T19	79		T20	31		T21	412
bins_for_gpio_bits[7]	auto[0]	auto[1]	auto[0]	1280473	1			T20	479		T22	8		T24	71
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[0]	1604216	1			T20	545		T22	30		T24	17
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[1]	421778	1			T20	17		T22	4		T24	119
bins_for_gpio_bits[7]	auto[1]	auto[1]	auto[1]	1260680	1			T20	502		T22	2		T24	58
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[0]	4918217	1			T19	76		T20	642		T21	486
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[1]	3705329	1			T19	99		T20	30		T21	460
bins_for_gpio_bits[8]	auto[0]	auto[1]	auto[0]	1277977	1			T20	480		T24	48		T25	46439
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[0]	1605531	1			T20	630		T22	15		T24	15
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[1]	421592	1			T20	21		T22	8		T24	136
bins_for_gpio_bits[8]	auto[1]	auto[1]	auto[1]	1263959	1			T20	424		T22	15		T24	50
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[0]	4930564	1			T19	81		T20	600		T21	420
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[1]	3697282	1			T19	94		T20	9		T21	526
bins_for_gpio_bits[9]	auto[0]	auto[1]	auto[0]	1277108	1			T20	397		T24	76		T25	45560
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[0]	1599208	1			T20	617		T22	31		T24	17
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[1]	421847	1			T20	32		T22	25		T24	134
bins_for_gpio_bits[9]	auto[1]	auto[1]	auto[1]	1266596	1			T20	572		T22	21		T24	50
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[0]	4924997	1			T19	95		T20	522		T21	477
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[1]	3700645	1			T19	80		T20	19		T21	469
bins_for_gpio_bits[10]	auto[0]	auto[1]	auto[0]	1277309	1			T20	526		T22	13		T24	66
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[0]	1603586	1			T20	692		T22	33		T24	13
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[1]	421615	1			T20	12		T22	15		T24	78
bins_for_gpio_bits[10]	auto[1]	auto[1]	auto[1]	1264453	1			T20	456		T22	14		T24	69
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[0]	4925445	1			T19	82		T20	500		T21	508
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[1]	3693816	1			T19	93		T20	22		T21	438
bins_for_gpio_bits[11]	auto[0]	auto[1]	auto[0]	1277015	1			T20	476		T22	13		T24	53
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[0]	1601192	1			T20	684		T22	18		T24	22
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[1]	423629	1			T20	30		T22	18		T24	151
bins_for_gpio_bits[11]	auto[1]	auto[1]	auto[1]	1271508	1			T20	515		T22	9		T24	48
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[0]	4930302	1			T19	69		T20	540		T21	485
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[1]	3700754	1			T19	106		T20	26		T21	461
bins_for_gpio_bits[12]	auto[0]	auto[1]	auto[0]	1279660	1			T20	462		T22	19		T24	73
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[0]	1599072	1			T20	718		T22	15		T24	22
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[1]	419179	1			T20	37		T22	12		T24	109
bins_for_gpio_bits[12]	auto[1]	auto[1]	auto[1]	1263638	1			T20	444		T22	7		T24	56
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[0]	4926643	1			T19	82		T20	575		T21	568
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[1]	3699326	1			T19	93		T20	23		T21	378
bins_for_gpio_bits[13]	auto[0]	auto[1]	auto[0]	1275314	1			T20	461		T22	7		T24	43
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[0]	1604467	1			T20	631		T22	12		T24	16
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[1]	422162	1			T20	23		T22	18		T24	146
bins_for_gpio_bits[13]	auto[1]	auto[1]	auto[1]	1264693	1			T20	514		T22	22		T24	25
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[0]	4928337	1			T19	97		T20	734		T21	488
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[1]	3702994	1			T19	78		T20	33		T21	458
bins_for_gpio_bits[14]	auto[0]	auto[1]	auto[0]	1277641	1			T20	549		T22	6		T24	27
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[0]	1599677	1			T20	446		T22	34		T24	14
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[1]	422036	1			T20	16		T22	10		T24	118
bins_for_gpio_bits[14]	auto[1]	auto[1]	auto[1]	1261920	1			T20	449		T22	15		T24	63
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[0]	4926699	1			T19	73		T20	564		T21	472
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[1]	3697422	1			T19	102		T20	38		T21	474
bins_for_gpio_bits[15]	auto[0]	auto[1]	auto[0]	1277520	1			T20	454		T22	8		T24	37
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[0]	1602984	1			T20	689		T22	27		T24	14
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[1]	422905	1			T20	25		T22	13		T24	171
bins_for_gpio_bits[15]	auto[1]	auto[1]	auto[1]	1265075	1			T20	457		T22	5		T24	54
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[0]	4935176	1			T19	88		T20	571		T21	509
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[1]	3695980	1			T19	87		T20	17		T21	437
bins_for_gpio_bits[16]	auto[0]	auto[1]	auto[0]	1276030	1			T20	485		T22	6		T24	50
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[0]	1600975	1			T20	601		T22	24		T24	7
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[1]	420963	1			T20	28		T22	10		T24	121
bins_for_gpio_bits[16]	auto[1]	auto[1]	auto[1]	1263481	1			T20	525		T22	7		T24	39
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[0]	4929053	1			T19	93		T20	561		T21	455
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[1]	3702147	1			T19	82		T20	22		T21	491
bins_for_gpio_bits[17]	auto[0]	auto[1]	auto[0]	1272052	1			T20	547		T22	1		T24	40
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[0]	1610054	1			T20	577		T22	21		T24	23
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[1]	420989	1			T20	28		T22	23		T24	176
bins_for_gpio_bits[17]	auto[1]	auto[1]	auto[1]	1258310	1			T20	492		T22	12		T24	37
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[0]	4931830	1			T19	80		T20	516		T21	430
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[1]	3703087	1			T19	95		T20	8		T21	516
bins_for_gpio_bits[18]	auto[0]	auto[1]	auto[0]	1271974	1			T20	475		T22	2		T24	44
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[0]	1605210	1			T20	782		T22	49		T24	22
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[1]	420512	1			T20	42		T22	15		T24	144
bins_for_gpio_bits[18]	auto[1]	auto[1]	auto[1]	1259992	1			T20	404		T22	7		T24	85
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[0]	4933974	1			T19	83		T20	545		T21	455
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[1]	3691975	1			T19	92		T20	27		T21	491
bins_for_gpio_bits[19]	auto[0]	auto[1]	auto[0]	1270955	1			T20	596		T22	3		T24	68
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[0]	1612930	1			T20	619		T22	4		T24	14
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[1]	424243	1			T20	24		T22	22		T24	114
bins_for_gpio_bits[19]	auto[1]	auto[1]	auto[1]	1258528	1			T20	416		T22	12		T24	45
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[0]	4927451	1			T19	88		T20	643		T21	488
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[1]	3702891	1			T19	87		T20	18		T21	458
bins_for_gpio_bits[20]	auto[0]	auto[1]	auto[0]	1271534	1			T20	492		T24	54		T25	45026
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[0]	1606285	1			T20	578		T22	21		T24	20
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[1]	422552	1			T20	16		T22	30		T24	116
bins_for_gpio_bits[20]	auto[1]	auto[1]	auto[1]	1261892	1			T20	480		T22	16		T24	68
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[0]	4921504	1			T19	84		T20	731		T21	540
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[1]	3710757	1			T19	91		T20	32		T21	406
bins_for_gpio_bits[21]	auto[0]	auto[1]	auto[0]	1272838	1			T20	421		T24	33		T25	45166
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[0]	1607901	1			T20	649		T22	21		T24	20
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[1]	422181	1			T20	11		T22	13		T24	140
bins_for_gpio_bits[21]	auto[1]	auto[1]	auto[1]	1257424	1			T20	383		T22	6		T24	61
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[0]	4912502	1			T19	78		T20	871		T21	440
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[1]	3712021	1			T19	97		T20	31		T21	506
bins_for_gpio_bits[22]	auto[0]	auto[1]	auto[0]	1274181	1			T20	437		T22	6		T24	58
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[0]	1606915	1			T20	528		T22	12		T24	18
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[1]	421321	1			T20	23		T22	6		T24	130
bins_for_gpio_bits[22]	auto[1]	auto[1]	auto[1]	1265665	1			T20	337		T22	3		T24	55
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[0]	4920649	1			T19	82		T20	669		T21	453
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[1]	3710480	1			T19	93		T20	20		T21	493
bins_for_gpio_bits[23]	auto[0]	auto[1]	auto[0]	1270614	1			T20	416		T22	3		T24	57
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[0]	1607561	1			T20	594		T22	22		T24	10
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[1]	421329	1			T20	27		T22	12		T24	101
bins_for_gpio_bits[23]	auto[1]	auto[1]	auto[1]	1261972	1			T20	501		T22	1		T24	46
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[0]	4922626	1			T19	98		T20	619		T21	502
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[1]	3707136	1			T19	77		T20	19		T21	444
bins_for_gpio_bits[24]	auto[0]	auto[1]	auto[0]	1275789	1			T20	362		T22	5		T24	58
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[0]	1604589	1			T20	742		T22	28		T24	12
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[1]	424390	1			T20	35		T22	5		T24	141
bins_for_gpio_bits[24]	auto[1]	auto[1]	auto[1]	1258075	1			T20	450		T24	30		T25	45286
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[0]	4928524	1			T19	78		T20	677		T21	497
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[1]	3699680	1			T19	97		T20	39		T21	449
bins_for_gpio_bits[25]	auto[0]	auto[1]	auto[0]	1274772	1			T20	529		T22	8		T24	36
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[0]	1604143	1			T20	607		T22	35		T24	9
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[1]	422545	1			T20	8		T22	17		T24	153
bins_for_gpio_bits[25]	auto[1]	auto[1]	auto[1]	1262941	1			T20	367		T22	12		T24	39
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[0]	4926876	1			T19	87		T20	564		T21	416
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[1]	3703002	1			T19	88		T20	23		T21	530
bins_for_gpio_bits[26]	auto[0]	auto[1]	auto[0]	1276033	1			T20	517		T22	5		T24	44
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[0]	1604672	1			T20	589		T22	18		T24	24
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[1]	423163	1			T20	25		T22	17		T24	154
bins_for_gpio_bits[26]	auto[1]	auto[1]	auto[1]	1258859	1			T20	509		T22	19		T24	44
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[0]	4932966	1			T19	84		T20	567		T21	503
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[1]	3702903	1			T19	91		T20	12		T21	443
bins_for_gpio_bits[27]	auto[0]	auto[1]	auto[0]	1273449	1			T20	447		T24	45		T25	45762
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[0]	1605784	1			T20	640		T22	28		T24	21
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[1]	422750	1			T20	36		T22	11		T24	81
bins_for_gpio_bits[27]	auto[1]	auto[1]	auto[1]	1254753	1			T20	525		T22	5		T24	70
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[0]	4923902	1			T19	76		T20	625		T21	463
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[1]	3707282	1			T19	99		T20	37		T21	483
bins_for_gpio_bits[28]	auto[0]	auto[1]	auto[0]	1274100	1			T20	524		T22	1		T24	18
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[0]	1605673	1			T20	527		T22	28		T24	21
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[1]	422555	1			T20	18		T22	7		T24	188
bins_for_gpio_bits[28]	auto[1]	auto[1]	auto[1]	1259093	1			T20	496		T22	4		T24	61
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[0]	4932451	1			T19	85		T20	555		T21	501
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[1]	3704588	1			T19	90		T20	9		T21	445
bins_for_gpio_bits[29]	auto[0]	auto[1]	auto[0]	1273416	1			T20	407		T22	2		T24	43
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[0]	1601638	1			T20	741		T22	29		T24	19
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[1]	423939	1			T20	29		T22	17		T24	196
bins_for_gpio_bits[29]	auto[1]	auto[1]	auto[1]	1256573	1			T20	486		T22	9		T24	30
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[0]	4932097	1			T19	87		T20	479		T21	404
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[1]	3697290	1			T19	88		T20	23		T21	542
bins_for_gpio_bits[30]	auto[0]	auto[1]	auto[0]	1266764	1			T20	436		T22	4		T24	47
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[0]	1612171	1			T20	712		T22	14		T24	18
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[1]	422909	1			T20	13		T22	17		T24	104
bins_for_gpio_bits[30]	auto[1]	auto[1]	auto[1]	1261374	1			T20	564		T22	3		T24	57
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[0]	4926455	1			T19	84		T20	601		T21	475
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[1]	3702419	1			T19	91		T20	20		T21	471
bins_for_gpio_bits[31]	auto[0]	auto[1]	auto[0]	1272175	1			T20	428		T22	2		T24	26
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[0]	1606944	1			T20	723		T22	20		T24	17
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[1]	422554	1			T20	22		T22	15		T24	158
bins_for_gpio_bits[31]	auto[1]	auto[1]	auto[1]	1262058	1			T20	433		T22	1		T24	88

User Defined Cross Bins for cp_cross_all

Excluded/Illegal bins

NAME	COUNT	STATUS
data_oe_1_data_out_0_data_in_1	0	Illegal
data_oe_1_data_out_1_data_in_0	0	Illegal