Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
gpio_value	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_pins_data_in	128	0	128	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	13192605	1			T19	175		T20	2227		T21	946
bins_for_gpio_bits[1]	13192605	1			T19	175		T20	2227		T21	946
bins_for_gpio_bits[2]	13192605	1			T19	175		T20	2227		T21	946
bins_for_gpio_bits[3]	13192605	1			T19	175		T20	2227		T21	946
bins_for_gpio_bits[4]	13192605	1			T19	175		T20	2227		T21	946
bins_for_gpio_bits[5]	13192605	1			T19	175		T20	2227		T21	946
bins_for_gpio_bits[6]	13192605	1			T19	175		T20	2227		T21	946
bins_for_gpio_bits[7]	13192605	1			T19	175		T20	2227		T21	946
bins_for_gpio_bits[8]	13192605	1			T19	175		T20	2227		T21	946
bins_for_gpio_bits[9]	13192605	1			T19	175		T20	2227		T21	946
bins_for_gpio_bits[10]	13192605	1			T19	175		T20	2227		T21	946
bins_for_gpio_bits[11]	13192605	1			T19	175		T20	2227		T21	946
bins_for_gpio_bits[12]	13192605	1			T19	175		T20	2227		T21	946
bins_for_gpio_bits[13]	13192605	1			T19	175		T20	2227		T21	946
bins_for_gpio_bits[14]	13192605	1			T19	175		T20	2227		T21	946
bins_for_gpio_bits[15]	13192605	1			T19	175		T20	2227		T21	946
bins_for_gpio_bits[16]	13192605	1			T19	175		T20	2227		T21	946
bins_for_gpio_bits[17]	13192605	1			T19	175		T20	2227		T21	946
bins_for_gpio_bits[18]	13192605	1			T19	175		T20	2227		T21	946
bins_for_gpio_bits[19]	13192605	1			T19	175		T20	2227		T21	946
bins_for_gpio_bits[20]	13192605	1			T19	175		T20	2227		T21	946
bins_for_gpio_bits[21]	13192605	1			T19	175		T20	2227		T21	946
bins_for_gpio_bits[22]	13192605	1			T19	175		T20	2227		T21	946
bins_for_gpio_bits[23]	13192605	1			T19	175		T20	2227		T21	946
bins_for_gpio_bits[24]	13192605	1			T19	175		T20	2227		T21	946
bins_for_gpio_bits[25]	13192605	1			T19	175		T20	2227		T21	946
bins_for_gpio_bits[26]	13192605	1			T19	175		T20	2227		T21	946
bins_for_gpio_bits[27]	13192605	1			T19	175		T20	2227		T21	946
bins_for_gpio_bits[28]	13192605	1			T19	175		T20	2227		T21	946
bins_for_gpio_bits[29]	13192605	1			T19	175		T20	2227		T21	946
bins_for_gpio_bits[30]	13192605	1			T19	175		T20	2227		T21	946
bins_for_gpio_bits[31]	13192605	1			T19	175		T20	2227		T21	946

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

249801340

1

T19

2699

T20

54764

T21

15346

auto[1]

172362020

1

T19

2901

T20

16500

T21

14926

---

Summary for Variable gpio_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for gpio_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

249794322

1

T19

2699

T20

54754

T21

15346

auto[1]

172369038

1

T19

2901

T20

16510

T21

14926

---

Summary for Cross cp_cross_pins_data_in

Samples crossed: cp_pin gpio_value data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_cross_pins_data_in

Bins

cp_pin	gpio_value	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	7579653	1			T19	87		T20	1571		T21	453
bins_for_gpio_bits[0]	auto[0]	auto[1]	227085	1			T20	74		T24	9		T25	8236
bins_for_gpio_bits[0]	auto[1]	auto[0]	227350	1			T20	74		T24	9		T25	8236
bins_for_gpio_bits[0]	auto[1]	auto[1]	5158517	1			T19	88		T20	508		T21	493
bins_for_gpio_bits[1]	auto[0]	auto[0]	7584667	1			T19	78		T20	1646		T21	456
bins_for_gpio_bits[1]	auto[0]	auto[1]	226052	1			T20	71		T24	11		T25	8253
bins_for_gpio_bits[1]	auto[1]	auto[0]	226284	1			T20	71		T22	1		T24	11
bins_for_gpio_bits[1]	auto[1]	auto[1]	5155602	1			T19	97		T20	439		T21	490
bins_for_gpio_bits[2]	auto[0]	auto[0]	7574829	1			T19	85		T20	1769		T21	504
bins_for_gpio_bits[2]	auto[0]	auto[1]	226429	1			T20	54		T24	12		T25	8128
bins_for_gpio_bits[2]	auto[1]	auto[0]	226674	1			T20	54		T22	1		T24	12
bins_for_gpio_bits[2]	auto[1]	auto[1]	5164673	1			T19	90		T20	350		T21	442
bins_for_gpio_bits[3]	auto[0]	auto[0]	7572896	1			T19	95		T20	1642		T21	529
bins_for_gpio_bits[3]	auto[0]	auto[1]	226917	1			T20	72		T24	9		T25	8145
bins_for_gpio_bits[3]	auto[1]	auto[0]	227114	1			T20	73		T24	9		T25	8145
bins_for_gpio_bits[3]	auto[1]	auto[1]	5165678	1			T19	80		T20	440		T21	417
bins_for_gpio_bits[4]	auto[0]	auto[0]	7582875	1			T19	72		T20	1619		T21	483
bins_for_gpio_bits[4]	auto[0]	auto[1]	225945	1			T20	67		T24	10		T25	8155
bins_for_gpio_bits[4]	auto[1]	auto[0]	226162	1			T20	67		T24	10		T25	8156
bins_for_gpio_bits[4]	auto[1]	auto[1]	5157623	1			T19	103		T20	474		T21	463
bins_for_gpio_bits[5]	auto[0]	auto[0]	7572210	1			T19	92		T20	1633		T21	482
bins_for_gpio_bits[5]	auto[0]	auto[1]	226531	1			T20	72		T22	1		T24	5
bins_for_gpio_bits[5]	auto[1]	auto[0]	226753	1			T20	72		T22	1		T24	5
bins_for_gpio_bits[5]	auto[1]	auto[1]	5167111	1			T19	83		T20	450		T21	464
bins_for_gpio_bits[6]	auto[0]	auto[0]	7586706	1			T19	84		T20	1611		T21	470
bins_for_gpio_bits[6]	auto[0]	auto[1]	226234	1			T20	74		T24	9		T25	8228
bins_for_gpio_bits[6]	auto[1]	auto[0]	226458	1			T20	74		T24	8		T25	8228
bins_for_gpio_bits[6]	auto[1]	auto[1]	5153207	1			T19	91		T20	468		T21	476
bins_for_gpio_bits[7]	auto[0]	auto[0]	7579606	1			T19	96		T20	1610		T21	534
bins_for_gpio_bits[7]	auto[0]	auto[1]	226269	1			T20	67		T24	12		T25	8110
bins_for_gpio_bits[7]	auto[1]	auto[0]	226481	1			T20	67		T24	12		T25	8111
bins_for_gpio_bits[7]	auto[1]	auto[1]	5160249	1			T19	79		T20	483		T21	412
bins_for_gpio_bits[8]	auto[0]	auto[0]	7575195	1			T19	76		T20	1693		T21	486
bins_for_gpio_bits[8]	auto[0]	auto[1]	226281	1			T20	59		T24	11		T25	8232
bins_for_gpio_bits[8]	auto[1]	auto[0]	226530	1			T20	59		T24	11		T25	8232
bins_for_gpio_bits[8]	auto[1]	auto[1]	5164599	1			T19	99		T20	416		T21	460
bins_for_gpio_bits[9]	auto[0]	auto[0]	7580841	1			T19	81		T20	1535		T21	420
bins_for_gpio_bits[9]	auto[0]	auto[1]	225859	1			T20	79		T24	11		T25	8274
bins_for_gpio_bits[9]	auto[1]	auto[0]	226039	1			T20	79		T24	11		T25	8274
bins_for_gpio_bits[9]	auto[1]	auto[1]	5159866	1			T19	94		T20	534		T21	526
bins_for_gpio_bits[10]	auto[0]	auto[0]	7579717	1			T19	95		T20	1671		T21	477
bins_for_gpio_bits[10]	auto[0]	auto[1]	225965	1			T20	69		T22	1		T24	14
bins_for_gpio_bits[10]	auto[1]	auto[0]	226175	1			T20	69		T22	1		T24	14
bins_for_gpio_bits[10]	auto[1]	auto[1]	5160748	1			T19	80		T20	418		T21	469
bins_for_gpio_bits[11]	auto[0]	auto[0]	7575860	1			T19	82		T20	1583		T21	508
bins_for_gpio_bits[11]	auto[0]	auto[1]	227535	1			T20	76		T24	10		T25	8175
bins_for_gpio_bits[11]	auto[1]	auto[0]	227792	1			T20	77		T24	10		T25	8176
bins_for_gpio_bits[11]	auto[1]	auto[1]	5161418	1			T19	93		T20	491		T21	438
bins_for_gpio_bits[12]	auto[0]	auto[0]	7581346	1			T19	69		T20	1646		T21	485
bins_for_gpio_bits[12]	auto[0]	auto[1]	227486	1			T20	73		T24	13		T25	8184
bins_for_gpio_bits[12]	auto[1]	auto[0]	227688	1			T20	74		T24	13		T25	8185
bins_for_gpio_bits[12]	auto[1]	auto[1]	5156085	1			T19	106		T20	434		T21	461
bins_for_gpio_bits[13]	auto[0]	auto[0]	7579683	1			T19	82		T20	1593		T21	568
bins_for_gpio_bits[13]	auto[0]	auto[1]	226511	1			T20	73		T24	8		T25	8171
bins_for_gpio_bits[13]	auto[1]	auto[0]	226741	1			T20	74		T24	8		T25	8172
bins_for_gpio_bits[13]	auto[1]	auto[1]	5159670	1			T19	93		T20	487		T21	378
bins_for_gpio_bits[14]	auto[0]	auto[0]	7579695	1			T19	97		T20	1663		T21	488
bins_for_gpio_bits[14]	auto[0]	auto[1]	225759	1			T20	66		T24	9		T25	8056
bins_for_gpio_bits[14]	auto[1]	auto[0]	225960	1			T20	66		T24	9		T25	8056
bins_for_gpio_bits[14]	auto[1]	auto[1]	5161191	1			T19	78		T20	432		T21	458
bins_for_gpio_bits[15]	auto[0]	auto[0]	7580472	1			T19	73		T20	1643		T21	472
bins_for_gpio_bits[15]	auto[0]	auto[1]	226513	1			T20	63		T24	7		T25	8179
bins_for_gpio_bits[15]	auto[1]	auto[0]	226731	1			T20	64		T24	7		T25	8180
bins_for_gpio_bits[15]	auto[1]	auto[1]	5158889	1			T19	102		T20	457		T21	474
bins_for_gpio_bits[16]	auto[0]	auto[0]	7584882	1			T19	88		T20	1580		T21	509
bins_for_gpio_bits[16]	auto[0]	auto[1]	227085	1			T20	77		T22	1		T24	10
bins_for_gpio_bits[16]	auto[1]	auto[0]	227299	1			T20	77		T22	2		T24	10
bins_for_gpio_bits[16]	auto[1]	auto[1]	5153339	1			T19	87		T20	493		T21	437
bins_for_gpio_bits[17]	auto[0]	auto[0]	7584516	1			T19	93		T20	1620		T21	455
bins_for_gpio_bits[17]	auto[0]	auto[1]	226435	1			T20	65		T24	8		T25	8122
bins_for_gpio_bits[17]	auto[1]	auto[0]	226643	1			T20	65		T24	8		T25	8122
bins_for_gpio_bits[17]	auto[1]	auto[1]	5155011	1			T19	82		T20	477		T21	491
bins_for_gpio_bits[18]	auto[0]	auto[0]	7581939	1			T19	80		T20	1706		T21	430
bins_for_gpio_bits[18]	auto[0]	auto[1]	226868	1			T20	66		T24	7		T25	8250
bins_for_gpio_bits[18]	auto[1]	auto[0]	227075	1			T20	67		T24	6		T25	8250
bins_for_gpio_bits[18]	auto[1]	auto[1]	5156723	1			T19	95		T20	388		T21	516
bins_for_gpio_bits[19]	auto[0]	auto[0]	7591246	1			T19	83		T20	1687		T21	455
bins_for_gpio_bits[19]	auto[0]	auto[1]	226400	1			T20	73		T24	9		T25	8361
bins_for_gpio_bits[19]	auto[1]	auto[0]	226613	1			T20	73		T24	9		T25	8361
bins_for_gpio_bits[19]	auto[1]	auto[1]	5148346	1			T19	92		T20	394		T21	491
bins_for_gpio_bits[20]	auto[0]	auto[0]	7578110	1			T19	88		T20	1643		T21	488
bins_for_gpio_bits[20]	auto[0]	auto[1]	226950	1			T20	69		T24	8		T25	8129
bins_for_gpio_bits[20]	auto[1]	auto[0]	227160	1			T20	70		T24	8		T25	8130
bins_for_gpio_bits[20]	auto[1]	auto[1]	5160385	1			T19	87		T20	445		T21	458
bins_for_gpio_bits[21]	auto[0]	auto[0]	7575498	1			T19	84		T20	1745		T21	540
bins_for_gpio_bits[21]	auto[0]	auto[1]	226512	1			T20	56		T24	10		T25	8096
bins_for_gpio_bits[21]	auto[1]	auto[0]	226745	1			T20	56		T24	10		T25	8096
bins_for_gpio_bits[21]	auto[1]	auto[1]	5163850	1			T19	91		T20	370		T21	406
bins_for_gpio_bits[22]	auto[0]	auto[0]	7566063	1			T19	78		T20	1788		T21	440
bins_for_gpio_bits[22]	auto[0]	auto[1]	227309	1			T20	48		T24	11		T25	8075
bins_for_gpio_bits[22]	auto[1]	auto[0]	227535	1			T20	48		T24	11		T25	8075
bins_for_gpio_bits[22]	auto[1]	auto[1]	5171698	1			T19	97		T20	343		T21	506
bins_for_gpio_bits[23]	auto[0]	auto[0]	7571576	1			T19	82		T20	1622		T21	453
bins_for_gpio_bits[23]	auto[0]	auto[1]	227000	1			T20	57		T24	12		T25	8334
bins_for_gpio_bits[23]	auto[1]	auto[0]	227248	1			T20	57		T24	12		T25	8335
bins_for_gpio_bits[23]	auto[1]	auto[1]	5166781	1			T19	93		T20	491		T21	493
bins_for_gpio_bits[24]	auto[0]	auto[0]	7576391	1			T19	98		T20	1655		T21	502
bins_for_gpio_bits[24]	auto[0]	auto[1]	226408	1			T20	68		T24	12		T25	8191
bins_for_gpio_bits[24]	auto[1]	auto[0]	226613	1			T20	68		T24	12		T25	8191
bins_for_gpio_bits[24]	auto[1]	auto[1]	5163193	1			T19	77		T20	436		T21	444
bins_for_gpio_bits[25]	auto[0]	auto[0]	7580469	1			T19	78		T20	1750		T21	497
bins_for_gpio_bits[25]	auto[0]	auto[1]	226800	1			T20	63		T24	10		T25	8085
bins_for_gpio_bits[25]	auto[1]	auto[0]	226970	1			T20	63		T24	10		T25	8085
bins_for_gpio_bits[25]	auto[1]	auto[1]	5158366	1			T19	97		T20	351		T21	449
bins_for_gpio_bits[26]	auto[0]	auto[0]	7580652	1			T19	87		T20	1589		T21	416
bins_for_gpio_bits[26]	auto[0]	auto[1]	226725	1			T20	81		T24	8		T25	8308
bins_for_gpio_bits[26]	auto[1]	auto[0]	226929	1			T20	81		T24	8		T25	8308
bins_for_gpio_bits[26]	auto[1]	auto[1]	5158299	1			T19	88		T20	476		T21	530
bins_for_gpio_bits[27]	auto[0]	auto[0]	7585859	1			T19	84		T20	1586		T21	503
bins_for_gpio_bits[27]	auto[0]	auto[1]	226113	1			T20	67		T24	13		T25	8215
bins_for_gpio_bits[27]	auto[1]	auto[0]	226340	1			T20	68		T24	12		T25	8215
bins_for_gpio_bits[27]	auto[1]	auto[1]	5154293	1			T19	91		T20	506		T21	443
bins_for_gpio_bits[28]	auto[0]	auto[0]	7576724	1			T19	76		T20	1600		T21	463
bins_for_gpio_bits[28]	auto[0]	auto[1]	226726	1			T20	76		T24	2		T25	8149
bins_for_gpio_bits[28]	auto[1]	auto[0]	226951	1			T20	76		T24	2		T25	8149
bins_for_gpio_bits[28]	auto[1]	auto[1]	5162204	1			T19	99		T20	475		T21	483
bins_for_gpio_bits[29]	auto[0]	auto[0]	7581160	1			T19	85		T20	1641		T21	501
bins_for_gpio_bits[29]	auto[0]	auto[1]	226136	1			T20	61		T24	6		T25	8251
bins_for_gpio_bits[29]	auto[1]	auto[0]	226345	1			T20	62		T24	6		T25	8251
bins_for_gpio_bits[29]	auto[1]	auto[1]	5158964	1			T19	90		T20	463		T21	445
bins_for_gpio_bits[30]	auto[0]	auto[0]	7584145	1			T19	87		T20	1546		T21	404
bins_for_gpio_bits[30]	auto[0]	auto[1]	226669	1			T20	80		T24	10		T25	8210
bins_for_gpio_bits[30]	auto[1]	auto[0]	226887	1			T20	81		T24	10		T25	8210
bins_for_gpio_bits[30]	auto[1]	auto[1]	5154904	1			T19	88		T20	520		T21	542
bins_for_gpio_bits[31]	auto[0]	auto[0]	7578509	1			T19	84		T20	1685		T21	475
bins_for_gpio_bits[31]	auto[0]	auto[1]	226825	1			T20	67		T24	6		T25	8297
bins_for_gpio_bits[31]	auto[1]	auto[0]	227065	1			T20	67		T24	6		T25	8297
bins_for_gpio_bits[31]	auto[1]	auto[1]	5160206	1			T19	91		T20	408		T21	471