Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7845166 |
1 |
|
|
T19 |
183 |
|
T20 |
1164 |
|
T21 |
946 |
| auto[1] |
5542505 |
1 |
|
|
T19 |
164 |
|
T20 |
1188 |
|
T22 |
28 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12677413 |
1 |
|
|
T19 |
336 |
|
T20 |
2302 |
|
T21 |
946 |
| auto[1] |
710258 |
1 |
|
|
T19 |
11 |
|
T20 |
50 |
|
T25 |
31011 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7842208 |
1 |
|
|
T19 |
165 |
|
T20 |
1203 |
|
T21 |
946 |
| auto[1] |
5545463 |
1 |
|
|
T19 |
182 |
|
T20 |
1149 |
|
T22 |
15 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2416780 |
1 |
|
|
T19 |
90 |
|
T20 |
552 |
|
T22 |
15 |
| auto[1] |
auto[0] |
auto[1] |
354831 |
1 |
|
|
T19 |
7 |
|
T20 |
27 |
|
T25 |
15410 |
| auto[1] |
auto[1] |
auto[0] |
2418425 |
1 |
|
|
T19 |
81 |
|
T20 |
547 |
|
T25 |
99572 |
| auto[1] |
auto[1] |
auto[1] |
355427 |
1 |
|
|
T19 |
4 |
|
T20 |
23 |
|
T25 |
15601 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7826795 |
1 |
|
|
T19 |
119 |
|
T20 |
1298 |
|
T21 |
946 |
| auto[1] |
5560876 |
1 |
|
|
T19 |
228 |
|
T20 |
1054 |
|
T22 |
27 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12678014 |
1 |
|
|
T19 |
334 |
|
T20 |
2303 |
|
T21 |
946 |
| auto[1] |
709657 |
1 |
|
|
T19 |
13 |
|
T20 |
49 |
|
T22 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7839294 |
1 |
|
|
T19 |
174 |
|
T20 |
1080 |
|
T21 |
946 |
| auto[1] |
5548377 |
1 |
|
|
T19 |
173 |
|
T20 |
1272 |
|
T22 |
36 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2398397 |
1 |
|
|
T19 |
59 |
|
T20 |
620 |
|
T22 |
26 |
| auto[1] |
auto[0] |
auto[1] |
350542 |
1 |
|
|
T19 |
4 |
|
T20 |
24 |
|
T22 |
2 |
| auto[1] |
auto[1] |
auto[0] |
2440323 |
1 |
|
|
T19 |
101 |
|
T20 |
603 |
|
T22 |
8 |
| auto[1] |
auto[1] |
auto[1] |
359115 |
1 |
|
|
T19 |
9 |
|
T20 |
25 |
|
T25 |
16555 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7887322 |
1 |
|
|
T19 |
243 |
|
T20 |
1101 |
|
T21 |
946 |
| auto[1] |
5500349 |
1 |
|
|
T19 |
104 |
|
T20 |
1251 |
|
T22 |
35 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12681965 |
1 |
|
|
T19 |
333 |
|
T20 |
2307 |
|
T21 |
946 |
| auto[1] |
705706 |
1 |
|
|
T19 |
14 |
|
T20 |
45 |
|
T25 |
31543 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7862312 |
1 |
|
|
T19 |
181 |
|
T20 |
1065 |
|
T21 |
946 |
| auto[1] |
5525359 |
1 |
|
|
T19 |
166 |
|
T20 |
1287 |
|
T22 |
20 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2412453 |
1 |
|
|
T19 |
118 |
|
T20 |
581 |
|
T22 |
20 |
| auto[1] |
auto[0] |
auto[1] |
353682 |
1 |
|
|
T19 |
10 |
|
T20 |
22 |
|
T25 |
14670 |
| auto[1] |
auto[1] |
auto[0] |
2407200 |
1 |
|
|
T19 |
34 |
|
T20 |
661 |
|
T25 |
106696 |
| auto[1] |
auto[1] |
auto[1] |
352024 |
1 |
|
|
T19 |
4 |
|
T20 |
23 |
|
T25 |
16873 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7846069 |
1 |
|
|
T19 |
236 |
|
T20 |
1190 |
|
T21 |
946 |
| auto[1] |
5541602 |
1 |
|
|
T19 |
111 |
|
T20 |
1162 |
|
T22 |
26 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12678579 |
1 |
|
|
T19 |
338 |
|
T20 |
2292 |
|
T21 |
946 |
| auto[1] |
709092 |
1 |
|
|
T19 |
9 |
|
T20 |
60 |
|
T25 |
32335 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7841074 |
1 |
|
|
T19 |
188 |
|
T20 |
1230 |
|
T21 |
946 |
| auto[1] |
5546597 |
1 |
|
|
T19 |
159 |
|
T20 |
1122 |
|
T22 |
16 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2413508 |
1 |
|
|
T19 |
90 |
|
T20 |
541 |
|
T22 |
16 |
| auto[1] |
auto[0] |
auto[1] |
353843 |
1 |
|
|
T19 |
6 |
|
T20 |
33 |
|
T25 |
16113 |
| auto[1] |
auto[1] |
auto[0] |
2423997 |
1 |
|
|
T19 |
60 |
|
T20 |
521 |
|
T25 |
102994 |
| auto[1] |
auto[1] |
auto[1] |
355249 |
1 |
|
|
T19 |
3 |
|
T20 |
27 |
|
T25 |
16222 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7869653 |
1 |
|
|
T19 |
168 |
|
T20 |
1264 |
|
T21 |
946 |
| auto[1] |
5518018 |
1 |
|
|
T19 |
179 |
|
T20 |
1088 |
|
T22 |
38 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12671276 |
1 |
|
|
T19 |
334 |
|
T20 |
2306 |
|
T21 |
946 |
| auto[1] |
716395 |
1 |
|
|
T19 |
13 |
|
T20 |
46 |
|
T25 |
31351 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7803324 |
1 |
|
|
T19 |
139 |
|
T20 |
1154 |
|
T21 |
946 |
| auto[1] |
5584347 |
1 |
|
|
T19 |
208 |
|
T20 |
1198 |
|
T22 |
12 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2443141 |
1 |
|
|
T19 |
106 |
|
T20 |
612 |
|
T22 |
9 |
| auto[1] |
auto[0] |
auto[1] |
359979 |
1 |
|
|
T19 |
9 |
|
T20 |
23 |
|
T25 |
15625 |
| auto[1] |
auto[1] |
auto[0] |
2424811 |
1 |
|
|
T19 |
89 |
|
T20 |
540 |
|
T22 |
3 |
| auto[1] |
auto[1] |
auto[1] |
356416 |
1 |
|
|
T19 |
4 |
|
T20 |
23 |
|
T25 |
15726 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7854632 |
1 |
|
|
T19 |
170 |
|
T20 |
1170 |
|
T21 |
946 |
| auto[1] |
5533039 |
1 |
|
|
T19 |
177 |
|
T20 |
1182 |
|
T22 |
17 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12679938 |
1 |
|
|
T19 |
340 |
|
T20 |
2297 |
|
T21 |
946 |
| auto[1] |
707733 |
1 |
|
|
T19 |
7 |
|
T20 |
55 |
|
T22 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7842998 |
1 |
|
|
T19 |
214 |
|
T20 |
1046 |
|
T21 |
946 |
| auto[1] |
5544673 |
1 |
|
|
T19 |
133 |
|
T20 |
1306 |
|
T22 |
32 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2413945 |
1 |
|
|
T19 |
68 |
|
T20 |
679 |
|
T22 |
30 |
| auto[1] |
auto[0] |
auto[1] |
352289 |
1 |
|
|
T19 |
2 |
|
T20 |
33 |
|
T22 |
2 |
| auto[1] |
auto[1] |
auto[0] |
2422995 |
1 |
|
|
T19 |
58 |
|
T20 |
572 |
|
T25 |
100436 |
| auto[1] |
auto[1] |
auto[1] |
355444 |
1 |
|
|
T19 |
5 |
|
T20 |
22 |
|
T25 |
15645 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7841736 |
1 |
|
|
T19 |
179 |
|
T20 |
1238 |
|
T21 |
946 |
| auto[1] |
5545935 |
1 |
|
|
T19 |
168 |
|
T20 |
1114 |
|
T22 |
24 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12683796 |
1 |
|
|
T19 |
340 |
|
T20 |
2302 |
|
T21 |
946 |
| auto[1] |
703875 |
1 |
|
|
T19 |
7 |
|
T20 |
50 |
|
T25 |
31608 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7871171 |
1 |
|
|
T19 |
199 |
|
T20 |
1182 |
|
T21 |
946 |
| auto[1] |
5516500 |
1 |
|
|
T19 |
148 |
|
T20 |
1170 |
|
T22 |
27 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2402992 |
1 |
|
|
T19 |
76 |
|
T20 |
595 |
|
T22 |
24 |
| auto[1] |
auto[0] |
auto[1] |
349531 |
1 |
|
|
T19 |
4 |
|
T20 |
23 |
|
T25 |
14843 |
| auto[1] |
auto[1] |
auto[0] |
2409633 |
1 |
|
|
T19 |
65 |
|
T20 |
525 |
|
T22 |
3 |
| auto[1] |
auto[1] |
auto[1] |
354344 |
1 |
|
|
T19 |
3 |
|
T20 |
27 |
|
T25 |
16765 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7884231 |
1 |
|
|
T19 |
216 |
|
T20 |
1155 |
|
T21 |
946 |
| auto[1] |
5503440 |
1 |
|
|
T19 |
131 |
|
T20 |
1197 |
|
T22 |
30 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12683097 |
1 |
|
|
T19 |
335 |
|
T20 |
2302 |
|
T21 |
946 |
| auto[1] |
704574 |
1 |
|
|
T19 |
12 |
|
T20 |
50 |
|
T25 |
31644 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7871556 |
1 |
|
|
T19 |
199 |
|
T20 |
1104 |
|
T21 |
946 |
| auto[1] |
5516115 |
1 |
|
|
T19 |
148 |
|
T20 |
1248 |
|
T22 |
20 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2417735 |
1 |
|
|
T19 |
91 |
|
T20 |
563 |
|
T22 |
20 |
| auto[1] |
auto[0] |
auto[1] |
354145 |
1 |
|
|
T19 |
8 |
|
T20 |
18 |
|
T25 |
15824 |
| auto[1] |
auto[1] |
auto[0] |
2393806 |
1 |
|
|
T19 |
45 |
|
T20 |
635 |
|
T25 |
101394 |
| auto[1] |
auto[1] |
auto[1] |
350429 |
1 |
|
|
T19 |
4 |
|
T20 |
32 |
|
T25 |
15820 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7847650 |
1 |
|
|
T19 |
138 |
|
T20 |
1077 |
|
T21 |
946 |
| auto[1] |
5540021 |
1 |
|
|
T19 |
209 |
|
T20 |
1275 |
|
T22 |
47 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12685426 |
1 |
|
|
T19 |
340 |
|
T20 |
2299 |
|
T21 |
946 |
| auto[1] |
702245 |
1 |
|
|
T19 |
7 |
|
T20 |
53 |
|
T22 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7883436 |
1 |
|
|
T19 |
172 |
|
T20 |
1231 |
|
T21 |
946 |
| auto[1] |
5504235 |
1 |
|
|
T19 |
175 |
|
T20 |
1121 |
|
T22 |
24 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2412586 |
1 |
|
|
T19 |
60 |
|
T20 |
502 |
|
T22 |
12 |
| auto[1] |
auto[0] |
auto[1] |
353805 |
1 |
|
|
T19 |
2 |
|
T20 |
20 |
|
T22 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2389404 |
1 |
|
|
T19 |
108 |
|
T20 |
566 |
|
T22 |
10 |
| auto[1] |
auto[1] |
auto[1] |
348440 |
1 |
|
|
T19 |
5 |
|
T20 |
33 |
|
T22 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7836153 |
1 |
|
|
T19 |
102 |
|
T20 |
1331 |
|
T21 |
946 |
| auto[1] |
5551518 |
1 |
|
|
T19 |
245 |
|
T20 |
1021 |
|
T22 |
40 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12684026 |
1 |
|
|
T19 |
334 |
|
T20 |
2310 |
|
T21 |
946 |
| auto[1] |
703645 |
1 |
|
|
T19 |
13 |
|
T20 |
42 |
|
T22 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7877192 |
1 |
|
|
T19 |
175 |
|
T20 |
1271 |
|
T21 |
946 |
| auto[1] |
5510479 |
1 |
|
|
T19 |
172 |
|
T20 |
1081 |
|
T22 |
13 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2401125 |
1 |
|
|
T19 |
44 |
|
T20 |
599 |
|
T22 |
3 |
| auto[1] |
auto[0] |
auto[1] |
350887 |
1 |
|
|
T19 |
3 |
|
T20 |
29 |
|
T25 |
16546 |
| auto[1] |
auto[1] |
auto[0] |
2405709 |
1 |
|
|
T19 |
115 |
|
T20 |
440 |
|
T22 |
9 |
| auto[1] |
auto[1] |
auto[1] |
352758 |
1 |
|
|
T19 |
10 |
|
T20 |
13 |
|
T22 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7887818 |
1 |
|
|
T19 |
174 |
|
T20 |
1031 |
|
T21 |
946 |
| auto[1] |
5499853 |
1 |
|
|
T19 |
173 |
|
T20 |
1321 |
|
T22 |
21 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12681888 |
1 |
|
|
T19 |
335 |
|
T20 |
2323 |
|
T21 |
946 |
| auto[1] |
705783 |
1 |
|
|
T19 |
12 |
|
T20 |
29 |
|
T22 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7867658 |
1 |
|
|
T19 |
114 |
|
T20 |
1499 |
|
T21 |
946 |
| auto[1] |
5520013 |
1 |
|
|
T19 |
233 |
|
T20 |
853 |
|
T22 |
36 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2425829 |
1 |
|
|
T19 |
102 |
|
T20 |
378 |
|
T22 |
24 |
| auto[1] |
auto[0] |
auto[1] |
356782 |
1 |
|
|
T19 |
7 |
|
T20 |
14 |
|
T22 |
2 |
| auto[1] |
auto[1] |
auto[0] |
2388401 |
1 |
|
|
T19 |
119 |
|
T20 |
446 |
|
T22 |
10 |
| auto[1] |
auto[1] |
auto[1] |
349001 |
1 |
|
|
T19 |
5 |
|
T20 |
15 |
|
T25 |
15682 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7887884 |
1 |
|
|
T19 |
173 |
|
T20 |
1178 |
|
T21 |
946 |
| auto[1] |
5499787 |
1 |
|
|
T19 |
174 |
|
T20 |
1174 |
|
T22 |
38 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12683752 |
1 |
|
|
T19 |
336 |
|
T20 |
2299 |
|
T21 |
946 |
| auto[1] |
703919 |
1 |
|
|
T19 |
11 |
|
T20 |
53 |
|
T22 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7889809 |
1 |
|
|
T19 |
187 |
|
T20 |
1111 |
|
T21 |
946 |
| auto[1] |
5497862 |
1 |
|
|
T19 |
160 |
|
T20 |
1241 |
|
T22 |
17 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2394858 |
1 |
|
|
T19 |
61 |
|
T20 |
580 |
|
T22 |
8 |
| auto[1] |
auto[0] |
auto[1] |
351432 |
1 |
|
|
T19 |
6 |
|
T20 |
24 |
|
T25 |
15958 |
| auto[1] |
auto[1] |
auto[0] |
2399085 |
1 |
|
|
T19 |
88 |
|
T20 |
608 |
|
T22 |
8 |
| auto[1] |
auto[1] |
auto[1] |
352487 |
1 |
|
|
T19 |
5 |
|
T20 |
29 |
|
T22 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7882495 |
1 |
|
|
T19 |
121 |
|
T20 |
1048 |
|
T21 |
946 |
| auto[1] |
5505176 |
1 |
|
|
T19 |
226 |
|
T20 |
1304 |
|
T22 |
33 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12679718 |
1 |
|
|
T19 |
339 |
|
T20 |
2307 |
|
T21 |
946 |
| auto[1] |
707953 |
1 |
|
|
T19 |
8 |
|
T20 |
45 |
|
T22 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7852594 |
1 |
|
|
T19 |
197 |
|
T20 |
1143 |
|
T21 |
946 |
| auto[1] |
5535077 |
1 |
|
|
T19 |
150 |
|
T20 |
1209 |
|
T22 |
19 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2425143 |
1 |
|
|
T19 |
48 |
|
T20 |
439 |
|
T22 |
11 |
| auto[1] |
auto[0] |
auto[1] |
356053 |
1 |
|
|
T19 |
4 |
|
T20 |
22 |
|
T25 |
14916 |
| auto[1] |
auto[1] |
auto[0] |
2401981 |
1 |
|
|
T19 |
94 |
|
T20 |
725 |
|
T22 |
7 |
| auto[1] |
auto[1] |
auto[1] |
351900 |
1 |
|
|
T19 |
4 |
|
T20 |
23 |
|
T22 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7866761 |
1 |
|
|
T19 |
201 |
|
T20 |
1152 |
|
T21 |
946 |
| auto[1] |
5520910 |
1 |
|
|
T19 |
146 |
|
T20 |
1200 |
|
T22 |
22 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12678477 |
1 |
|
|
T19 |
339 |
|
T20 |
2315 |
|
T21 |
946 |
| auto[1] |
709194 |
1 |
|
|
T19 |
8 |
|
T20 |
37 |
|
T25 |
30608 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7844855 |
1 |
|
|
T19 |
190 |
|
T20 |
1322 |
|
T21 |
946 |
| auto[1] |
5542816 |
1 |
|
|
T19 |
157 |
|
T20 |
1030 |
|
T22 |
8 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2429270 |
1 |
|
|
T19 |
82 |
|
T20 |
484 |
|
T22 |
8 |
| auto[1] |
auto[0] |
auto[1] |
357219 |
1 |
|
|
T19 |
4 |
|
T20 |
18 |
|
T25 |
15815 |
| auto[1] |
auto[1] |
auto[0] |
2404352 |
1 |
|
|
T19 |
67 |
|
T20 |
509 |
|
T25 |
97512 |
| auto[1] |
auto[1] |
auto[1] |
351975 |
1 |
|
|
T19 |
4 |
|
T20 |
19 |
|
T25 |
14793 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7888901 |
1 |
|
|
T19 |
201 |
|
T20 |
1387 |
|
T21 |
946 |
| auto[1] |
5498770 |
1 |
|
|
T19 |
146 |
|
T20 |
965 |
|
T22 |
30 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12677581 |
1 |
|
|
T19 |
336 |
|
T20 |
2321 |
|
T21 |
946 |
| auto[1] |
710090 |
1 |
|
|
T19 |
11 |
|
T20 |
31 |
|
T22 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7835435 |
1 |
|
|
T19 |
175 |
|
T20 |
1289 |
|
T21 |
946 |
| auto[1] |
5552236 |
1 |
|
|
T19 |
172 |
|
T20 |
1063 |
|
T22 |
20 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2430156 |
1 |
|
|
T19 |
93 |
|
T20 |
565 |
|
T22 |
15 |
| auto[1] |
auto[0] |
auto[1] |
354838 |
1 |
|
|
T19 |
8 |
|
T20 |
17 |
|
T25 |
15155 |
| auto[1] |
auto[1] |
auto[0] |
2411990 |
1 |
|
|
T19 |
68 |
|
T20 |
467 |
|
T22 |
4 |
| auto[1] |
auto[1] |
auto[1] |
355252 |
1 |
|
|
T19 |
3 |
|
T20 |
14 |
|
T22 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7835464 |
1 |
|
|
T19 |
152 |
|
T20 |
1137 |
|
T21 |
946 |
| auto[1] |
5552207 |
1 |
|
|
T19 |
195 |
|
T20 |
1215 |
|
T22 |
44 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12681884 |
1 |
|
|
T19 |
337 |
|
T20 |
2314 |
|
T21 |
946 |
| auto[1] |
705787 |
1 |
|
|
T19 |
10 |
|
T20 |
38 |
|
T25 |
32090 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7857235 |
1 |
|
|
T19 |
180 |
|
T20 |
1045 |
|
T21 |
946 |
| auto[1] |
5530436 |
1 |
|
|
T19 |
167 |
|
T20 |
1307 |
|
T22 |
23 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2417068 |
1 |
|
|
T19 |
68 |
|
T20 |
649 |
|
T22 |
15 |
| auto[1] |
auto[0] |
auto[1] |
353276 |
1 |
|
|
T19 |
4 |
|
T20 |
20 |
|
T25 |
15684 |
| auto[1] |
auto[1] |
auto[0] |
2407581 |
1 |
|
|
T19 |
89 |
|
T20 |
620 |
|
T22 |
8 |
| auto[1] |
auto[1] |
auto[1] |
352511 |
1 |
|
|
T19 |
6 |
|
T20 |
18 |
|
T25 |
16406 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7885277 |
1 |
|
|
T19 |
223 |
|
T20 |
1234 |
|
T21 |
946 |
| auto[1] |
5502394 |
1 |
|
|
T19 |
124 |
|
T20 |
1118 |
|
T22 |
26 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12687667 |
1 |
|
|
T19 |
337 |
|
T20 |
2310 |
|
T21 |
946 |
| auto[1] |
700004 |
1 |
|
|
T19 |
10 |
|
T20 |
42 |
|
T25 |
31038 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7904345 |
1 |
|
|
T19 |
201 |
|
T20 |
1357 |
|
T21 |
946 |
| auto[1] |
5483326 |
1 |
|
|
T19 |
146 |
|
T20 |
995 |
|
T22 |
20 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2393743 |
1 |
|
|
T19 |
84 |
|
T20 |
568 |
|
T22 |
20 |
| auto[1] |
auto[0] |
auto[1] |
349929 |
1 |
|
|
T19 |
8 |
|
T20 |
22 |
|
T25 |
16231 |
| auto[1] |
auto[1] |
auto[0] |
2389579 |
1 |
|
|
T19 |
52 |
|
T20 |
385 |
|
T25 |
96637 |
| auto[1] |
auto[1] |
auto[1] |
350075 |
1 |
|
|
T19 |
2 |
|
T20 |
20 |
|
T25 |
14807 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7893455 |
1 |
|
|
T19 |
157 |
|
T20 |
1191 |
|
T21 |
946 |
| auto[1] |
5494216 |
1 |
|
|
T19 |
190 |
|
T20 |
1161 |
|
T22 |
25 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12679171 |
1 |
|
|
T19 |
339 |
|
T20 |
2309 |
|
T21 |
946 |
| auto[1] |
708500 |
1 |
|
|
T19 |
8 |
|
T20 |
43 |
|
T22 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7845535 |
1 |
|
|
T19 |
146 |
|
T20 |
1235 |
|
T21 |
946 |
| auto[1] |
5542136 |
1 |
|
|
T19 |
201 |
|
T20 |
1117 |
|
T22 |
26 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2431273 |
1 |
|
|
T19 |
87 |
|
T20 |
547 |
|
T22 |
15 |
| auto[1] |
auto[0] |
auto[1] |
356927 |
1 |
|
|
T19 |
2 |
|
T20 |
22 |
|
T22 |
2 |
| auto[1] |
auto[1] |
auto[0] |
2402363 |
1 |
|
|
T19 |
106 |
|
T20 |
527 |
|
T22 |
9 |
| auto[1] |
auto[1] |
auto[1] |
351573 |
1 |
|
|
T19 |
6 |
|
T20 |
21 |
|
T25 |
14960 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7902917 |
1 |
|
|
T19 |
235 |
|
T20 |
1176 |
|
T21 |
946 |
| auto[1] |
5484754 |
1 |
|
|
T19 |
112 |
|
T20 |
1176 |
|
T22 |
36 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12678790 |
1 |
|
|
T19 |
337 |
|
T20 |
2308 |
|
T21 |
946 |
| auto[1] |
708881 |
1 |
|
|
T19 |
10 |
|
T20 |
44 |
|
T25 |
30759 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7836107 |
1 |
|
|
T19 |
143 |
|
T20 |
1092 |
|
T21 |
946 |
| auto[1] |
5551564 |
1 |
|
|
T19 |
204 |
|
T20 |
1260 |
|
T22 |
7 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2435461 |
1 |
|
|
T19 |
122 |
|
T20 |
622 |
|
T22 |
4 |
| auto[1] |
auto[0] |
auto[1] |
357489 |
1 |
|
|
T19 |
5 |
|
T20 |
22 |
|
T25 |
15613 |
| auto[1] |
auto[1] |
auto[0] |
2407222 |
1 |
|
|
T19 |
72 |
|
T20 |
594 |
|
T22 |
3 |
| auto[1] |
auto[1] |
auto[1] |
351392 |
1 |
|
|
T19 |
5 |
|
T20 |
22 |
|
T25 |
15146 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |