Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7883820 |
1 |
|
|
T19 |
127 |
|
T20 |
1238 |
|
T21 |
946 |
| auto[1] |
5503851 |
1 |
|
|
T19 |
220 |
|
T20 |
1114 |
|
T22 |
41 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12685900 |
1 |
|
|
T19 |
335 |
|
T20 |
2305 |
|
T21 |
946 |
| auto[1] |
701771 |
1 |
|
|
T19 |
12 |
|
T20 |
47 |
|
T22 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7885724 |
1 |
|
|
T19 |
121 |
|
T20 |
1046 |
|
T21 |
946 |
| auto[1] |
5501947 |
1 |
|
|
T19 |
226 |
|
T20 |
1306 |
|
T22 |
15 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2415307 |
1 |
|
|
T19 |
86 |
|
T20 |
658 |
|
T22 |
13 |
| auto[1] |
auto[0] |
auto[1] |
353247 |
1 |
|
|
T19 |
3 |
|
T20 |
34 |
|
T22 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2384869 |
1 |
|
|
T19 |
128 |
|
T20 |
601 |
|
T22 |
1 |
| auto[1] |
auto[1] |
auto[1] |
348524 |
1 |
|
|
T19 |
9 |
|
T20 |
13 |
|
T25 |
15181 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |