Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7826468 |
1 |
|
|
T19 |
151 |
|
T20 |
1110 |
|
T21 |
946 |
| auto[1] |
5561203 |
1 |
|
|
T19 |
196 |
|
T20 |
1242 |
|
T22 |
19 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12687592 |
1 |
|
|
T19 |
330 |
|
T20 |
2305 |
|
T21 |
946 |
| auto[1] |
700079 |
1 |
|
|
T19 |
17 |
|
T20 |
47 |
|
T25 |
30599 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7903349 |
1 |
|
|
T19 |
173 |
|
T20 |
1202 |
|
T21 |
946 |
| auto[1] |
5484322 |
1 |
|
|
T19 |
174 |
|
T20 |
1150 |
|
T22 |
30 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2398449 |
1 |
|
|
T19 |
71 |
|
T20 |
526 |
|
T22 |
27 |
| auto[1] |
auto[0] |
auto[1] |
350626 |
1 |
|
|
T19 |
8 |
|
T20 |
28 |
|
T25 |
15507 |
| auto[1] |
auto[1] |
auto[0] |
2385794 |
1 |
|
|
T19 |
86 |
|
T20 |
577 |
|
T22 |
3 |
| auto[1] |
auto[1] |
auto[1] |
349453 |
1 |
|
|
T19 |
9 |
|
T20 |
19 |
|
T25 |
15092 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |