Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7866024 |
1 |
|
|
T19 |
194 |
|
T20 |
1409 |
|
T21 |
946 |
| auto[1] |
5521647 |
1 |
|
|
T19 |
153 |
|
T20 |
943 |
|
T22 |
17 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12681393 |
1 |
|
|
T19 |
340 |
|
T20 |
2305 |
|
T21 |
946 |
| auto[1] |
706278 |
1 |
|
|
T19 |
7 |
|
T20 |
47 |
|
T25 |
31394 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7863573 |
1 |
|
|
T19 |
208 |
|
T20 |
1227 |
|
T21 |
946 |
| auto[1] |
5524098 |
1 |
|
|
T19 |
139 |
|
T20 |
1125 |
|
T22 |
25 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2413328 |
1 |
|
|
T19 |
78 |
|
T20 |
677 |
|
T22 |
25 |
| auto[1] |
auto[0] |
auto[1] |
354960 |
1 |
|
|
T19 |
7 |
|
T20 |
29 |
|
T25 |
15851 |
| auto[1] |
auto[1] |
auto[0] |
2404492 |
1 |
|
|
T19 |
54 |
|
T20 |
401 |
|
T25 |
99557 |
| auto[1] |
auto[1] |
auto[1] |
351318 |
1 |
|
|
T20 |
18 |
|
T25 |
15543 |
|
T28 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |