Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7860334 |
1 |
|
|
T19 |
131 |
|
T20 |
1236 |
|
T21 |
946 |
| auto[1] |
5527337 |
1 |
|
|
T19 |
216 |
|
T20 |
1116 |
|
T22 |
30 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12683639 |
1 |
|
|
T19 |
332 |
|
T20 |
2306 |
|
T21 |
946 |
| auto[1] |
704032 |
1 |
|
|
T19 |
15 |
|
T20 |
46 |
|
T22 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7883148 |
1 |
|
|
T19 |
153 |
|
T20 |
1045 |
|
T21 |
946 |
| auto[1] |
5504523 |
1 |
|
|
T19 |
194 |
|
T20 |
1307 |
|
T22 |
23 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2415328 |
1 |
|
|
T19 |
52 |
|
T20 |
608 |
|
T22 |
21 |
| auto[1] |
auto[0] |
auto[1] |
354550 |
1 |
|
|
T19 |
6 |
|
T20 |
20 |
|
T22 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2385163 |
1 |
|
|
T19 |
127 |
|
T20 |
653 |
|
T22 |
1 |
| auto[1] |
auto[1] |
auto[1] |
349482 |
1 |
|
|
T19 |
9 |
|
T20 |
26 |
|
T25 |
15445 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |