Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7887322 |
1 |
|
|
T19 |
243 |
|
T20 |
1101 |
|
T21 |
946 |
| auto[1] |
5500349 |
1 |
|
|
T19 |
104 |
|
T20 |
1251 |
|
T22 |
35 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11097123 |
1 |
|
|
T19 |
265 |
|
T20 |
2110 |
|
T21 |
946 |
| auto[1] |
2290548 |
1 |
|
|
T19 |
82 |
|
T20 |
242 |
|
T22 |
15 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7848616 |
1 |
|
|
T19 |
170 |
|
T20 |
1193 |
|
T21 |
946 |
| auto[1] |
5539055 |
1 |
|
|
T19 |
177 |
|
T20 |
1159 |
|
T22 |
40 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1627133 |
1 |
|
|
T19 |
66 |
|
T20 |
476 |
|
T22 |
23 |
| auto[1] |
auto[0] |
auto[1] |
1144286 |
1 |
|
|
T19 |
53 |
|
T20 |
100 |
|
T22 |
9 |
| auto[1] |
auto[1] |
auto[0] |
1621374 |
1 |
|
|
T19 |
29 |
|
T20 |
441 |
|
T22 |
2 |
| auto[1] |
auto[1] |
auto[1] |
1146262 |
1 |
|
|
T19 |
29 |
|
T20 |
142 |
|
T22 |
6 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |