Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7846069 |
1 |
|
|
T19 |
236 |
|
T20 |
1190 |
|
T21 |
946 |
| auto[1] |
5541602 |
1 |
|
|
T19 |
111 |
|
T20 |
1162 |
|
T22 |
26 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11084896 |
1 |
|
|
T19 |
277 |
|
T20 |
2044 |
|
T21 |
946 |
| auto[1] |
2302775 |
1 |
|
|
T19 |
70 |
|
T20 |
308 |
|
T22 |
10 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7830765 |
1 |
|
|
T19 |
193 |
|
T20 |
947 |
|
T21 |
946 |
| auto[1] |
5556906 |
1 |
|
|
T19 |
154 |
|
T20 |
1405 |
|
T22 |
16 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1616890 |
1 |
|
|
T19 |
57 |
|
T20 |
503 |
|
T22 |
6 |
| auto[1] |
auto[0] |
auto[1] |
1148142 |
1 |
|
|
T19 |
49 |
|
T20 |
181 |
|
T22 |
10 |
| auto[1] |
auto[1] |
auto[0] |
1637241 |
1 |
|
|
T19 |
27 |
|
T20 |
594 |
|
T25 |
70700 |
| auto[1] |
auto[1] |
auto[1] |
1154633 |
1 |
|
|
T19 |
21 |
|
T20 |
127 |
|
T25 |
44796 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |