Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7869653 |
1 |
|
|
T19 |
168 |
|
T20 |
1264 |
|
T21 |
946 |
| auto[1] |
5518018 |
1 |
|
|
T19 |
179 |
|
T20 |
1088 |
|
T22 |
38 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11092400 |
1 |
|
|
T19 |
277 |
|
T20 |
2194 |
|
T21 |
946 |
| auto[1] |
2295271 |
1 |
|
|
T19 |
70 |
|
T20 |
158 |
|
T22 |
20 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7847743 |
1 |
|
|
T19 |
236 |
|
T20 |
1521 |
|
T21 |
946 |
| auto[1] |
5539928 |
1 |
|
|
T19 |
111 |
|
T20 |
831 |
|
T22 |
35 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1622393 |
1 |
|
|
T19 |
13 |
|
T20 |
348 |
|
T22 |
11 |
| auto[1] |
auto[0] |
auto[1] |
1146701 |
1 |
|
|
T19 |
27 |
|
T20 |
75 |
|
T22 |
10 |
| auto[1] |
auto[1] |
auto[0] |
1622264 |
1 |
|
|
T19 |
28 |
|
T20 |
325 |
|
T22 |
4 |
| auto[1] |
auto[1] |
auto[1] |
1148570 |
1 |
|
|
T19 |
43 |
|
T20 |
83 |
|
T22 |
10 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |