Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7866376 |
1 |
|
|
T19 |
187 |
|
T20 |
1118 |
|
T21 |
946 |
| auto[1] |
5521295 |
1 |
|
|
T19 |
160 |
|
T20 |
1234 |
|
T22 |
40 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12680982 |
1 |
|
|
T19 |
340 |
|
T20 |
2311 |
|
T21 |
946 |
| auto[1] |
706689 |
1 |
|
|
T19 |
7 |
|
T20 |
41 |
|
T22 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7858342 |
1 |
|
|
T19 |
199 |
|
T20 |
1324 |
|
T21 |
946 |
| auto[1] |
5529329 |
1 |
|
|
T19 |
148 |
|
T20 |
1028 |
|
T22 |
24 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2415870 |
1 |
|
|
T19 |
65 |
|
T20 |
446 |
|
T22 |
4 |
| auto[1] |
auto[0] |
auto[1] |
353889 |
1 |
|
|
T19 |
3 |
|
T20 |
20 |
|
T25 |
15150 |
| auto[1] |
auto[1] |
auto[0] |
2406770 |
1 |
|
|
T19 |
76 |
|
T20 |
541 |
|
T22 |
19 |
| auto[1] |
auto[1] |
auto[1] |
352800 |
1 |
|
|
T19 |
4 |
|
T20 |
21 |
|
T22 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |