Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7884231 |
1 |
|
|
T19 |
216 |
|
T20 |
1155 |
|
T21 |
946 |
| auto[1] |
5503440 |
1 |
|
|
T19 |
131 |
|
T20 |
1197 |
|
T22 |
30 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11097978 |
1 |
|
|
T19 |
214 |
|
T20 |
2121 |
|
T21 |
946 |
| auto[1] |
2289693 |
1 |
|
|
T19 |
133 |
|
T20 |
231 |
|
T22 |
19 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7848195 |
1 |
|
|
T19 |
154 |
|
T20 |
1396 |
|
T21 |
946 |
| auto[1] |
5539476 |
1 |
|
|
T19 |
193 |
|
T20 |
956 |
|
T22 |
49 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1633578 |
1 |
|
|
T19 |
40 |
|
T20 |
330 |
|
T22 |
24 |
| auto[1] |
auto[0] |
auto[1] |
1149791 |
1 |
|
|
T19 |
59 |
|
T20 |
120 |
|
T22 |
5 |
| auto[1] |
auto[1] |
auto[0] |
1616205 |
1 |
|
|
T19 |
20 |
|
T20 |
395 |
|
T22 |
6 |
| auto[1] |
auto[1] |
auto[1] |
1139902 |
1 |
|
|
T19 |
74 |
|
T20 |
111 |
|
T22 |
14 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |