Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7847650 |
1 |
|
|
T19 |
138 |
|
T20 |
1077 |
|
T21 |
946 |
| auto[1] |
5540021 |
1 |
|
|
T19 |
209 |
|
T20 |
1275 |
|
T22 |
47 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11101507 |
1 |
|
|
T19 |
264 |
|
T20 |
2074 |
|
T21 |
946 |
| auto[1] |
2286164 |
1 |
|
|
T19 |
83 |
|
T20 |
278 |
|
T22 |
15 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7870815 |
1 |
|
|
T19 |
188 |
|
T20 |
1323 |
|
T21 |
946 |
| auto[1] |
5516856 |
1 |
|
|
T19 |
159 |
|
T20 |
1029 |
|
T22 |
41 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1622826 |
1 |
|
|
T19 |
25 |
|
T20 |
388 |
|
T22 |
14 |
| auto[1] |
auto[0] |
auto[1] |
1148331 |
1 |
|
|
T19 |
34 |
|
T20 |
116 |
|
T22 |
13 |
| auto[1] |
auto[1] |
auto[0] |
1607866 |
1 |
|
|
T19 |
51 |
|
T20 |
363 |
|
T22 |
12 |
| auto[1] |
auto[1] |
auto[1] |
1137833 |
1 |
|
|
T19 |
49 |
|
T20 |
162 |
|
T22 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |