Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7836153 |
1 |
|
|
T19 |
102 |
|
T20 |
1331 |
|
T21 |
946 |
| auto[1] |
5551518 |
1 |
|
|
T19 |
245 |
|
T20 |
1021 |
|
T22 |
40 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11093446 |
1 |
|
|
T19 |
273 |
|
T20 |
2090 |
|
T21 |
946 |
| auto[1] |
2294225 |
1 |
|
|
T19 |
74 |
|
T20 |
262 |
|
T22 |
34 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7845004 |
1 |
|
|
T19 |
175 |
|
T20 |
1288 |
|
T21 |
946 |
| auto[1] |
5542667 |
1 |
|
|
T19 |
172 |
|
T20 |
1064 |
|
T22 |
47 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1621429 |
1 |
|
|
T19 |
10 |
|
T20 |
404 |
|
T22 |
3 |
| auto[1] |
auto[0] |
auto[1] |
1144900 |
1 |
|
|
T19 |
27 |
|
T20 |
152 |
|
T22 |
25 |
| auto[1] |
auto[1] |
auto[0] |
1627013 |
1 |
|
|
T19 |
88 |
|
T20 |
398 |
|
T22 |
10 |
| auto[1] |
auto[1] |
auto[1] |
1149325 |
1 |
|
|
T19 |
47 |
|
T20 |
110 |
|
T22 |
9 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |