Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7887818 |
1 |
|
|
T19 |
174 |
|
T20 |
1031 |
|
T21 |
946 |
| auto[1] |
5499853 |
1 |
|
|
T19 |
173 |
|
T20 |
1321 |
|
T22 |
21 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11091452 |
1 |
|
|
T19 |
214 |
|
T20 |
2128 |
|
T21 |
946 |
| auto[1] |
2296219 |
1 |
|
|
T19 |
133 |
|
T20 |
224 |
|
T22 |
6 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7846418 |
1 |
|
|
T19 |
135 |
|
T20 |
1100 |
|
T21 |
946 |
| auto[1] |
5541253 |
1 |
|
|
T19 |
212 |
|
T20 |
1252 |
|
T22 |
15 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1633930 |
1 |
|
|
T19 |
54 |
|
T20 |
383 |
|
T22 |
9 |
| auto[1] |
auto[0] |
auto[1] |
1152046 |
1 |
|
|
T19 |
56 |
|
T20 |
115 |
|
T22 |
3 |
| auto[1] |
auto[1] |
auto[0] |
1611104 |
1 |
|
|
T19 |
25 |
|
T20 |
645 |
|
T25 |
71229 |
| auto[1] |
auto[1] |
auto[1] |
1144173 |
1 |
|
|
T19 |
77 |
|
T20 |
109 |
|
T22 |
3 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |