Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7887884 |
1 |
|
|
T19 |
173 |
|
T20 |
1178 |
|
T21 |
946 |
| auto[1] |
5499787 |
1 |
|
|
T19 |
174 |
|
T20 |
1174 |
|
T22 |
38 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11103910 |
1 |
|
|
T19 |
235 |
|
T20 |
2055 |
|
T21 |
946 |
| auto[1] |
2283761 |
1 |
|
|
T19 |
112 |
|
T20 |
297 |
|
T22 |
25 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7883568 |
1 |
|
|
T19 |
146 |
|
T20 |
912 |
|
T21 |
946 |
| auto[1] |
5504103 |
1 |
|
|
T19 |
201 |
|
T20 |
1440 |
|
T22 |
32 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1620910 |
1 |
|
|
T19 |
27 |
|
T20 |
561 |
|
T22 |
2 |
| auto[1] |
auto[0] |
auto[1] |
1146267 |
1 |
|
|
T19 |
55 |
|
T20 |
173 |
|
T22 |
21 |
| auto[1] |
auto[1] |
auto[0] |
1599432 |
1 |
|
|
T19 |
62 |
|
T20 |
582 |
|
T22 |
5 |
| auto[1] |
auto[1] |
auto[1] |
1137494 |
1 |
|
|
T19 |
57 |
|
T20 |
124 |
|
T22 |
4 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |