Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7888901 |
1 |
|
|
T19 |
201 |
|
T20 |
1387 |
|
T21 |
946 |
| auto[1] |
5498770 |
1 |
|
|
T19 |
146 |
|
T20 |
965 |
|
T22 |
30 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11100361 |
1 |
|
|
T19 |
265 |
|
T20 |
2121 |
|
T21 |
946 |
| auto[1] |
2287310 |
1 |
|
|
T19 |
82 |
|
T20 |
231 |
|
T22 |
3 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7881052 |
1 |
|
|
T19 |
197 |
|
T20 |
1122 |
|
T21 |
946 |
| auto[1] |
5506619 |
1 |
|
|
T19 |
150 |
|
T20 |
1230 |
|
T22 |
24 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1619316 |
1 |
|
|
T19 |
26 |
|
T20 |
668 |
|
T22 |
20 |
| auto[1] |
auto[0] |
auto[1] |
1147883 |
1 |
|
|
T19 |
31 |
|
T20 |
118 |
|
T22 |
1 |
| auto[1] |
auto[1] |
auto[0] |
1599993 |
1 |
|
|
T19 |
42 |
|
T20 |
331 |
|
T22 |
1 |
| auto[1] |
auto[1] |
auto[1] |
1139427 |
1 |
|
|
T19 |
51 |
|
T20 |
113 |
|
T22 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |