Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7835464 |
1 |
|
|
T19 |
152 |
|
T20 |
1137 |
|
T21 |
946 |
| auto[1] |
5552207 |
1 |
|
|
T19 |
195 |
|
T20 |
1215 |
|
T22 |
44 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11089997 |
1 |
|
|
T19 |
272 |
|
T20 |
2177 |
|
T21 |
946 |
| auto[1] |
2297674 |
1 |
|
|
T19 |
75 |
|
T20 |
175 |
|
T22 |
6 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7848027 |
1 |
|
|
T19 |
227 |
|
T20 |
1218 |
|
T21 |
946 |
| auto[1] |
5539644 |
1 |
|
|
T19 |
120 |
|
T20 |
1134 |
|
T22 |
16 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1627434 |
1 |
|
|
T19 |
11 |
|
T20 |
491 |
|
T22 |
4 |
| auto[1] |
auto[0] |
auto[1] |
1148065 |
1 |
|
|
T19 |
25 |
|
T20 |
84 |
|
T22 |
6 |
| auto[1] |
auto[1] |
auto[0] |
1614536 |
1 |
|
|
T19 |
34 |
|
T20 |
468 |
|
T22 |
6 |
| auto[1] |
auto[1] |
auto[1] |
1149609 |
1 |
|
|
T19 |
50 |
|
T20 |
91 |
|
T25 |
46514 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |