Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7893455 |
1 |
|
|
T19 |
157 |
|
T20 |
1191 |
|
T21 |
946 |
| auto[1] |
5494216 |
1 |
|
|
T19 |
190 |
|
T20 |
1161 |
|
T22 |
25 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11095519 |
1 |
|
|
T19 |
258 |
|
T20 |
2059 |
|
T21 |
946 |
| auto[1] |
2292152 |
1 |
|
|
T19 |
89 |
|
T20 |
293 |
|
T22 |
19 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7844964 |
1 |
|
|
T19 |
177 |
|
T20 |
1219 |
|
T21 |
946 |
| auto[1] |
5542707 |
1 |
|
|
T19 |
170 |
|
T20 |
1133 |
|
T22 |
46 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1635738 |
1 |
|
|
T19 |
33 |
|
T20 |
421 |
|
T22 |
20 |
| auto[1] |
auto[0] |
auto[1] |
1152680 |
1 |
|
|
T19 |
44 |
|
T20 |
157 |
|
T22 |
16 |
| auto[1] |
auto[1] |
auto[0] |
1614817 |
1 |
|
|
T19 |
48 |
|
T20 |
419 |
|
T22 |
7 |
| auto[1] |
auto[1] |
auto[1] |
1139472 |
1 |
|
|
T19 |
45 |
|
T20 |
136 |
|
T22 |
3 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |