Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7856742 |
1 |
|
|
T19 |
171 |
|
T20 |
1247 |
|
T21 |
946 |
| auto[1] |
5530929 |
1 |
|
|
T19 |
176 |
|
T20 |
1105 |
|
T22 |
33 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12679147 |
1 |
|
|
T19 |
339 |
|
T20 |
2303 |
|
T21 |
946 |
| auto[1] |
708524 |
1 |
|
|
T19 |
8 |
|
T20 |
49 |
|
T22 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7848489 |
1 |
|
|
T19 |
183 |
|
T20 |
1009 |
|
T21 |
946 |
| auto[1] |
5539182 |
1 |
|
|
T19 |
164 |
|
T20 |
1343 |
|
T22 |
31 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2419907 |
1 |
|
|
T19 |
90 |
|
T20 |
714 |
|
T22 |
25 |
| auto[1] |
auto[0] |
auto[1] |
354699 |
1 |
|
|
T19 |
5 |
|
T20 |
20 |
|
T22 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2410751 |
1 |
|
|
T19 |
66 |
|
T20 |
580 |
|
T22 |
5 |
| auto[1] |
auto[1] |
auto[1] |
353825 |
1 |
|
|
T19 |
3 |
|
T20 |
29 |
|
T25 |
15303 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |