Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7853745 |
1 |
|
|
T19 |
183 |
|
T20 |
967 |
|
T21 |
946 |
| auto[1] |
5533926 |
1 |
|
|
T19 |
164 |
|
T20 |
1385 |
|
T22 |
22 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12684472 |
1 |
|
|
T19 |
330 |
|
T20 |
2299 |
|
T21 |
946 |
| auto[1] |
703199 |
1 |
|
|
T19 |
17 |
|
T20 |
53 |
|
T25 |
31155 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7876418 |
1 |
|
|
T19 |
105 |
|
T20 |
926 |
|
T21 |
946 |
| auto[1] |
5511253 |
1 |
|
|
T19 |
242 |
|
T20 |
1426 |
|
T22 |
15 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2419882 |
1 |
|
|
T19 |
102 |
|
T20 |
592 |
|
T22 |
9 |
| auto[1] |
auto[0] |
auto[1] |
355570 |
1 |
|
|
T19 |
8 |
|
T20 |
17 |
|
T25 |
15287 |
| auto[1] |
auto[1] |
auto[0] |
2388172 |
1 |
|
|
T19 |
123 |
|
T20 |
781 |
|
T22 |
6 |
| auto[1] |
auto[1] |
auto[1] |
347629 |
1 |
|
|
T19 |
9 |
|
T20 |
36 |
|
T25 |
15868 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |