Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.63 99.06 99.24 100.00 99.80 99.68 99.99


Total test records in report: 941
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html
T767 /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.3151076124 Jul 30 06:42:39 PM PDT 24 Jul 30 06:42:40 PM PDT 24 53770030 ps
T95 /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.1410056348 Jul 30 06:42:36 PM PDT 24 Jul 30 06:42:37 PM PDT 24 52183473 ps
T768 /workspace/coverage/cover_reg_top/6.gpio_csr_rw.2840391009 Jul 30 06:42:31 PM PDT 24 Jul 30 06:42:32 PM PDT 24 13565103 ps
T769 /workspace/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.185015323 Jul 30 06:42:37 PM PDT 24 Jul 30 06:42:38 PM PDT 24 84245166 ps
T81 /workspace/coverage/cover_reg_top/4.gpio_csr_rw.1968772536 Jul 30 06:42:31 PM PDT 24 Jul 30 06:42:32 PM PDT 24 46196929 ps
T82 /workspace/coverage/cover_reg_top/8.gpio_csr_rw.3008246098 Jul 30 06:42:37 PM PDT 24 Jul 30 06:42:38 PM PDT 24 30512178 ps
T770 /workspace/coverage/cover_reg_top/6.gpio_tl_errors.2423157947 Jul 30 06:42:42 PM PDT 24 Jul 30 06:42:45 PM PDT 24 65151721 ps
T771 /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.2579590687 Jul 30 06:42:42 PM PDT 24 Jul 30 06:42:43 PM PDT 24 35348429 ps
T772 /workspace/coverage/cover_reg_top/46.gpio_intr_test.2561424091 Jul 30 06:42:39 PM PDT 24 Jul 30 06:42:40 PM PDT 24 26785692 ps
T773 /workspace/coverage/cover_reg_top/30.gpio_intr_test.1150369479 Jul 30 06:42:31 PM PDT 24 Jul 30 06:42:37 PM PDT 24 23241670 ps
T774 /workspace/coverage/cover_reg_top/10.gpio_intr_test.2515740839 Jul 30 06:42:37 PM PDT 24 Jul 30 06:42:38 PM PDT 24 13094870 ps
T775 /workspace/coverage/cover_reg_top/11.gpio_intr_test.2169001273 Jul 30 06:42:30 PM PDT 24 Jul 30 06:42:31 PM PDT 24 24133690 ps
T776 /workspace/coverage/cover_reg_top/25.gpio_intr_test.226130150 Jul 30 06:42:25 PM PDT 24 Jul 30 06:42:26 PM PDT 24 43550553 ps
T96 /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.1038308203 Jul 30 06:42:30 PM PDT 24 Jul 30 06:42:31 PM PDT 24 39349195 ps
T97 /workspace/coverage/cover_reg_top/9.gpio_same_csr_outstanding.1137120304 Jul 30 06:42:43 PM PDT 24 Jul 30 06:42:44 PM PDT 24 24906545 ps
T83 /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.4089390036 Jul 30 06:42:30 PM PDT 24 Jul 30 06:42:31 PM PDT 24 29627879 ps
T777 /workspace/coverage/cover_reg_top/43.gpio_intr_test.2152037387 Jul 30 06:42:44 PM PDT 24 Jul 30 06:42:45 PM PDT 24 19446318 ps
T778 /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.1777153848 Jul 30 06:42:28 PM PDT 24 Jul 30 06:42:29 PM PDT 24 43038809 ps
T779 /workspace/coverage/cover_reg_top/36.gpio_intr_test.1651087858 Jul 30 06:42:45 PM PDT 24 Jul 30 06:42:46 PM PDT 24 26595574 ps
T780 /workspace/coverage/cover_reg_top/26.gpio_intr_test.2362364156 Jul 30 06:42:33 PM PDT 24 Jul 30 06:42:34 PM PDT 24 23630191 ps
T47 /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.1664647293 Jul 30 06:42:30 PM PDT 24 Jul 30 06:42:31 PM PDT 24 49528333 ps
T781 /workspace/coverage/cover_reg_top/21.gpio_intr_test.2025402732 Jul 30 06:42:42 PM PDT 24 Jul 30 06:42:43 PM PDT 24 39339622 ps
T782 /workspace/coverage/cover_reg_top/19.gpio_intr_test.713145571 Jul 30 06:42:45 PM PDT 24 Jul 30 06:42:46 PM PDT 24 14846597 ps
T783 /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.373642051 Jul 30 06:42:35 PM PDT 24 Jul 30 06:42:36 PM PDT 24 15572704 ps
T84 /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.25691625 Jul 30 06:42:36 PM PDT 24 Jul 30 06:42:37 PM PDT 24 14619017 ps
T46 /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.1418503351 Jul 30 06:42:32 PM PDT 24 Jul 30 06:42:33 PM PDT 24 359656669 ps
T85 /workspace/coverage/cover_reg_top/9.gpio_csr_rw.1676471641 Jul 30 06:43:40 PM PDT 24 Jul 30 06:43:41 PM PDT 24 10883015 ps
T103 /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.366005170 Jul 30 06:42:42 PM PDT 24 Jul 30 06:42:43 PM PDT 24 708528857 ps
T784 /workspace/coverage/cover_reg_top/13.gpio_tl_errors.3360317673 Jul 30 06:42:39 PM PDT 24 Jul 30 06:42:43 PM PDT 24 271899163 ps
T785 /workspace/coverage/cover_reg_top/7.gpio_tl_errors.1697569590 Jul 30 06:42:43 PM PDT 24 Jul 30 06:42:45 PM PDT 24 51347604 ps
T786 /workspace/coverage/cover_reg_top/15.gpio_tl_errors.2025711242 Jul 30 06:42:37 PM PDT 24 Jul 30 06:42:39 PM PDT 24 333417202 ps
T787 /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.1081423063 Jul 30 06:42:32 PM PDT 24 Jul 30 06:42:34 PM PDT 24 384346447 ps
T788 /workspace/coverage/cover_reg_top/7.gpio_intr_test.116555380 Jul 30 06:42:38 PM PDT 24 Jul 30 06:42:39 PM PDT 24 61519026 ps
T789 /workspace/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.4096141974 Jul 30 06:42:31 PM PDT 24 Jul 30 06:42:33 PM PDT 24 72205600 ps
T89 /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.3636580339 Jul 30 06:42:38 PM PDT 24 Jul 30 06:42:40 PM PDT 24 312912487 ps
T790 /workspace/coverage/cover_reg_top/3.gpio_tl_errors.859300149 Jul 30 06:42:30 PM PDT 24 Jul 30 06:42:32 PM PDT 24 80646228 ps
T791 /workspace/coverage/cover_reg_top/13.gpio_csr_rw.4142745475 Jul 30 06:42:37 PM PDT 24 Jul 30 06:42:38 PM PDT 24 30159432 ps
T86 /workspace/coverage/cover_reg_top/1.gpio_csr_rw.108011434 Jul 30 06:42:27 PM PDT 24 Jul 30 06:42:28 PM PDT 24 23753809 ps
T792 /workspace/coverage/cover_reg_top/2.gpio_intr_test.3318748152 Jul 30 06:42:37 PM PDT 24 Jul 30 06:42:38 PM PDT 24 19841337 ps
T793 /workspace/coverage/cover_reg_top/44.gpio_intr_test.1470455159 Jul 30 06:42:34 PM PDT 24 Jul 30 06:42:35 PM PDT 24 16819284 ps
T794 /workspace/coverage/cover_reg_top/14.gpio_tl_errors.620337761 Jul 30 06:42:26 PM PDT 24 Jul 30 06:42:29 PM PDT 24 96247492 ps
T795 /workspace/coverage/cover_reg_top/17.gpio_tl_errors.259410873 Jul 30 06:43:36 PM PDT 24 Jul 30 06:43:37 PM PDT 24 170659679 ps
T796 /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.4214691265 Jul 30 06:42:35 PM PDT 24 Jul 30 06:42:36 PM PDT 24 28191596 ps
T797 /workspace/coverage/cover_reg_top/33.gpio_intr_test.4104436706 Jul 30 06:42:34 PM PDT 24 Jul 30 06:42:40 PM PDT 24 36110967 ps
T798 /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.166757571 Jul 30 06:42:35 PM PDT 24 Jul 30 06:42:36 PM PDT 24 163350962 ps
T799 /workspace/coverage/cover_reg_top/40.gpio_intr_test.142760130 Jul 30 06:42:35 PM PDT 24 Jul 30 06:42:35 PM PDT 24 17555305 ps
T800 /workspace/coverage/cover_reg_top/16.gpio_tl_intg_err.4006683554 Jul 30 06:42:34 PM PDT 24 Jul 30 06:42:36 PM PDT 24 45161409 ps
T801 /workspace/coverage/cover_reg_top/6.gpio_intr_test.1758497295 Jul 30 06:42:38 PM PDT 24 Jul 30 06:42:39 PM PDT 24 249896903 ps
T802 /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.1352606941 Jul 30 06:42:28 PM PDT 24 Jul 30 06:42:30 PM PDT 24 2137095576 ps
T87 /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.323909609 Jul 30 06:42:29 PM PDT 24 Jul 30 06:42:29 PM PDT 24 28004377 ps
T803 /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.3759542647 Jul 30 06:42:37 PM PDT 24 Jul 30 06:42:38 PM PDT 24 141891107 ps
T804 /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.665190559 Jul 30 06:42:34 PM PDT 24 Jul 30 06:42:34 PM PDT 24 16259945 ps
T805 /workspace/coverage/cover_reg_top/32.gpio_intr_test.1386793621 Jul 30 06:42:44 PM PDT 24 Jul 30 06:42:45 PM PDT 24 64744069 ps
T88 /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.2095282602 Jul 30 06:42:27 PM PDT 24 Jul 30 06:42:28 PM PDT 24 26521015 ps
T806 /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.4166544778 Jul 30 06:42:38 PM PDT 24 Jul 30 06:42:39 PM PDT 24 29451599 ps
T807 /workspace/coverage/cover_reg_top/0.gpio_tl_errors.3033266160 Jul 30 06:42:26 PM PDT 24 Jul 30 06:42:29 PM PDT 24 462229536 ps
T808 /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.549219464 Jul 30 06:42:32 PM PDT 24 Jul 30 06:42:33 PM PDT 24 14716490 ps
T809 /workspace/coverage/cover_reg_top/27.gpio_intr_test.913563672 Jul 30 06:42:36 PM PDT 24 Jul 30 06:42:37 PM PDT 24 15656816 ps
T810 /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.3087399903 Jul 30 06:42:43 PM PDT 24 Jul 30 06:42:45 PM PDT 24 112471857 ps
T811 /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.1362452931 Jul 30 06:42:40 PM PDT 24 Jul 30 06:42:41 PM PDT 24 56433564 ps
T812 /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.540074298 Jul 30 06:42:32 PM PDT 24 Jul 30 06:42:34 PM PDT 24 127740562 ps
T813 /workspace/coverage/cover_reg_top/15.gpio_intr_test.3387138630 Jul 30 06:42:37 PM PDT 24 Jul 30 06:42:38 PM PDT 24 36419471 ps
T814 /workspace/coverage/cover_reg_top/3.gpio_intr_test.2313699282 Jul 30 06:42:38 PM PDT 24 Jul 30 06:42:39 PM PDT 24 23706806 ps
T815 /workspace/coverage/cover_reg_top/37.gpio_intr_test.3980967831 Jul 30 06:42:54 PM PDT 24 Jul 30 06:42:54 PM PDT 24 31892366 ps
T816 /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.2694489916 Jul 30 06:42:27 PM PDT 24 Jul 30 06:42:28 PM PDT 24 476701987 ps
T817 /workspace/coverage/cover_reg_top/11.gpio_csr_mem_rw_with_rand_reset.2095508873 Jul 30 06:43:33 PM PDT 24 Jul 30 06:43:34 PM PDT 24 44949271 ps
T818 /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.367673146 Jul 30 06:42:28 PM PDT 24 Jul 30 06:42:29 PM PDT 24 21476474 ps
T819 /workspace/coverage/cover_reg_top/31.gpio_intr_test.1492292793 Jul 30 06:42:31 PM PDT 24 Jul 30 06:42:32 PM PDT 24 71135026 ps
T820 /workspace/coverage/cover_reg_top/11.gpio_same_csr_outstanding.3645700612 Jul 30 06:42:30 PM PDT 24 Jul 30 06:42:31 PM PDT 24 25344469 ps
T821 /workspace/coverage/cover_reg_top/8.gpio_same_csr_outstanding.4168313730 Jul 30 06:42:32 PM PDT 24 Jul 30 06:42:33 PM PDT 24 15956838 ps
T90 /workspace/coverage/cover_reg_top/10.gpio_csr_rw.3673825322 Jul 30 06:42:37 PM PDT 24 Jul 30 06:42:38 PM PDT 24 12674964 ps
T822 /workspace/coverage/cover_reg_top/4.gpio_intr_test.720454540 Jul 30 06:42:37 PM PDT 24 Jul 30 06:42:37 PM PDT 24 15702231 ps
T823 /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.2049392886 Jul 30 06:42:38 PM PDT 24 Jul 30 06:42:39 PM PDT 24 148440409 ps
T824 /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.1416387917 Jul 30 06:42:30 PM PDT 24 Jul 30 06:42:31 PM PDT 24 16373649 ps
T825 /workspace/coverage/cover_reg_top/8.gpio_tl_errors.4113266365 Jul 30 06:42:32 PM PDT 24 Jul 30 06:42:33 PM PDT 24 19307051 ps
T826 /workspace/coverage/cover_reg_top/0.gpio_csr_rw.2478365757 Jul 30 06:42:28 PM PDT 24 Jul 30 06:42:28 PM PDT 24 35878441 ps
T827 /workspace/coverage/cover_reg_top/0.gpio_intr_test.4081171717 Jul 30 06:42:29 PM PDT 24 Jul 30 06:42:30 PM PDT 24 47784242 ps
T828 /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.3638783803 Jul 30 06:42:29 PM PDT 24 Jul 30 06:42:31 PM PDT 24 67672730 ps
T829 /workspace/coverage/cover_reg_top/14.gpio_intr_test.2704242528 Jul 30 06:42:34 PM PDT 24 Jul 30 06:42:35 PM PDT 24 41700747 ps
T830 /workspace/coverage/cover_reg_top/16.gpio_intr_test.3461925254 Jul 30 06:42:42 PM PDT 24 Jul 30 06:42:42 PM PDT 24 16061601 ps
T831 /workspace/coverage/cover_reg_top/12.gpio_tl_errors.58758871 Jul 30 06:42:30 PM PDT 24 Jul 30 06:42:32 PM PDT 24 275461642 ps
T832 /workspace/coverage/cover_reg_top/12.gpio_same_csr_outstanding.2456098430 Jul 30 06:42:29 PM PDT 24 Jul 30 06:42:30 PM PDT 24 133860185 ps
T833 /workspace/coverage/cover_reg_top/1.gpio_csr_aliasing.1958134485 Jul 30 06:42:26 PM PDT 24 Jul 30 06:42:27 PM PDT 24 20081802 ps
T834 /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.1839240583 Jul 30 06:42:31 PM PDT 24 Jul 30 06:42:33 PM PDT 24 175050576 ps
T835 /workspace/coverage/cover_reg_top/49.gpio_intr_test.444442627 Jul 30 06:42:35 PM PDT 24 Jul 30 06:42:36 PM PDT 24 27323855 ps
T836 /workspace/coverage/cover_reg_top/3.gpio_same_csr_outstanding.3099959514 Jul 30 06:42:33 PM PDT 24 Jul 30 06:42:34 PM PDT 24 46501873 ps
T837 /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.851675912 Jul 30 06:42:36 PM PDT 24 Jul 30 06:42:37 PM PDT 24 17520465 ps
T838 /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.4231317500 Jul 30 06:43:33 PM PDT 24 Jul 30 06:43:34 PM PDT 24 20268021 ps
T839 /workspace/coverage/cover_reg_top/10.gpio_tl_errors.2221820875 Jul 30 06:42:31 PM PDT 24 Jul 30 06:42:39 PM PDT 24 100009563 ps
T840 /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.4003488741 Jul 30 06:42:31 PM PDT 24 Jul 30 06:42:33 PM PDT 24 108039257 ps
T841 /workspace/coverage/cover_reg_top/4.gpio_tl_errors.1509853121 Jul 30 06:42:26 PM PDT 24 Jul 30 06:42:29 PM PDT 24 63398478 ps
T842 /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.2886047413 Jul 30 05:57:05 PM PDT 24 Jul 30 05:57:06 PM PDT 24 100915920 ps
T843 /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1082874401 Jul 30 05:56:50 PM PDT 24 Jul 30 05:56:52 PM PDT 24 63751158 ps
T844 /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3008531669 Jul 30 05:57:04 PM PDT 24 Jul 30 05:57:05 PM PDT 24 187250042 ps
T845 /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3199730230 Jul 30 05:56:47 PM PDT 24 Jul 30 05:56:48 PM PDT 24 658474478 ps
T846 /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.1526257141 Jul 30 05:56:53 PM PDT 24 Jul 30 05:56:55 PM PDT 24 215835371 ps
T847 /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.3923745926 Jul 30 05:57:02 PM PDT 24 Jul 30 05:57:03 PM PDT 24 603793067 ps
T848 /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.636681607 Jul 30 05:56:48 PM PDT 24 Jul 30 05:56:49 PM PDT 24 685749599 ps
T849 /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.3783769248 Jul 30 05:57:06 PM PDT 24 Jul 30 05:57:07 PM PDT 24 132897274 ps
T850 /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.3387752101 Jul 30 05:56:48 PM PDT 24 Jul 30 05:56:49 PM PDT 24 444149683 ps
T851 /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2571625817 Jul 30 05:57:05 PM PDT 24 Jul 30 05:57:06 PM PDT 24 124082256 ps
T852 /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.316159915 Jul 30 05:56:58 PM PDT 24 Jul 30 05:56:59 PM PDT 24 156960109 ps
T853 /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1980008899 Jul 30 05:56:59 PM PDT 24 Jul 30 05:57:00 PM PDT 24 238551998 ps
T854 /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1268137427 Jul 30 05:56:55 PM PDT 24 Jul 30 05:56:56 PM PDT 24 88283683 ps
T855 /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.1090954552 Jul 30 05:56:49 PM PDT 24 Jul 30 05:56:50 PM PDT 24 68336224 ps
T856 /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.3117677263 Jul 30 05:56:50 PM PDT 24 Jul 30 05:56:51 PM PDT 24 499887223 ps
T857 /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2669949987 Jul 30 05:56:50 PM PDT 24 Jul 30 05:56:51 PM PDT 24 216345261 ps
T858 /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.3505227599 Jul 30 05:57:02 PM PDT 24 Jul 30 05:57:04 PM PDT 24 146100491 ps
T859 /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.615119372 Jul 30 05:56:55 PM PDT 24 Jul 30 05:56:56 PM PDT 24 205429245 ps
T860 /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.671428129 Jul 30 05:57:04 PM PDT 24 Jul 30 05:57:05 PM PDT 24 280606731 ps
T861 /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3735260434 Jul 30 05:56:53 PM PDT 24 Jul 30 05:56:54 PM PDT 24 56641196 ps
T862 /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.3479393754 Jul 30 05:56:50 PM PDT 24 Jul 30 05:56:51 PM PDT 24 59011440 ps
T863 /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.928958284 Jul 30 05:56:59 PM PDT 24 Jul 30 05:57:01 PM PDT 24 77976654 ps
T864 /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1994284627 Jul 30 05:56:50 PM PDT 24 Jul 30 05:56:51 PM PDT 24 49891526 ps
T865 /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.1731588392 Jul 30 05:57:03 PM PDT 24 Jul 30 05:57:04 PM PDT 24 55648661 ps
T866 /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1707777494 Jul 30 05:56:50 PM PDT 24 Jul 30 05:56:51 PM PDT 24 229168397 ps
T867 /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.228224999 Jul 30 05:57:01 PM PDT 24 Jul 30 05:57:02 PM PDT 24 30578894 ps
T868 /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1252311441 Jul 30 05:56:56 PM PDT 24 Jul 30 05:56:58 PM PDT 24 40134493 ps
T869 /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.3590233241 Jul 30 05:56:53 PM PDT 24 Jul 30 05:56:54 PM PDT 24 67871603 ps
T870 /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.3380486269 Jul 30 05:56:43 PM PDT 24 Jul 30 05:56:44 PM PDT 24 77096361 ps
T871 /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.799254520 Jul 30 05:56:50 PM PDT 24 Jul 30 05:56:51 PM PDT 24 73908332 ps
T872 /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1895582616 Jul 30 05:57:00 PM PDT 24 Jul 30 05:57:01 PM PDT 24 238028282 ps
T873 /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.2978264407 Jul 30 05:57:01 PM PDT 24 Jul 30 05:57:02 PM PDT 24 200251576 ps
T874 /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.3511090752 Jul 30 05:57:01 PM PDT 24 Jul 30 05:57:03 PM PDT 24 113855598 ps
T875 /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.210327177 Jul 30 05:56:50 PM PDT 24 Jul 30 05:56:51 PM PDT 24 59202467 ps
T876 /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2536302791 Jul 30 05:57:01 PM PDT 24 Jul 30 05:57:03 PM PDT 24 258915019 ps
T877 /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2152471721 Jul 30 05:56:50 PM PDT 24 Jul 30 05:56:52 PM PDT 24 62390229 ps
T878 /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.541852339 Jul 30 05:56:46 PM PDT 24 Jul 30 05:56:47 PM PDT 24 43648805 ps
T879 /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2062824760 Jul 30 05:56:49 PM PDT 24 Jul 30 05:56:50 PM PDT 24 108157098 ps
T880 /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4153665109 Jul 30 05:56:48 PM PDT 24 Jul 30 05:56:49 PM PDT 24 48179527 ps
T881 /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.1231807043 Jul 30 05:56:57 PM PDT 24 Jul 30 05:56:59 PM PDT 24 460596100 ps
T882 /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2852004633 Jul 30 05:56:49 PM PDT 24 Jul 30 05:56:50 PM PDT 24 269593045 ps
T883 /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3744104967 Jul 30 05:56:46 PM PDT 24 Jul 30 05:56:48 PM PDT 24 346250943 ps
T884 /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.3539487225 Jul 30 05:56:54 PM PDT 24 Jul 30 05:56:55 PM PDT 24 67032952 ps
T885 /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.3716444659 Jul 30 05:56:46 PM PDT 24 Jul 30 05:56:47 PM PDT 24 53085171 ps
T886 /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1557815257 Jul 30 05:57:01 PM PDT 24 Jul 30 05:57:03 PM PDT 24 305121187 ps
T887 /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.1119169357 Jul 30 05:57:01 PM PDT 24 Jul 30 05:57:02 PM PDT 24 108200204 ps
T888 /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.306327594 Jul 30 05:56:59 PM PDT 24 Jul 30 05:57:00 PM PDT 24 188262472 ps
T889 /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.1274350323 Jul 30 05:56:47 PM PDT 24 Jul 30 05:56:48 PM PDT 24 35334940 ps
T890 /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.564771483 Jul 30 05:56:49 PM PDT 24 Jul 30 05:56:50 PM PDT 24 53258924 ps
T891 /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.3551811351 Jul 30 05:56:50 PM PDT 24 Jul 30 05:56:50 PM PDT 24 30654373 ps
T892 /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.2620555775 Jul 30 05:56:47 PM PDT 24 Jul 30 05:56:48 PM PDT 24 37432193 ps
T893 /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.153121096 Jul 30 05:57:03 PM PDT 24 Jul 30 05:57:04 PM PDT 24 74430567 ps
T894 /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.3558143620 Jul 30 05:56:52 PM PDT 24 Jul 30 05:56:54 PM PDT 24 324134139 ps
T895 /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.4058428993 Jul 30 05:56:54 PM PDT 24 Jul 30 05:56:56 PM PDT 24 95506998 ps
T896 /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.810782384 Jul 30 05:57:05 PM PDT 24 Jul 30 05:57:06 PM PDT 24 56438356 ps
T897 /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3159797779 Jul 30 05:56:53 PM PDT 24 Jul 30 05:56:54 PM PDT 24 58404185 ps
T898 /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1020983260 Jul 30 05:56:55 PM PDT 24 Jul 30 05:56:56 PM PDT 24 93109722 ps
T899 /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1073686671 Jul 30 05:56:57 PM PDT 24 Jul 30 05:56:59 PM PDT 24 262274396 ps
T900 /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1600686538 Jul 30 05:56:54 PM PDT 24 Jul 30 05:56:55 PM PDT 24 436917583 ps
T901 /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3361939665 Jul 30 05:56:52 PM PDT 24 Jul 30 05:56:53 PM PDT 24 854122614 ps
T902 /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.643950557 Jul 30 05:56:54 PM PDT 24 Jul 30 05:56:56 PM PDT 24 28730066 ps
T903 /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.1146324084 Jul 30 05:56:59 PM PDT 24 Jul 30 05:57:00 PM PDT 24 27771046 ps
T904 /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.2225839401 Jul 30 05:56:55 PM PDT 24 Jul 30 05:56:56 PM PDT 24 27983283 ps
T905 /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.351263303 Jul 30 05:57:01 PM PDT 24 Jul 30 05:57:02 PM PDT 24 57331764 ps
T906 /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.913711837 Jul 30 05:56:55 PM PDT 24 Jul 30 05:56:57 PM PDT 24 43980764 ps
T907 /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1878332845 Jul 30 05:57:02 PM PDT 24 Jul 30 05:57:03 PM PDT 24 137403055 ps
T908 /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.41276533 Jul 30 05:56:54 PM PDT 24 Jul 30 05:56:56 PM PDT 24 162639161 ps
T909 /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.1317228925 Jul 30 05:56:46 PM PDT 24 Jul 30 05:56:48 PM PDT 24 208298353 ps
T910 /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2529171976 Jul 30 05:56:56 PM PDT 24 Jul 30 05:56:57 PM PDT 24 35299204 ps
T911 /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1882940871 Jul 30 05:56:57 PM PDT 24 Jul 30 05:56:58 PM PDT 24 52540683 ps
T912 /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3609761614 Jul 30 05:57:05 PM PDT 24 Jul 30 05:57:06 PM PDT 24 213620242 ps
T913 /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.4250262948 Jul 30 05:56:57 PM PDT 24 Jul 30 05:56:58 PM PDT 24 28654837 ps
T914 /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.891440813 Jul 30 05:56:55 PM PDT 24 Jul 30 05:56:56 PM PDT 24 163464743 ps
T915 /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.982486493 Jul 30 05:56:47 PM PDT 24 Jul 30 05:56:48 PM PDT 24 233749094 ps
T916 /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.1145644884 Jul 30 05:56:56 PM PDT 24 Jul 30 05:56:58 PM PDT 24 74347540 ps
T917 /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.300796866 Jul 30 05:56:54 PM PDT 24 Jul 30 05:56:56 PM PDT 24 342554071 ps
T918 /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1866626902 Jul 30 05:56:53 PM PDT 24 Jul 30 05:56:54 PM PDT 24 342698639 ps
T919 /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.1012580448 Jul 30 05:56:45 PM PDT 24 Jul 30 05:56:46 PM PDT 24 106446873 ps
T920 /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.2204234751 Jul 30 05:56:50 PM PDT 24 Jul 30 05:56:51 PM PDT 24 83832419 ps
T921 /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2532156942 Jul 30 05:57:03 PM PDT 24 Jul 30 05:57:04 PM PDT 24 45276718 ps
T922 /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4225952990 Jul 30 05:57:04 PM PDT 24 Jul 30 05:57:05 PM PDT 24 42010419 ps
T923 /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.828846880 Jul 30 05:57:00 PM PDT 24 Jul 30 05:57:01 PM PDT 24 107633417 ps
T924 /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.2611974799 Jul 30 05:57:02 PM PDT 24 Jul 30 05:57:03 PM PDT 24 51062437 ps
T925 /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.4174806862 Jul 30 05:57:01 PM PDT 24 Jul 30 05:57:02 PM PDT 24 27912411 ps
T926 /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.2437284312 Jul 30 05:56:56 PM PDT 24 Jul 30 05:56:57 PM PDT 24 92764013 ps
T927 /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.2895609135 Jul 30 05:56:53 PM PDT 24 Jul 30 05:56:55 PM PDT 24 75938192 ps
T928 /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1811757904 Jul 30 05:56:50 PM PDT 24 Jul 30 05:56:52 PM PDT 24 59061912 ps
T929 /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.1391839659 Jul 30 05:57:05 PM PDT 24 Jul 30 05:57:07 PM PDT 24 466565361 ps
T930 /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3661182814 Jul 30 05:56:53 PM PDT 24 Jul 30 05:56:54 PM PDT 24 69757834 ps
T931 /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3026809290 Jul 30 05:56:52 PM PDT 24 Jul 30 05:56:53 PM PDT 24 49241607 ps
T932 /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.3297322714 Jul 30 05:57:02 PM PDT 24 Jul 30 05:57:03 PM PDT 24 41021660 ps
T933 /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3753754867 Jul 30 05:56:55 PM PDT 24 Jul 30 05:56:56 PM PDT 24 196720346 ps
T934 /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1591375275 Jul 30 05:56:57 PM PDT 24 Jul 30 05:56:59 PM PDT 24 74218373 ps
T935 /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1912193394 Jul 30 05:57:02 PM PDT 24 Jul 30 05:57:03 PM PDT 24 35052182 ps
T936 /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.472147510 Jul 30 05:57:02 PM PDT 24 Jul 30 05:57:03 PM PDT 24 45081869 ps
T937 /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.1507746623 Jul 30 05:56:53 PM PDT 24 Jul 30 05:56:54 PM PDT 24 325554791 ps
T938 /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.1317492516 Jul 30 05:56:49 PM PDT 24 Jul 30 05:56:50 PM PDT 24 113548223 ps
T939 /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1106573347 Jul 30 05:56:46 PM PDT 24 Jul 30 05:56:47 PM PDT 24 131480834 ps
T940 /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4084719524 Jul 30 05:57:00 PM PDT 24 Jul 30 05:57:01 PM PDT 24 213034406 ps
T941 /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.2167471372 Jul 30 05:56:51 PM PDT 24 Jul 30 05:56:52 PM PDT 24 103287034 ps

Test location /workspace/coverage/default/48.gpio_stress_all_with_rand_reset.2219906584
Short name T25
Test name
Test status
Simulation time 410679126684 ps
CPU time 1051.05 seconds
Started Jul 30 06:03:15 PM PDT 24
Finished Jul 30 06:20:46 PM PDT 24
Peak memory 207020 kb
Host smart-76f4ff6c-82ba-4ea1-b4ae-a6b6dfa009bb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2219906584 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_stress_all_with_rand_reset.2219906584
Directory /workspace/48.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.gpio_intr_with_filter_rand_intr_event.1872329314
Short name T114
Test name
Test status
Simulation time 181228177 ps
CPU time 3.85 seconds
Started Jul 30 06:02:53 PM PDT 24
Finished Jul 30 06:02:57 PM PDT 24
Peak memory 198600 kb
Host smart-7908a5e8-71d9-4e5c-8b1d-2b9278c8daae
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872329314 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 39.gpio_intr_with_filter_rand_intr_event.1872329314
Directory /workspace/39.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/4.gpio_sec_cm.2759248505
Short name T27
Test name
Test status
Simulation time 223587160 ps
CPU time 0.85 seconds
Started Jul 30 06:01:50 PM PDT 24
Finished Jul 30 06:01:51 PM PDT 24
Peak memory 214428 kb
Host smart-0c526687-5041-46fb-ba1d-430782440f6d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759248505 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_sec_cm.2759248505
Directory /workspace/4.gpio_sec_cm/latest

Test location /workspace/coverage/default/0.gpio_stress_all_with_rand_reset.991284857
Short name T9
Test name
Test status
Simulation time 39754924471 ps
CPU time 510.85 seconds
Started Jul 30 06:01:46 PM PDT 24
Finished Jul 30 06:10:17 PM PDT 24
Peak memory 198852 kb
Host smart-b8954343-9603-45ba-9331-ff9033b5ecce
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=991284857 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_stress_all_with_rand_reset.991284857
Directory /workspace/0.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.25691625
Short name T84
Test name
Test status
Simulation time 14619017 ps
CPU time 0.69 seconds
Started Jul 30 06:42:36 PM PDT 24
Finished Jul 30 06:42:37 PM PDT 24
Peak memory 195820 kb
Host smart-32ca95f9-cc45-4c56-ae4b-fb7b015d8af6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25691625 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.
gpio_csr_aliasing.25691625
Directory /workspace/4.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.1272217650
Short name T43
Test name
Test status
Simulation time 600036751 ps
CPU time 1.32 seconds
Started Jul 30 06:43:36 PM PDT 24
Finished Jul 30 06:43:37 PM PDT 24
Peak memory 198584 kb
Host smart-2d570441-dba5-454c-8a3e-ee8473d4c522
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272217650 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 15.gpio_tl_intg_err.1272217650
Directory /workspace/15.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/11.gpio_alert_test.3798002564
Short name T181
Test name
Test status
Simulation time 22114682 ps
CPU time 0.56 seconds
Started Jul 30 06:01:59 PM PDT 24
Finished Jul 30 06:01:59 PM PDT 24
Peak memory 194628 kb
Host smart-b22feb63-f5d8-4edb-9058-d6b737b36855
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798002564 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_alert_test.3798002564
Directory /workspace/11.gpio_alert_test/latest

Test location /workspace/coverage/default/3.gpio_dout_din_regs_random_rw.3297063005
Short name T26
Test name
Test status
Simulation time 70986187 ps
CPU time 0.67 seconds
Started Jul 30 06:01:49 PM PDT 24
Finished Jul 30 06:01:50 PM PDT 24
Peak memory 194688 kb
Host smart-418e8701-6319-4583-af45-d6bd1c875b66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3297063005 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_dout_din_regs_random_rw.3297063005
Directory /workspace/3.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.1038308203
Short name T96
Test name
Test status
Simulation time 39349195 ps
CPU time 0.86 seconds
Started Jul 30 06:42:30 PM PDT 24
Finished Jul 30 06:42:31 PM PDT 24
Peak memory 197612 kb
Host smart-1a18055a-21a7-4736-afe0-2e795dceb796
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038308203 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 1.gpio_same_csr_outstanding.1038308203
Directory /workspace/1.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.540074298
Short name T812
Test name
Test status
Simulation time 127740562 ps
CPU time 1.12 seconds
Started Jul 30 06:42:32 PM PDT 24
Finished Jul 30 06:42:34 PM PDT 24
Peak memory 198748 kb
Host smart-a62c6ad7-14fb-4bd3-bca2-f17578c0eae3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540074298 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 19.gpio_tl_intg_err.540074298
Directory /workspace/19.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.3759542647
Short name T803
Test name
Test status
Simulation time 141891107 ps
CPU time 1.36 seconds
Started Jul 30 06:42:37 PM PDT 24
Finished Jul 30 06:42:38 PM PDT 24
Peak memory 198428 kb
Host smart-861f0d2c-6872-44f9-aeec-ae3ce5fcf879
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759542647 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 11.gpio_tl_intg_err.3759542647
Directory /workspace/11.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.323909609
Short name T87
Test name
Test status
Simulation time 28004377 ps
CPU time 0.76 seconds
Started Jul 30 06:42:29 PM PDT 24
Finished Jul 30 06:42:29 PM PDT 24
Peak memory 197292 kb
Host smart-b65e3a2a-f149-4e9a-ad3d-78025b8ad8da
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323909609 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0
.gpio_csr_aliasing.323909609
Directory /workspace/0.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.2895765614
Short name T765
Test name
Test status
Simulation time 34127955 ps
CPU time 1.41 seconds
Started Jul 30 06:42:39 PM PDT 24
Finished Jul 30 06:42:41 PM PDT 24
Peak memory 198644 kb
Host smart-111b6043-b203-4876-9727-f3c50b8abe28
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895765614 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_bit_bash.2895765614
Directory /workspace/0.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.2095282602
Short name T88
Test name
Test status
Simulation time 26521015 ps
CPU time 0.65 seconds
Started Jul 30 06:42:27 PM PDT 24
Finished Jul 30 06:42:28 PM PDT 24
Peak memory 196316 kb
Host smart-14580b5e-9159-443f-a214-57690786bc6e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095282602 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_hw_reset.2095282602
Directory /workspace/0.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.4096141974
Short name T789
Test name
Test status
Simulation time 72205600 ps
CPU time 0.97 seconds
Started Jul 30 06:42:31 PM PDT 24
Finished Jul 30 06:42:33 PM PDT 24
Peak memory 198788 kb
Host smart-ae893b7e-53b0-4837-a0bd-3f75f2caa2d7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096141974 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_mem_rw_with_rand_reset.4096141974
Directory /workspace/0.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_rw.2478365757
Short name T826
Test name
Test status
Simulation time 35878441 ps
CPU time 0.6 seconds
Started Jul 30 06:42:28 PM PDT 24
Finished Jul 30 06:42:28 PM PDT 24
Peak memory 195476 kb
Host smart-4c9d6638-8e80-4da7-8ec6-4b92f925269e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478365757 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio
_csr_rw.2478365757
Directory /workspace/0.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_intr_test.4081171717
Short name T827
Test name
Test status
Simulation time 47784242 ps
CPU time 0.6 seconds
Started Jul 30 06:42:29 PM PDT 24
Finished Jul 30 06:42:30 PM PDT 24
Peak memory 194496 kb
Host smart-cb18c857-ccc6-45c7-8503-a9f3de3c1747
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081171717 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_intr_test.4081171717
Directory /workspace/0.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.1777153848
Short name T778
Test name
Test status
Simulation time 43038809 ps
CPU time 0.72 seconds
Started Jul 30 06:42:28 PM PDT 24
Finished Jul 30 06:42:29 PM PDT 24
Peak memory 197504 kb
Host smart-1202373c-df98-4ed6-8cb2-15785fc2d13d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777153848 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 0.gpio_same_csr_outstanding.1777153848
Directory /workspace/0.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_errors.3033266160
Short name T807
Test name
Test status
Simulation time 462229536 ps
CPU time 2.24 seconds
Started Jul 30 06:42:26 PM PDT 24
Finished Jul 30 06:42:29 PM PDT 24
Peak memory 198780 kb
Host smart-067f37a6-1729-44c2-a599-19432541272c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033266160 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_tl_errors.3033266160
Directory /workspace/0.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.1081423063
Short name T787
Test name
Test status
Simulation time 384346447 ps
CPU time 1.36 seconds
Started Jul 30 06:42:32 PM PDT 24
Finished Jul 30 06:42:34 PM PDT 24
Peak memory 198660 kb
Host smart-d85c7ce1-6fee-4ed7-babd-799fb5146f8f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081423063 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 0.gpio_tl_intg_err.1081423063
Directory /workspace/0.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_aliasing.1958134485
Short name T833
Test name
Test status
Simulation time 20081802 ps
CPU time 0.66 seconds
Started Jul 30 06:42:26 PM PDT 24
Finished Jul 30 06:42:27 PM PDT 24
Peak memory 195128 kb
Host smart-e6120146-be91-44f3-833f-397e34343df8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958134485 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
1.gpio_csr_aliasing.1958134485
Directory /workspace/1.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.1352606941
Short name T802
Test name
Test status
Simulation time 2137095576 ps
CPU time 2.36 seconds
Started Jul 30 06:42:28 PM PDT 24
Finished Jul 30 06:42:30 PM PDT 24
Peak memory 197320 kb
Host smart-07b643df-4205-4b05-9c00-753beae6871b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352606941 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_bit_bash.1352606941
Directory /workspace/1.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_hw_reset.2931273209
Short name T757
Test name
Test status
Simulation time 13988451 ps
CPU time 0.61 seconds
Started Jul 30 06:42:27 PM PDT 24
Finished Jul 30 06:42:28 PM PDT 24
Peak memory 196124 kb
Host smart-db3246c1-2d87-424e-ba2c-04239c5d35be
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931273209 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_hw_reset.2931273209
Directory /workspace/1.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.3151076124
Short name T767
Test name
Test status
Simulation time 53770030 ps
CPU time 0.71 seconds
Started Jul 30 06:42:39 PM PDT 24
Finished Jul 30 06:42:40 PM PDT 24
Peak memory 198612 kb
Host smart-846e74dc-3e7c-4e6e-a759-35a46c14c3db
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151076124 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_mem_rw_with_rand_reset.3151076124
Directory /workspace/1.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_rw.108011434
Short name T86
Test name
Test status
Simulation time 23753809 ps
CPU time 0.58 seconds
Started Jul 30 06:42:27 PM PDT 24
Finished Jul 30 06:42:28 PM PDT 24
Peak memory 194720 kb
Host smart-cc9e7255-5c84-4914-8484-2ca69b174a13
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108011434 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_
csr_rw.108011434
Directory /workspace/1.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_intr_test.405026872
Short name T766
Test name
Test status
Simulation time 12960258 ps
CPU time 0.59 seconds
Started Jul 30 06:42:27 PM PDT 24
Finished Jul 30 06:42:28 PM PDT 24
Peak memory 194484 kb
Host smart-a0f4daef-5d91-4638-8015-c28d76362c2e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405026872 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_intr_test.405026872
Directory /workspace/1.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_errors.2344624180
Short name T716
Test name
Test status
Simulation time 89429981 ps
CPU time 1.75 seconds
Started Jul 30 06:42:28 PM PDT 24
Finished Jul 30 06:42:30 PM PDT 24
Peak memory 198780 kb
Host smart-f0466eff-8373-4aa8-81d2-727d6363e42f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344624180 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_tl_errors.2344624180
Directory /workspace/1.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_intg_err.2722275315
Short name T45
Test name
Test status
Simulation time 64004453 ps
CPU time 0.92 seconds
Started Jul 30 06:42:35 PM PDT 24
Finished Jul 30 06:42:36 PM PDT 24
Peak memory 197464 kb
Host smart-ddc4008d-26d0-443c-ab4e-23b17c41381b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722275315 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 1.gpio_tl_intg_err.2722275315
Directory /workspace/1.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_mem_rw_with_rand_reset.1382387731
Short name T751
Test name
Test status
Simulation time 31394904 ps
CPU time 0.9 seconds
Started Jul 30 06:42:34 PM PDT 24
Finished Jul 30 06:42:36 PM PDT 24
Peak memory 198576 kb
Host smart-570b1a1b-2491-4050-80b8-fcdedc1d0190
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382387731 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_csr_mem_rw_with_rand_reset.1382387731
Directory /workspace/10.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_rw.3673825322
Short name T90
Test name
Test status
Simulation time 12674964 ps
CPU time 0.63 seconds
Started Jul 30 06:42:37 PM PDT 24
Finished Jul 30 06:42:38 PM PDT 24
Peak memory 195716 kb
Host smart-70200ffb-a081-4959-bd5b-651b0c3c1d96
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673825322 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpi
o_csr_rw.3673825322
Directory /workspace/10.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_intr_test.2515740839
Short name T774
Test name
Test status
Simulation time 13094870 ps
CPU time 0.58 seconds
Started Jul 30 06:42:37 PM PDT 24
Finished Jul 30 06:42:38 PM PDT 24
Peak memory 194484 kb
Host smart-09208977-e10a-4a38-9d3e-f7d01cc512ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515740839 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_intr_test.2515740839
Directory /workspace/10.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.128212333
Short name T93
Test name
Test status
Simulation time 41499192 ps
CPU time 0.77 seconds
Started Jul 30 06:42:46 PM PDT 24
Finished Jul 30 06:42:47 PM PDT 24
Peak memory 196456 kb
Host smart-3903a86b-e65d-4890-8288-74b690935426
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128212333 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 10.gpio_same_csr_outstanding.128212333
Directory /workspace/10.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_errors.2221820875
Short name T839
Test name
Test status
Simulation time 100009563 ps
CPU time 2.38 seconds
Started Jul 30 06:42:31 PM PDT 24
Finished Jul 30 06:42:39 PM PDT 24
Peak memory 198852 kb
Host smart-c0ae7a54-b455-4b39-ae74-b7e654edf934
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221820875 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_tl_errors.2221820875
Directory /workspace/10.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.3087399903
Short name T810
Test name
Test status
Simulation time 112471857 ps
CPU time 1.16 seconds
Started Jul 30 06:42:43 PM PDT 24
Finished Jul 30 06:42:45 PM PDT 24
Peak memory 198768 kb
Host smart-12b865cb-d9a0-42e0-b6b1-7db86d7d33ef
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087399903 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 10.gpio_tl_intg_err.3087399903
Directory /workspace/10.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_mem_rw_with_rand_reset.2095508873
Short name T817
Test name
Test status
Simulation time 44949271 ps
CPU time 0.85 seconds
Started Jul 30 06:43:33 PM PDT 24
Finished Jul 30 06:43:34 PM PDT 24
Peak memory 198468 kb
Host smart-ff38c12c-37ea-4047-9392-97d8049a5db6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095508873 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_csr_mem_rw_with_rand_reset.2095508873
Directory /workspace/11.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_rw.2138331823
Short name T101
Test name
Test status
Simulation time 12303779 ps
CPU time 0.57 seconds
Started Jul 30 06:42:33 PM PDT 24
Finished Jul 30 06:42:34 PM PDT 24
Peak memory 194116 kb
Host smart-994cbd6b-80c5-4b97-a810-6e7e0f8d9a5e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138331823 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpi
o_csr_rw.2138331823
Directory /workspace/11.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_intr_test.2169001273
Short name T775
Test name
Test status
Simulation time 24133690 ps
CPU time 0.58 seconds
Started Jul 30 06:42:30 PM PDT 24
Finished Jul 30 06:42:31 PM PDT 24
Peak memory 194560 kb
Host smart-746efd05-7de6-49e2-88ee-f24292643771
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169001273 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_intr_test.2169001273
Directory /workspace/11.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_same_csr_outstanding.3645700612
Short name T820
Test name
Test status
Simulation time 25344469 ps
CPU time 0.67 seconds
Started Jul 30 06:42:30 PM PDT 24
Finished Jul 30 06:42:31 PM PDT 24
Peak memory 195400 kb
Host smart-dd9b6ddc-059f-4f74-9c7b-af539de0a281
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645700612 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 11.gpio_same_csr_outstanding.3645700612
Directory /workspace/11.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_errors.2761619247
Short name T755
Test name
Test status
Simulation time 111428446 ps
CPU time 2.3 seconds
Started Jul 30 06:42:38 PM PDT 24
Finished Jul 30 06:42:40 PM PDT 24
Peak memory 198768 kb
Host smart-97182c4a-1b7d-415e-962a-e5799045efd6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761619247 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_tl_errors.2761619247
Directory /workspace/11.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.4003488741
Short name T840
Test name
Test status
Simulation time 108039257 ps
CPU time 1.61 seconds
Started Jul 30 06:42:31 PM PDT 24
Finished Jul 30 06:42:33 PM PDT 24
Peak memory 198916 kb
Host smart-8c648811-112b-4f9e-9b8d-c795af0317a7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003488741 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_csr_mem_rw_with_rand_reset.4003488741
Directory /workspace/12.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_rw.4127000350
Short name T748
Test name
Test status
Simulation time 19189010 ps
CPU time 0.61 seconds
Started Jul 30 06:42:31 PM PDT 24
Finished Jul 30 06:42:32 PM PDT 24
Peak memory 194744 kb
Host smart-705c1f62-593a-4c90-a06f-1c97e979b780
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127000350 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpi
o_csr_rw.4127000350
Directory /workspace/12.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_intr_test.2875127970
Short name T723
Test name
Test status
Simulation time 21794910 ps
CPU time 0.57 seconds
Started Jul 30 06:42:45 PM PDT 24
Finished Jul 30 06:42:46 PM PDT 24
Peak memory 195100 kb
Host smart-f3e86d72-1485-4a2a-86a9-7a580d3d6325
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875127970 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_intr_test.2875127970
Directory /workspace/12.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_same_csr_outstanding.2456098430
Short name T832
Test name
Test status
Simulation time 133860185 ps
CPU time 0.87 seconds
Started Jul 30 06:42:29 PM PDT 24
Finished Jul 30 06:42:30 PM PDT 24
Peak memory 197108 kb
Host smart-0b2ff115-2563-41cf-9cf5-54cbb1e54b01
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456098430 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 12.gpio_same_csr_outstanding.2456098430
Directory /workspace/12.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_errors.58758871
Short name T831
Test name
Test status
Simulation time 275461642 ps
CPU time 1.65 seconds
Started Jul 30 06:42:30 PM PDT 24
Finished Jul 30 06:42:32 PM PDT 24
Peak memory 198700 kb
Host smart-0adfc3d1-e17f-400d-83ef-6ac0b6ac842a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58758871 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_tl_errors.58758871
Directory /workspace/12.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.3638783803
Short name T828
Test name
Test status
Simulation time 67672730 ps
CPU time 0.93 seconds
Started Jul 30 06:42:29 PM PDT 24
Finished Jul 30 06:42:31 PM PDT 24
Peak memory 197700 kb
Host smart-34b4749d-f639-49bb-ab73-db001fe0086c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638783803 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 12.gpio_tl_intg_err.3638783803
Directory /workspace/12.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.2579590687
Short name T771
Test name
Test status
Simulation time 35348429 ps
CPU time 0.89 seconds
Started Jul 30 06:42:42 PM PDT 24
Finished Jul 30 06:42:43 PM PDT 24
Peak memory 198640 kb
Host smart-6cab03ab-830d-45b9-81db-6b4cfea18d70
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579590687 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_csr_mem_rw_with_rand_reset.2579590687
Directory /workspace/13.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_rw.4142745475
Short name T791
Test name
Test status
Simulation time 30159432 ps
CPU time 0.62 seconds
Started Jul 30 06:42:37 PM PDT 24
Finished Jul 30 06:42:38 PM PDT 24
Peak memory 195232 kb
Host smart-920a390e-800e-40af-80e5-e433560e404d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142745475 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpi
o_csr_rw.4142745475
Directory /workspace/13.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_intr_test.422070686
Short name T733
Test name
Test status
Simulation time 98010005 ps
CPU time 0.6 seconds
Started Jul 30 06:42:30 PM PDT 24
Finished Jul 30 06:42:30 PM PDT 24
Peak memory 195120 kb
Host smart-4bd465e3-d055-47f4-8d0a-91453614c34b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422070686 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_intr_test.422070686
Directory /workspace/13.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.1362452931
Short name T811
Test name
Test status
Simulation time 56433564 ps
CPU time 0.79 seconds
Started Jul 30 06:42:40 PM PDT 24
Finished Jul 30 06:42:41 PM PDT 24
Peak memory 196684 kb
Host smart-9a8b21e1-80b8-4e59-91d0-5624f0e5fd07
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362452931 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 13.gpio_same_csr_outstanding.1362452931
Directory /workspace/13.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_errors.3360317673
Short name T784
Test name
Test status
Simulation time 271899163 ps
CPU time 2.7 seconds
Started Jul 30 06:42:39 PM PDT 24
Finished Jul 30 06:42:43 PM PDT 24
Peak memory 198808 kb
Host smart-4c82726d-2630-455f-9ada-b4d29a4b92e1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360317673 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_tl_errors.3360317673
Directory /workspace/13.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_intg_err.3655089522
Short name T752
Test name
Test status
Simulation time 208796634 ps
CPU time 0.81 seconds
Started Jul 30 06:42:40 PM PDT 24
Finished Jul 30 06:42:41 PM PDT 24
Peak memory 197540 kb
Host smart-c77d5c8e-b805-4c8e-abc3-d426d719a08d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655089522 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 13.gpio_tl_intg_err.3655089522
Directory /workspace/13.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.1982483156
Short name T720
Test name
Test status
Simulation time 67287277 ps
CPU time 0.66 seconds
Started Jul 30 06:42:49 PM PDT 24
Finished Jul 30 06:42:50 PM PDT 24
Peak memory 197372 kb
Host smart-23c8fd74-e489-45c0-9bf3-8f3e1c2e8eff
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982483156 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_csr_mem_rw_with_rand_reset.1982483156
Directory /workspace/14.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_rw.3379876619
Short name T727
Test name
Test status
Simulation time 59173841 ps
CPU time 0.55 seconds
Started Jul 30 06:42:33 PM PDT 24
Finished Jul 30 06:42:34 PM PDT 24
Peak memory 195972 kb
Host smart-fec09dc8-b808-475b-9222-a8c37678fef3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379876619 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpi
o_csr_rw.3379876619
Directory /workspace/14.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_intr_test.2704242528
Short name T829
Test name
Test status
Simulation time 41700747 ps
CPU time 0.58 seconds
Started Jul 30 06:42:34 PM PDT 24
Finished Jul 30 06:42:35 PM PDT 24
Peak memory 194992 kb
Host smart-bc917904-4dcc-48f9-b8cc-a8331843de78
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704242528 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_intr_test.2704242528
Directory /workspace/14.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_same_csr_outstanding.4253379592
Short name T91
Test name
Test status
Simulation time 27938904 ps
CPU time 0.68 seconds
Started Jul 30 06:43:40 PM PDT 24
Finished Jul 30 06:43:41 PM PDT 24
Peak memory 195492 kb
Host smart-f6880e5d-2087-4063-90b4-3c0b9c3ee5c9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253379592 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 14.gpio_same_csr_outstanding.4253379592
Directory /workspace/14.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_errors.620337761
Short name T794
Test name
Test status
Simulation time 96247492 ps
CPU time 2.55 seconds
Started Jul 30 06:42:26 PM PDT 24
Finished Jul 30 06:42:29 PM PDT 24
Peak memory 198812 kb
Host smart-d00ec2d7-3aa4-438b-9c63-64fa6ff908a5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620337761 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_tl_errors.620337761
Directory /workspace/14.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_intg_err.1134840981
Short name T33
Test name
Test status
Simulation time 431289324 ps
CPU time 1.41 seconds
Started Jul 30 06:42:38 PM PDT 24
Finished Jul 30 06:42:40 PM PDT 24
Peak memory 198704 kb
Host smart-973c4340-e72d-4f22-966e-432de92b55b3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134840981 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 14.gpio_tl_intg_err.1134840981
Directory /workspace/14.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.2049392886
Short name T823
Test name
Test status
Simulation time 148440409 ps
CPU time 0.93 seconds
Started Jul 30 06:42:38 PM PDT 24
Finished Jul 30 06:42:39 PM PDT 24
Peak memory 198652 kb
Host smart-00875602-44b7-42c4-a71e-b13eb10d7677
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049392886 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_csr_mem_rw_with_rand_reset.2049392886
Directory /workspace/15.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_rw.2474114061
Short name T719
Test name
Test status
Simulation time 95152413 ps
CPU time 0.59 seconds
Started Jul 30 06:42:38 PM PDT 24
Finished Jul 30 06:42:39 PM PDT 24
Peak memory 195028 kb
Host smart-ef735e00-dc13-4c60-94cb-5071f46483fc
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474114061 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpi
o_csr_rw.2474114061
Directory /workspace/15.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_intr_test.3387138630
Short name T813
Test name
Test status
Simulation time 36419471 ps
CPU time 0.56 seconds
Started Jul 30 06:42:37 PM PDT 24
Finished Jul 30 06:42:38 PM PDT 24
Peak memory 194408 kb
Host smart-433c4c92-e304-415c-8d81-ec2c56f27949
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387138630 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_intr_test.3387138630
Directory /workspace/15.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.1228449282
Short name T79
Test name
Test status
Simulation time 30778683 ps
CPU time 0.71 seconds
Started Jul 30 06:42:32 PM PDT 24
Finished Jul 30 06:42:33 PM PDT 24
Peak memory 195664 kb
Host smart-60259453-b2d8-46d2-8d8e-824115caa789
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228449282 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 15.gpio_same_csr_outstanding.1228449282
Directory /workspace/15.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_errors.2025711242
Short name T786
Test name
Test status
Simulation time 333417202 ps
CPU time 1.71 seconds
Started Jul 30 06:42:37 PM PDT 24
Finished Jul 30 06:42:39 PM PDT 24
Peak memory 198780 kb
Host smart-a629bb24-4487-4773-9ce8-1273056fdbaa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025711242 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_tl_errors.2025711242
Directory /workspace/15.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.2588305364
Short name T730
Test name
Test status
Simulation time 168063030 ps
CPU time 1.01 seconds
Started Jul 30 06:42:36 PM PDT 24
Finished Jul 30 06:42:37 PM PDT 24
Peak memory 198624 kb
Host smart-6dad1f53-9d84-43b6-b3f1-a8d08aad8450
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588305364 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_csr_mem_rw_with_rand_reset.2588305364
Directory /workspace/16.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_rw.2830327492
Short name T738
Test name
Test status
Simulation time 11527975 ps
CPU time 0.55 seconds
Started Jul 30 06:43:39 PM PDT 24
Finished Jul 30 06:43:39 PM PDT 24
Peak memory 193848 kb
Host smart-5f02f45f-e654-44e0-8c88-c0efcb6d001f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830327492 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpi
o_csr_rw.2830327492
Directory /workspace/16.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_intr_test.3461925254
Short name T830
Test name
Test status
Simulation time 16061601 ps
CPU time 0.6 seconds
Started Jul 30 06:42:42 PM PDT 24
Finished Jul 30 06:42:42 PM PDT 24
Peak memory 195148 kb
Host smart-e3df3407-a2d0-4cb9-abd5-3af79d687c4d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461925254 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_intr_test.3461925254
Directory /workspace/16.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.4231317500
Short name T838
Test name
Test status
Simulation time 20268021 ps
CPU time 0.63 seconds
Started Jul 30 06:43:33 PM PDT 24
Finished Jul 30 06:43:34 PM PDT 24
Peak memory 195428 kb
Host smart-bab791e6-39af-4b07-9028-7c274a0c2a25
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231317500 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 16.gpio_same_csr_outstanding.4231317500
Directory /workspace/16.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_errors.405787361
Short name T749
Test name
Test status
Simulation time 251674524 ps
CPU time 2.59 seconds
Started Jul 30 06:43:49 PM PDT 24
Finished Jul 30 06:43:52 PM PDT 24
Peak memory 198612 kb
Host smart-9eef4b2a-bf8a-4cb3-b0c4-41506a23eda0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405787361 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_tl_errors.405787361
Directory /workspace/16.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_intg_err.4006683554
Short name T800
Test name
Test status
Simulation time 45161409 ps
CPU time 0.91 seconds
Started Jul 30 06:42:34 PM PDT 24
Finished Jul 30 06:42:36 PM PDT 24
Peak memory 197444 kb
Host smart-db432a05-c3c9-4c43-9487-fd30cd2a422c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006683554 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 16.gpio_tl_intg_err.4006683554
Directory /workspace/16.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.3673091176
Short name T725
Test name
Test status
Simulation time 86488518 ps
CPU time 1.41 seconds
Started Jul 30 06:42:49 PM PDT 24
Finished Jul 30 06:42:51 PM PDT 24
Peak memory 198880 kb
Host smart-119eb617-7507-4595-86ff-321db8f3a344
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673091176 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_csr_mem_rw_with_rand_reset.3673091176
Directory /workspace/17.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_rw.2648168278
Short name T75
Test name
Test status
Simulation time 20650040 ps
CPU time 0.62 seconds
Started Jul 30 06:42:27 PM PDT 24
Finished Jul 30 06:42:28 PM PDT 24
Peak memory 196224 kb
Host smart-0d580aa4-03ad-4653-b2a0-7d7669e1b3b5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648168278 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpi
o_csr_rw.2648168278
Directory /workspace/17.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_intr_test.3402489681
Short name T736
Test name
Test status
Simulation time 34197517 ps
CPU time 0.66 seconds
Started Jul 30 06:42:34 PM PDT 24
Finished Jul 30 06:42:36 PM PDT 24
Peak memory 194784 kb
Host smart-c95addd5-5472-4983-a28c-5317d6748e58
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402489681 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_intr_test.3402489681
Directory /workspace/17.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.4214691265
Short name T796
Test name
Test status
Simulation time 28191596 ps
CPU time 0.7 seconds
Started Jul 30 06:42:35 PM PDT 24
Finished Jul 30 06:42:36 PM PDT 24
Peak memory 195824 kb
Host smart-2a97f3ad-175f-46d6-8079-15828028d01d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214691265 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 17.gpio_same_csr_outstanding.4214691265
Directory /workspace/17.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_errors.259410873
Short name T795
Test name
Test status
Simulation time 170659679 ps
CPU time 1.14 seconds
Started Jul 30 06:43:36 PM PDT 24
Finished Jul 30 06:43:37 PM PDT 24
Peak memory 198628 kb
Host smart-ff999f80-6fea-41a5-8ead-9c9e06b5aa56
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259410873 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_tl_errors.259410873
Directory /workspace/17.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.1418503351
Short name T46
Test name
Test status
Simulation time 359656669 ps
CPU time 1.06 seconds
Started Jul 30 06:42:32 PM PDT 24
Finished Jul 30 06:42:33 PM PDT 24
Peak memory 198668 kb
Host smart-00ea7b42-40b7-4906-b634-fb9009833b52
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418503351 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 17.gpio_tl_intg_err.1418503351
Directory /workspace/17.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_mem_rw_with_rand_reset.4290836456
Short name T760
Test name
Test status
Simulation time 54065762 ps
CPU time 1.42 seconds
Started Jul 30 06:42:48 PM PDT 24
Finished Jul 30 06:42:50 PM PDT 24
Peak memory 198700 kb
Host smart-880cfd85-6b8d-474c-b58c-71c26f0cf279
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290836456 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_csr_mem_rw_with_rand_reset.4290836456
Directory /workspace/18.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_rw.857346790
Short name T100
Test name
Test status
Simulation time 60854914 ps
CPU time 0.64 seconds
Started Jul 30 06:42:40 PM PDT 24
Finished Jul 30 06:42:46 PM PDT 24
Peak memory 195500 kb
Host smart-5fdd3186-a698-4f9e-839e-bc6ac8748927
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857346790 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio
_csr_rw.857346790
Directory /workspace/18.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_intr_test.1986449436
Short name T742
Test name
Test status
Simulation time 19395771 ps
CPU time 0.7 seconds
Started Jul 30 06:42:30 PM PDT 24
Finished Jul 30 06:42:31 PM PDT 24
Peak memory 194520 kb
Host smart-e78bfebc-586c-4620-bcdf-96e7925ce78a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986449436 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_intr_test.1986449436
Directory /workspace/18.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.1214080989
Short name T94
Test name
Test status
Simulation time 15499551 ps
CPU time 0.64 seconds
Started Jul 30 06:42:45 PM PDT 24
Finished Jul 30 06:42:46 PM PDT 24
Peak memory 195628 kb
Host smart-afbffecc-079e-4e27-b4ef-058e698ea64f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214080989 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 18.gpio_same_csr_outstanding.1214080989
Directory /workspace/18.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_errors.3373808209
Short name T753
Test name
Test status
Simulation time 591411381 ps
CPU time 2.54 seconds
Started Jul 30 06:42:30 PM PDT 24
Finished Jul 30 06:42:32 PM PDT 24
Peak memory 198724 kb
Host smart-14488983-2cb6-47bd-a09f-f6a92e859ae5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373808209 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_tl_errors.3373808209
Directory /workspace/18.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.366005170
Short name T103
Test name
Test status
Simulation time 708528857 ps
CPU time 1.53 seconds
Started Jul 30 06:42:42 PM PDT 24
Finished Jul 30 06:42:43 PM PDT 24
Peak memory 198672 kb
Host smart-6a2b4bd2-f655-4d60-afc6-f0538a5aa19b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366005170 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 18.gpio_tl_intg_err.366005170
Directory /workspace/18.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.4166544778
Short name T806
Test name
Test status
Simulation time 29451599 ps
CPU time 1.27 seconds
Started Jul 30 06:42:38 PM PDT 24
Finished Jul 30 06:42:39 PM PDT 24
Peak memory 198760 kb
Host smart-d9ce8b1a-2eb8-4ca4-ab3c-69d85fa88f53
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166544778 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_csr_mem_rw_with_rand_reset.4166544778
Directory /workspace/19.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_rw.2012007032
Short name T737
Test name
Test status
Simulation time 23664161 ps
CPU time 0.56 seconds
Started Jul 30 06:42:34 PM PDT 24
Finished Jul 30 06:42:35 PM PDT 24
Peak memory 195332 kb
Host smart-4cc73583-ff46-4482-92ed-4093b25f4dfc
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012007032 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpi
o_csr_rw.2012007032
Directory /workspace/19.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_intr_test.713145571
Short name T782
Test name
Test status
Simulation time 14846597 ps
CPU time 0.62 seconds
Started Jul 30 06:42:45 PM PDT 24
Finished Jul 30 06:42:46 PM PDT 24
Peak memory 195208 kb
Host smart-2cdb1034-f67c-4204-9993-506948b27d12
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713145571 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_intr_test.713145571
Directory /workspace/19.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.851675912
Short name T837
Test name
Test status
Simulation time 17520465 ps
CPU time 0.78 seconds
Started Jul 30 06:42:36 PM PDT 24
Finished Jul 30 06:42:37 PM PDT 24
Peak memory 196632 kb
Host smart-6be18695-751e-4894-afd1-6bc9cccfe4a2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851675912 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 19.gpio_same_csr_outstanding.851675912
Directory /workspace/19.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_errors.1210428688
Short name T734
Test name
Test status
Simulation time 264945080 ps
CPU time 1.54 seconds
Started Jul 30 06:43:00 PM PDT 24
Finished Jul 30 06:43:01 PM PDT 24
Peak memory 198800 kb
Host smart-0b0cb15b-c076-4a3e-8095-02cd409d5843
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210428688 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_tl_errors.1210428688
Directory /workspace/19.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.4089390036
Short name T83
Test name
Test status
Simulation time 29627879 ps
CPU time 0.76 seconds
Started Jul 30 06:42:30 PM PDT 24
Finished Jul 30 06:42:31 PM PDT 24
Peak memory 196380 kb
Host smart-27ee6f88-71d5-43c9-a393-79ba0ee97bfe
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089390036 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
2.gpio_csr_aliasing.4089390036
Directory /workspace/2.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.1271961563
Short name T745
Test name
Test status
Simulation time 63876760 ps
CPU time 1.38 seconds
Started Jul 30 06:42:25 PM PDT 24
Finished Jul 30 06:42:27 PM PDT 24
Peak memory 197556 kb
Host smart-f48be5f5-32bc-443c-9afc-d379daea416e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271961563 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_bit_bash.1271961563
Directory /workspace/2.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_hw_reset.483553323
Short name T74
Test name
Test status
Simulation time 30932820 ps
CPU time 0.63 seconds
Started Jul 30 06:42:32 PM PDT 24
Finished Jul 30 06:42:33 PM PDT 24
Peak memory 195536 kb
Host smart-755a4561-7948-4b75-8a89-e0b95c821b96
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483553323 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_hw_reset.483553323
Directory /workspace/2.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.1839240583
Short name T834
Test name
Test status
Simulation time 175050576 ps
CPU time 1.38 seconds
Started Jul 30 06:42:31 PM PDT 24
Finished Jul 30 06:42:33 PM PDT 24
Peak memory 198800 kb
Host smart-7b7286a5-3390-4862-ad90-10a1530d1075
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839240583 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_mem_rw_with_rand_reset.1839240583
Directory /workspace/2.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_rw.2664775417
Short name T718
Test name
Test status
Simulation time 24702045 ps
CPU time 0.62 seconds
Started Jul 30 06:42:30 PM PDT 24
Finished Jul 30 06:42:31 PM PDT 24
Peak memory 195288 kb
Host smart-69885814-3c6a-437f-b4c4-97c6ef502b51
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664775417 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio
_csr_rw.2664775417
Directory /workspace/2.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_intr_test.3318748152
Short name T792
Test name
Test status
Simulation time 19841337 ps
CPU time 0.59 seconds
Started Jul 30 06:42:37 PM PDT 24
Finished Jul 30 06:42:38 PM PDT 24
Peak memory 194488 kb
Host smart-dbe59117-32ac-456c-bf04-962579312b2c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318748152 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_intr_test.3318748152
Directory /workspace/2.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_same_csr_outstanding.456307763
Short name T78
Test name
Test status
Simulation time 28543593 ps
CPU time 0.78 seconds
Started Jul 30 06:42:25 PM PDT 24
Finished Jul 30 06:42:26 PM PDT 24
Peak memory 197604 kb
Host smart-846b84df-d8d0-4cb1-9d8c-90b8fe780a24
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456307763 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 2.gpio_same_csr_outstanding.456307763
Directory /workspace/2.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_errors.2248637621
Short name T732
Test name
Test status
Simulation time 735278310 ps
CPU time 2.3 seconds
Started Jul 30 06:42:34 PM PDT 24
Finished Jul 30 06:42:37 PM PDT 24
Peak memory 198780 kb
Host smart-dd2ca6c9-5f72-4d99-8395-31f085d168b4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248637621 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_tl_errors.2248637621
Directory /workspace/2.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.2694489916
Short name T816
Test name
Test status
Simulation time 476701987 ps
CPU time 0.88 seconds
Started Jul 30 06:42:27 PM PDT 24
Finished Jul 30 06:42:28 PM PDT 24
Peak memory 198720 kb
Host smart-24d507f0-5c25-43b7-921a-47fe33e0014b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694489916 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 2.gpio_tl_intg_err.2694489916
Directory /workspace/2.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.gpio_intr_test.2515981610
Short name T717
Test name
Test status
Simulation time 32283628 ps
CPU time 0.64 seconds
Started Jul 30 06:42:38 PM PDT 24
Finished Jul 30 06:42:39 PM PDT 24
Peak memory 195060 kb
Host smart-54c263ab-62b1-439e-bd38-9002801579f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515981610 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.gpio_intr_test.2515981610
Directory /workspace/20.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.gpio_intr_test.2025402732
Short name T781
Test name
Test status
Simulation time 39339622 ps
CPU time 0.59 seconds
Started Jul 30 06:42:42 PM PDT 24
Finished Jul 30 06:42:43 PM PDT 24
Peak memory 194432 kb
Host smart-cc03953f-a41f-499e-87ef-6c1b678368e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025402732 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.gpio_intr_test.2025402732
Directory /workspace/21.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.gpio_intr_test.3755136551
Short name T746
Test name
Test status
Simulation time 20006009 ps
CPU time 0.59 seconds
Started Jul 30 06:42:34 PM PDT 24
Finished Jul 30 06:42:35 PM PDT 24
Peak memory 194544 kb
Host smart-01266b26-5a45-46f4-add1-032224303a34
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755136551 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.gpio_intr_test.3755136551
Directory /workspace/22.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.gpio_intr_test.2748847374
Short name T740
Test name
Test status
Simulation time 99321855 ps
CPU time 0.61 seconds
Started Jul 30 06:42:31 PM PDT 24
Finished Jul 30 06:42:32 PM PDT 24
Peak memory 194580 kb
Host smart-77f7365c-f924-430e-8c41-f6a86cee0416
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748847374 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.gpio_intr_test.2748847374
Directory /workspace/23.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.gpio_intr_test.21356104
Short name T721
Test name
Test status
Simulation time 11366790 ps
CPU time 0.61 seconds
Started Jul 30 06:42:34 PM PDT 24
Finished Jul 30 06:42:35 PM PDT 24
Peak memory 195288 kb
Host smart-2ad52ba0-a68e-46f1-8e74-9fc8d1a3ef8b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21356104 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.gpio_intr_test.21356104
Directory /workspace/24.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.gpio_intr_test.226130150
Short name T776
Test name
Test status
Simulation time 43550553 ps
CPU time 0.58 seconds
Started Jul 30 06:42:25 PM PDT 24
Finished Jul 30 06:42:26 PM PDT 24
Peak memory 194528 kb
Host smart-f3d87a69-aabe-4679-9685-20fb933f11b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226130150 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.gpio_intr_test.226130150
Directory /workspace/25.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.gpio_intr_test.2362364156
Short name T780
Test name
Test status
Simulation time 23630191 ps
CPU time 0.6 seconds
Started Jul 30 06:42:33 PM PDT 24
Finished Jul 30 06:42:34 PM PDT 24
Peak memory 194628 kb
Host smart-788307cd-6b41-4437-8551-2ce394c22849
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362364156 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.gpio_intr_test.2362364156
Directory /workspace/26.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.gpio_intr_test.913563672
Short name T809
Test name
Test status
Simulation time 15656816 ps
CPU time 0.61 seconds
Started Jul 30 06:42:36 PM PDT 24
Finished Jul 30 06:42:37 PM PDT 24
Peak memory 195108 kb
Host smart-36ee4c25-4cce-450a-b5c1-f68241929ec6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913563672 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.gpio_intr_test.913563672
Directory /workspace/27.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.gpio_intr_test.4057829600
Short name T762
Test name
Test status
Simulation time 34996468 ps
CPU time 0.6 seconds
Started Jul 30 06:42:40 PM PDT 24
Finished Jul 30 06:42:41 PM PDT 24
Peak memory 195168 kb
Host smart-cbd9463f-ff1c-4d53-9753-f2b77b458d70
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057829600 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.gpio_intr_test.4057829600
Directory /workspace/28.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.gpio_intr_test.80286251
Short name T739
Test name
Test status
Simulation time 35149552 ps
CPU time 0.57 seconds
Started Jul 30 06:42:32 PM PDT 24
Finished Jul 30 06:42:33 PM PDT 24
Peak memory 195092 kb
Host smart-2b54e3ab-2e49-49ac-91db-15852bd04b0d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80286251 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.gpio_intr_test.80286251
Directory /workspace/29.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.1681546394
Short name T80
Test name
Test status
Simulation time 105188750 ps
CPU time 0.75 seconds
Started Jul 30 06:42:31 PM PDT 24
Finished Jul 30 06:42:32 PM PDT 24
Peak memory 197128 kb
Host smart-76e6a0c8-b92c-4d4f-b80a-83cb6741ba89
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681546394 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
3.gpio_csr_aliasing.1681546394
Directory /workspace/3.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.3636580339
Short name T89
Test name
Test status
Simulation time 312912487 ps
CPU time 2.16 seconds
Started Jul 30 06:42:38 PM PDT 24
Finished Jul 30 06:42:40 PM PDT 24
Peak memory 197780 kb
Host smart-a56c20dc-dca9-46b3-ab22-fdd7df8781e4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636580339 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_bit_bash.3636580339
Directory /workspace/3.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.367673146
Short name T818
Test name
Test status
Simulation time 21476474 ps
CPU time 0.63 seconds
Started Jul 30 06:42:28 PM PDT 24
Finished Jul 30 06:42:29 PM PDT 24
Peak memory 195124 kb
Host smart-9152afa3-8e15-49c3-806d-063d1984f79d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367673146 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_hw_reset.367673146
Directory /workspace/3.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.185015323
Short name T769
Test name
Test status
Simulation time 84245166 ps
CPU time 1.05 seconds
Started Jul 30 06:42:37 PM PDT 24
Finished Jul 30 06:42:38 PM PDT 24
Peak memory 198648 kb
Host smart-7fb3a55e-a3a5-45f7-bbaf-21acca0cb97e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185015323 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_mem_rw_with_rand_reset.185015323
Directory /workspace/3.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_rw.3726295877
Short name T77
Test name
Test status
Simulation time 14046529 ps
CPU time 0.58 seconds
Started Jul 30 06:42:33 PM PDT 24
Finished Jul 30 06:42:34 PM PDT 24
Peak memory 193980 kb
Host smart-983c70bf-4dd2-428e-9300-c40a8f8a8bcf
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726295877 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio
_csr_rw.3726295877
Directory /workspace/3.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_intr_test.2313699282
Short name T814
Test name
Test status
Simulation time 23706806 ps
CPU time 0.61 seconds
Started Jul 30 06:42:38 PM PDT 24
Finished Jul 30 06:42:39 PM PDT 24
Peak memory 195240 kb
Host smart-bad2b17f-c13c-430c-83df-8e226c901f38
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313699282 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_intr_test.2313699282
Directory /workspace/3.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_same_csr_outstanding.3099959514
Short name T836
Test name
Test status
Simulation time 46501873 ps
CPU time 0.75 seconds
Started Jul 30 06:42:33 PM PDT 24
Finished Jul 30 06:42:34 PM PDT 24
Peak memory 197336 kb
Host smart-540377ab-940f-4def-a38b-7a36d48d6e3b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099959514 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 3.gpio_same_csr_outstanding.3099959514
Directory /workspace/3.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_errors.859300149
Short name T790
Test name
Test status
Simulation time 80646228 ps
CPU time 2.23 seconds
Started Jul 30 06:42:30 PM PDT 24
Finished Jul 30 06:42:32 PM PDT 24
Peak memory 198888 kb
Host smart-6d28481c-6a6c-413a-9285-1b19c6f2fa3c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859300149 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_tl_errors.859300149
Directory /workspace/3.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.3638288991
Short name T34
Test name
Test status
Simulation time 169182208 ps
CPU time 1.07 seconds
Started Jul 30 06:42:29 PM PDT 24
Finished Jul 30 06:42:30 PM PDT 24
Peak memory 198784 kb
Host smart-bf83fe9f-ded5-4308-96a6-5039abe8e603
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638288991 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 3.gpio_tl_intg_err.3638288991
Directory /workspace/3.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.gpio_intr_test.1150369479
Short name T773
Test name
Test status
Simulation time 23241670 ps
CPU time 0.6 seconds
Started Jul 30 06:42:31 PM PDT 24
Finished Jul 30 06:42:37 PM PDT 24
Peak memory 194508 kb
Host smart-3f5916d3-26ba-4a93-bcb3-28ad64c8fe65
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150369479 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.gpio_intr_test.1150369479
Directory /workspace/30.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.gpio_intr_test.1492292793
Short name T819
Test name
Test status
Simulation time 71135026 ps
CPU time 0.55 seconds
Started Jul 30 06:42:31 PM PDT 24
Finished Jul 30 06:42:32 PM PDT 24
Peak memory 194492 kb
Host smart-3bcc9ed0-7500-4393-a1f6-684c99d3cbac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492292793 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.gpio_intr_test.1492292793
Directory /workspace/31.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.gpio_intr_test.1386793621
Short name T805
Test name
Test status
Simulation time 64744069 ps
CPU time 0.59 seconds
Started Jul 30 06:42:44 PM PDT 24
Finished Jul 30 06:42:45 PM PDT 24
Peak memory 194524 kb
Host smart-146081df-065e-46da-b38e-757428930d39
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386793621 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.gpio_intr_test.1386793621
Directory /workspace/32.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.gpio_intr_test.4104436706
Short name T797
Test name
Test status
Simulation time 36110967 ps
CPU time 0.55 seconds
Started Jul 30 06:42:34 PM PDT 24
Finished Jul 30 06:42:40 PM PDT 24
Peak memory 195128 kb
Host smart-ef71860e-29c9-40fc-94b2-afff0a9d0601
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104436706 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.gpio_intr_test.4104436706
Directory /workspace/33.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.gpio_intr_test.1426512116
Short name T731
Test name
Test status
Simulation time 27099157 ps
CPU time 0.61 seconds
Started Jul 30 06:42:36 PM PDT 24
Finished Jul 30 06:42:37 PM PDT 24
Peak memory 195216 kb
Host smart-8200e15a-794f-4151-a1c4-8f6d0ce3a86b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426512116 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.gpio_intr_test.1426512116
Directory /workspace/34.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.gpio_intr_test.613487161
Short name T747
Test name
Test status
Simulation time 12376827 ps
CPU time 0.57 seconds
Started Jul 30 06:42:34 PM PDT 24
Finished Jul 30 06:42:35 PM PDT 24
Peak memory 194464 kb
Host smart-bde2051b-2aef-4963-88de-c43f4c3b83ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613487161 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.gpio_intr_test.613487161
Directory /workspace/35.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.gpio_intr_test.1651087858
Short name T779
Test name
Test status
Simulation time 26595574 ps
CPU time 0.62 seconds
Started Jul 30 06:42:45 PM PDT 24
Finished Jul 30 06:42:46 PM PDT 24
Peak memory 195196 kb
Host smart-bf671ed4-468c-44b9-9cca-0f767eb11d26
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651087858 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.gpio_intr_test.1651087858
Directory /workspace/36.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.gpio_intr_test.3980967831
Short name T815
Test name
Test status
Simulation time 31892366 ps
CPU time 0.59 seconds
Started Jul 30 06:42:54 PM PDT 24
Finished Jul 30 06:42:54 PM PDT 24
Peak memory 194476 kb
Host smart-06e3d269-57f2-44ee-bb30-795868ed4348
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980967831 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.gpio_intr_test.3980967831
Directory /workspace/37.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.gpio_intr_test.3287487319
Short name T754
Test name
Test status
Simulation time 14468052 ps
CPU time 0.6 seconds
Started Jul 30 06:42:39 PM PDT 24
Finished Jul 30 06:42:40 PM PDT 24
Peak memory 194496 kb
Host smart-96e86a0b-ba2e-4c5c-8201-4e36c5705985
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287487319 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.gpio_intr_test.3287487319
Directory /workspace/38.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.gpio_intr_test.1466397223
Short name T741
Test name
Test status
Simulation time 63167569 ps
CPU time 0.58 seconds
Started Jul 30 06:42:31 PM PDT 24
Finished Jul 30 06:42:32 PM PDT 24
Peak memory 194556 kb
Host smart-88549632-778b-4595-9c0e-06df5fbab196
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466397223 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.gpio_intr_test.1466397223
Directory /workspace/39.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_bit_bash.4269081902
Short name T76
Test name
Test status
Simulation time 62484450 ps
CPU time 1.4 seconds
Started Jul 30 06:42:30 PM PDT 24
Finished Jul 30 06:42:32 PM PDT 24
Peak memory 198692 kb
Host smart-8bde3af2-793a-435b-8796-15b5b1cbafb4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269081902 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_bit_bash.4269081902
Directory /workspace/4.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.665190559
Short name T804
Test name
Test status
Simulation time 16259945 ps
CPU time 0.59 seconds
Started Jul 30 06:42:34 PM PDT 24
Finished Jul 30 06:42:34 PM PDT 24
Peak memory 195264 kb
Host smart-cdc9384a-443e-41a7-a414-629bb0e64f18
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665190559 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_hw_reset.665190559
Directory /workspace/4.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.137471482
Short name T724
Test name
Test status
Simulation time 41491295 ps
CPU time 0.92 seconds
Started Jul 30 06:42:26 PM PDT 24
Finished Jul 30 06:42:27 PM PDT 24
Peak memory 194292 kb
Host smart-0c8c5153-e45b-4e0f-b15f-07dc91e8a5a7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137471482 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_mem_rw_with_rand_reset.137471482
Directory /workspace/4.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_rw.1968772536
Short name T81
Test name
Test status
Simulation time 46196929 ps
CPU time 0.58 seconds
Started Jul 30 06:42:31 PM PDT 24
Finished Jul 30 06:42:32 PM PDT 24
Peak memory 195588 kb
Host smart-57509633-f5e9-45cc-8658-7761aac5fe6a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968772536 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio
_csr_rw.1968772536
Directory /workspace/4.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_intr_test.720454540
Short name T822
Test name
Test status
Simulation time 15702231 ps
CPU time 0.6 seconds
Started Jul 30 06:42:37 PM PDT 24
Finished Jul 30 06:42:37 PM PDT 24
Peak memory 194476 kb
Host smart-61c52e33-0024-45ba-b3c2-9809c277520e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720454540 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_intr_test.720454540
Directory /workspace/4.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.3310889103
Short name T73
Test name
Test status
Simulation time 29399967 ps
CPU time 0.77 seconds
Started Jul 30 06:42:35 PM PDT 24
Finished Jul 30 06:42:36 PM PDT 24
Peak memory 197032 kb
Host smart-d2791868-633c-45e7-a0ad-924f4305c845
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310889103 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 4.gpio_same_csr_outstanding.3310889103
Directory /workspace/4.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_errors.1509853121
Short name T841
Test name
Test status
Simulation time 63398478 ps
CPU time 3 seconds
Started Jul 30 06:42:26 PM PDT 24
Finished Jul 30 06:42:29 PM PDT 24
Peak memory 198772 kb
Host smart-4546d641-76c3-4cba-a5fa-a983f7a7700d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509853121 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_tl_errors.1509853121
Directory /workspace/4.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.166757571
Short name T798
Test name
Test status
Simulation time 163350962 ps
CPU time 1.13 seconds
Started Jul 30 06:42:35 PM PDT 24
Finished Jul 30 06:42:36 PM PDT 24
Peak memory 198764 kb
Host smart-16ba0c3e-0a56-4b49-bd98-2d11f71de1bf
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166757571 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 4.gpio_tl_intg_err.166757571
Directory /workspace/4.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.gpio_intr_test.142760130
Short name T799
Test name
Test status
Simulation time 17555305 ps
CPU time 0.61 seconds
Started Jul 30 06:42:35 PM PDT 24
Finished Jul 30 06:42:35 PM PDT 24
Peak memory 194540 kb
Host smart-9868abb5-39c7-407a-9fda-b3149c63c14e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142760130 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.gpio_intr_test.142760130
Directory /workspace/40.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.gpio_intr_test.575530218
Short name T750
Test name
Test status
Simulation time 49484032 ps
CPU time 0.6 seconds
Started Jul 30 06:42:35 PM PDT 24
Finished Jul 30 06:42:36 PM PDT 24
Peak memory 195108 kb
Host smart-4bf49c46-9ce0-4e5b-9eeb-16e2993d38ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575530218 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.gpio_intr_test.575530218
Directory /workspace/41.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.gpio_intr_test.1103162851
Short name T758
Test name
Test status
Simulation time 13163129 ps
CPU time 0.57 seconds
Started Jul 30 06:42:31 PM PDT 24
Finished Jul 30 06:42:32 PM PDT 24
Peak memory 194460 kb
Host smart-1bec1022-47b2-4072-a70d-20e9f6ace3d2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103162851 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.gpio_intr_test.1103162851
Directory /workspace/42.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.gpio_intr_test.2152037387
Short name T777
Test name
Test status
Simulation time 19446318 ps
CPU time 0.62 seconds
Started Jul 30 06:42:44 PM PDT 24
Finished Jul 30 06:42:45 PM PDT 24
Peak memory 194564 kb
Host smart-7865a10e-f5cc-4128-9e19-26d36d746ec8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152037387 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.gpio_intr_test.2152037387
Directory /workspace/43.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.gpio_intr_test.1470455159
Short name T793
Test name
Test status
Simulation time 16819284 ps
CPU time 0.61 seconds
Started Jul 30 06:42:34 PM PDT 24
Finished Jul 30 06:42:35 PM PDT 24
Peak memory 195148 kb
Host smart-b4d2df3f-36fd-4cdb-96ee-38b3571657e2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470455159 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.gpio_intr_test.1470455159
Directory /workspace/44.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.gpio_intr_test.2524247667
Short name T729
Test name
Test status
Simulation time 14655709 ps
CPU time 0.56 seconds
Started Jul 30 06:42:36 PM PDT 24
Finished Jul 30 06:42:36 PM PDT 24
Peak memory 195096 kb
Host smart-e29f636f-2445-4f8d-85d0-c1aa237b76d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524247667 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.gpio_intr_test.2524247667
Directory /workspace/45.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.gpio_intr_test.2561424091
Short name T772
Test name
Test status
Simulation time 26785692 ps
CPU time 0.66 seconds
Started Jul 30 06:42:39 PM PDT 24
Finished Jul 30 06:42:40 PM PDT 24
Peak memory 194524 kb
Host smart-215b6c2c-4f80-4c30-9c47-1bb7dcc264bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561424091 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.gpio_intr_test.2561424091
Directory /workspace/46.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.gpio_intr_test.914826853
Short name T735
Test name
Test status
Simulation time 157046443 ps
CPU time 0.65 seconds
Started Jul 30 06:42:38 PM PDT 24
Finished Jul 30 06:42:39 PM PDT 24
Peak memory 194508 kb
Host smart-40e722b9-15f2-41cf-b1c0-9fcbc876d52a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914826853 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.gpio_intr_test.914826853
Directory /workspace/47.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.gpio_intr_test.1760614305
Short name T744
Test name
Test status
Simulation time 22937452 ps
CPU time 0.58 seconds
Started Jul 30 06:42:39 PM PDT 24
Finished Jul 30 06:42:40 PM PDT 24
Peak memory 195128 kb
Host smart-df9246c9-49e6-4a4e-88a2-d117ed91a1d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760614305 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.gpio_intr_test.1760614305
Directory /workspace/48.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.gpio_intr_test.444442627
Short name T835
Test name
Test status
Simulation time 27323855 ps
CPU time 0.61 seconds
Started Jul 30 06:42:35 PM PDT 24
Finished Jul 30 06:42:36 PM PDT 24
Peak memory 194548 kb
Host smart-a1de47c2-65ec-4cc3-9bcb-8b549eed5b40
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444442627 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.gpio_intr_test.444442627
Directory /workspace/49.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_mem_rw_with_rand_reset.3255259420
Short name T759
Test name
Test status
Simulation time 464438633 ps
CPU time 1.55 seconds
Started Jul 30 06:42:32 PM PDT 24
Finished Jul 30 06:42:34 PM PDT 24
Peak memory 198812 kb
Host smart-babb4427-59f4-4525-821b-52425adef383
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255259420 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_csr_mem_rw_with_rand_reset.3255259420
Directory /workspace/5.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_rw.3125230964
Short name T102
Test name
Test status
Simulation time 40948968 ps
CPU time 0.62 seconds
Started Jul 30 06:42:34 PM PDT 24
Finished Jul 30 06:42:34 PM PDT 24
Peak memory 195588 kb
Host smart-1e57b9b1-eadb-4215-9011-2b1e76c06183
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125230964 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio
_csr_rw.3125230964
Directory /workspace/5.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_intr_test.2747094323
Short name T743
Test name
Test status
Simulation time 19491885 ps
CPU time 0.58 seconds
Started Jul 30 06:42:34 PM PDT 24
Finished Jul 30 06:42:35 PM PDT 24
Peak memory 195108 kb
Host smart-02f8df5e-f645-43c7-bcc9-3d3a7f515fa3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747094323 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_intr_test.2747094323
Directory /workspace/5.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.247517138
Short name T92
Test name
Test status
Simulation time 18414126 ps
CPU time 0.63 seconds
Started Jul 30 06:42:37 PM PDT 24
Finished Jul 30 06:42:38 PM PDT 24
Peak memory 196036 kb
Host smart-6e8e5f11-53e9-4ab2-bde1-b43c4447a219
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247517138 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 5.gpio_same_csr_outstanding.247517138
Directory /workspace/5.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_errors.483271928
Short name T722
Test name
Test status
Simulation time 448094716 ps
CPU time 1.67 seconds
Started Jul 30 06:42:31 PM PDT 24
Finished Jul 30 06:42:33 PM PDT 24
Peak memory 198848 kb
Host smart-92162b55-5047-449a-8ae0-d6e31b48a547
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483271928 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_tl_errors.483271928
Directory /workspace/5.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.600697706
Short name T41
Test name
Test status
Simulation time 130794250 ps
CPU time 1.4 seconds
Started Jul 30 06:42:43 PM PDT 24
Finished Jul 30 06:42:45 PM PDT 24
Peak memory 198808 kb
Host smart-f99e2120-6317-4dcc-a5da-329432929690
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600697706 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 5.gpio_tl_intg_err.600697706
Directory /workspace/5.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.1087843134
Short name T726
Test name
Test status
Simulation time 103553371 ps
CPU time 0.89 seconds
Started Jul 30 06:42:28 PM PDT 24
Finished Jul 30 06:42:29 PM PDT 24
Peak memory 198676 kb
Host smart-91184d0d-8a4f-45b2-99cc-3c664f04ded7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087843134 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_csr_mem_rw_with_rand_reset.1087843134
Directory /workspace/6.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_rw.2840391009
Short name T768
Test name
Test status
Simulation time 13565103 ps
CPU time 0.59 seconds
Started Jul 30 06:42:31 PM PDT 24
Finished Jul 30 06:42:32 PM PDT 24
Peak memory 195352 kb
Host smart-2569a24b-1f32-458f-b975-8b3048f990b5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840391009 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio
_csr_rw.2840391009
Directory /workspace/6.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_intr_test.1758497295
Short name T801
Test name
Test status
Simulation time 249896903 ps
CPU time 0.63 seconds
Started Jul 30 06:42:38 PM PDT 24
Finished Jul 30 06:42:39 PM PDT 24
Peak memory 194488 kb
Host smart-e0207c14-9327-4f86-82c1-87f6dda4b38d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758497295 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_intr_test.1758497295
Directory /workspace/6.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.549219464
Short name T808
Test name
Test status
Simulation time 14716490 ps
CPU time 0.7 seconds
Started Jul 30 06:42:32 PM PDT 24
Finished Jul 30 06:42:33 PM PDT 24
Peak memory 195540 kb
Host smart-4ace170c-7cd5-4df9-923f-39a2068dc7fe
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549219464 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 6.gpio_same_csr_outstanding.549219464
Directory /workspace/6.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_errors.2423157947
Short name T770
Test name
Test status
Simulation time 65151721 ps
CPU time 3.27 seconds
Started Jul 30 06:42:42 PM PDT 24
Finished Jul 30 06:42:45 PM PDT 24
Peak memory 198776 kb
Host smart-592487ce-5267-48bb-8ac4-fee7bcc30176
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423157947 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_tl_errors.2423157947
Directory /workspace/6.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.4278593682
Short name T44
Test name
Test status
Simulation time 75744069 ps
CPU time 1.15 seconds
Started Jul 30 06:42:30 PM PDT 24
Finished Jul 30 06:42:31 PM PDT 24
Peak memory 198608 kb
Host smart-7d392a26-c377-4c15-ab8b-1229d8fe9b01
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278593682 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 6.gpio_tl_intg_err.4278593682
Directory /workspace/6.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.2046722144
Short name T763
Test name
Test status
Simulation time 95875721 ps
CPU time 0.83 seconds
Started Jul 30 06:42:33 PM PDT 24
Finished Jul 30 06:42:34 PM PDT 24
Peak memory 198636 kb
Host smart-0ee1b2f6-8f62-43b7-8e1e-c2969c5cf8e2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046722144 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_csr_mem_rw_with_rand_reset.2046722144
Directory /workspace/7.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_rw.201125955
Short name T764
Test name
Test status
Simulation time 14339550 ps
CPU time 0.61 seconds
Started Jul 30 06:42:39 PM PDT 24
Finished Jul 30 06:42:40 PM PDT 24
Peak memory 195360 kb
Host smart-99d60c7b-d0ec-416c-8dd3-ddcadc1e79ed
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201125955 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_
csr_rw.201125955
Directory /workspace/7.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_intr_test.116555380
Short name T788
Test name
Test status
Simulation time 61519026 ps
CPU time 0.58 seconds
Started Jul 30 06:42:38 PM PDT 24
Finished Jul 30 06:42:39 PM PDT 24
Peak memory 195116 kb
Host smart-1c6cc508-0e84-43f1-a4e7-270e5223862b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116555380 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_intr_test.116555380
Directory /workspace/7.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.1410056348
Short name T95
Test name
Test status
Simulation time 52183473 ps
CPU time 0.73 seconds
Started Jul 30 06:42:36 PM PDT 24
Finished Jul 30 06:42:37 PM PDT 24
Peak memory 197588 kb
Host smart-446fac6c-9cee-4700-8072-b599b9dfcbb8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410056348 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 7.gpio_same_csr_outstanding.1410056348
Directory /workspace/7.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_errors.1697569590
Short name T785
Test name
Test status
Simulation time 51347604 ps
CPU time 0.9 seconds
Started Jul 30 06:42:43 PM PDT 24
Finished Jul 30 06:42:45 PM PDT 24
Peak memory 198608 kb
Host smart-791c4446-398a-4008-ba61-1f813ae99897
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697569590 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_tl_errors.1697569590
Directory /workspace/7.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.1665189653
Short name T42
Test name
Test status
Simulation time 126580886 ps
CPU time 1.49 seconds
Started Jul 30 06:42:33 PM PDT 24
Finished Jul 30 06:42:40 PM PDT 24
Peak memory 198728 kb
Host smart-ca9f6e15-a61d-45a3-a101-3a87b64ed3ca
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665189653 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 7.gpio_tl_intg_err.1665189653
Directory /workspace/7.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.373642051
Short name T783
Test name
Test status
Simulation time 15572704 ps
CPU time 0.66 seconds
Started Jul 30 06:42:35 PM PDT 24
Finished Jul 30 06:42:36 PM PDT 24
Peak memory 197188 kb
Host smart-611b113d-7a3d-4e0e-831c-911b46f25ceb
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373642051 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_csr_mem_rw_with_rand_reset.373642051
Directory /workspace/8.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_rw.3008246098
Short name T82
Test name
Test status
Simulation time 30512178 ps
CPU time 0.6 seconds
Started Jul 30 06:42:37 PM PDT 24
Finished Jul 30 06:42:38 PM PDT 24
Peak memory 196040 kb
Host smart-137e6e6a-b9de-466e-88dd-16aedfced276
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008246098 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio
_csr_rw.3008246098
Directory /workspace/8.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_intr_test.1647678439
Short name T728
Test name
Test status
Simulation time 17151702 ps
CPU time 0.56 seconds
Started Jul 30 06:42:27 PM PDT 24
Finished Jul 30 06:42:28 PM PDT 24
Peak memory 194508 kb
Host smart-9c0bf856-a2b3-4b6f-9c8b-5f757fd9d5c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647678439 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_intr_test.1647678439
Directory /workspace/8.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_same_csr_outstanding.4168313730
Short name T821
Test name
Test status
Simulation time 15956838 ps
CPU time 0.66 seconds
Started Jul 30 06:42:32 PM PDT 24
Finished Jul 30 06:42:33 PM PDT 24
Peak memory 196328 kb
Host smart-1d7aa01a-fa2a-43b7-ada2-fcfd912b2f37
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168313730 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 8.gpio_same_csr_outstanding.4168313730
Directory /workspace/8.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_errors.4113266365
Short name T825
Test name
Test status
Simulation time 19307051 ps
CPU time 0.99 seconds
Started Jul 30 06:42:32 PM PDT 24
Finished Jul 30 06:42:33 PM PDT 24
Peak memory 198604 kb
Host smart-50784118-529e-4ef5-8884-9f023d9619e7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113266365 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_tl_errors.4113266365
Directory /workspace/8.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_intg_err.2629365292
Short name T32
Test name
Test status
Simulation time 152057923 ps
CPU time 1.12 seconds
Started Jul 30 06:42:40 PM PDT 24
Finished Jul 30 06:42:41 PM PDT 24
Peak memory 198728 kb
Host smart-688307d7-9e00-49f8-b60d-ebd5bf99b8e3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629365292 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 8.gpio_tl_intg_err.2629365292
Directory /workspace/8.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.1416387917
Short name T824
Test name
Test status
Simulation time 16373649 ps
CPU time 0.64 seconds
Started Jul 30 06:42:30 PM PDT 24
Finished Jul 30 06:42:31 PM PDT 24
Peak memory 197776 kb
Host smart-70bf0f72-bc48-4a29-bc19-73dc998369a0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416387917 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_csr_mem_rw_with_rand_reset.1416387917
Directory /workspace/9.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_rw.1676471641
Short name T85
Test name
Test status
Simulation time 10883015 ps
CPU time 0.57 seconds
Started Jul 30 06:43:40 PM PDT 24
Finished Jul 30 06:43:41 PM PDT 24
Peak memory 194992 kb
Host smart-f5859fa4-8752-45ad-9a68-d57375d284f4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676471641 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio
_csr_rw.1676471641
Directory /workspace/9.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_intr_test.4212839221
Short name T761
Test name
Test status
Simulation time 26424755 ps
CPU time 0.59 seconds
Started Jul 30 06:42:48 PM PDT 24
Finished Jul 30 06:42:49 PM PDT 24
Peak memory 194532 kb
Host smart-1dbcf6c0-bd2b-48fd-9e3a-fb51f57a7d28
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212839221 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_intr_test.4212839221
Directory /workspace/9.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_same_csr_outstanding.1137120304
Short name T97
Test name
Test status
Simulation time 24906545 ps
CPU time 0.69 seconds
Started Jul 30 06:42:43 PM PDT 24
Finished Jul 30 06:42:44 PM PDT 24
Peak memory 195608 kb
Host smart-e13dbfc7-6738-4b28-a5d3-f0b1e44c6958
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137120304 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 9.gpio_same_csr_outstanding.1137120304
Directory /workspace/9.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_errors.1089464092
Short name T756
Test name
Test status
Simulation time 258481586 ps
CPU time 1.5 seconds
Started Jul 30 06:42:37 PM PDT 24
Finished Jul 30 06:42:39 PM PDT 24
Peak memory 198852 kb
Host smart-e005b368-8f34-45f3-89e4-368b8f558763
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089464092 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_tl_errors.1089464092
Directory /workspace/9.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.1664647293
Short name T47
Test name
Test status
Simulation time 49528333 ps
CPU time 0.91 seconds
Started Jul 30 06:42:30 PM PDT 24
Finished Jul 30 06:42:31 PM PDT 24
Peak memory 198280 kb
Host smart-6475569c-e74a-4fa5-ad85-cf8e841fdd92
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664647293 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 9.gpio_tl_intg_err.1664647293
Directory /workspace/9.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/0.gpio_alert_test.2411278153
Short name T287
Test name
Test status
Simulation time 12314479 ps
CPU time 0.57 seconds
Started Jul 30 06:01:51 PM PDT 24
Finished Jul 30 06:01:52 PM PDT 24
Peak memory 194488 kb
Host smart-8d9bac05-a6c3-4b13-8799-e3dd985fa022
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411278153 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_alert_test.2411278153
Directory /workspace/0.gpio_alert_test/latest

Test location /workspace/coverage/default/0.gpio_dout_din_regs_random_rw.1508334252
Short name T683
Test name
Test status
Simulation time 26056668 ps
CPU time 0.88 seconds
Started Jul 30 06:01:45 PM PDT 24
Finished Jul 30 06:01:46 PM PDT 24
Peak memory 197032 kb
Host smart-52540a7d-05d6-4c69-8653-2148cab10817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1508334252 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_dout_din_regs_random_rw.1508334252
Directory /workspace/0.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/0.gpio_filter_stress.1015201398
Short name T175
Test name
Test status
Simulation time 870156418 ps
CPU time 15.62 seconds
Started Jul 30 06:01:53 PM PDT 24
Finished Jul 30 06:02:09 PM PDT 24
Peak memory 198600 kb
Host smart-9b6ec7b1-9b9c-464f-af77-f6148c192ab3
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015201398 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_filter_stres
s.1015201398
Directory /workspace/0.gpio_filter_stress/latest

Test location /workspace/coverage/default/0.gpio_full_random.1559188590
Short name T274
Test name
Test status
Simulation time 80883468 ps
CPU time 0.69 seconds
Started Jul 30 06:01:48 PM PDT 24
Finished Jul 30 06:01:49 PM PDT 24
Peak memory 195664 kb
Host smart-2d59789f-01c8-49ca-8288-bffe4c6254e4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559188590 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_full_random.1559188590
Directory /workspace/0.gpio_full_random/latest

Test location /workspace/coverage/default/0.gpio_intr_rand_pgm.3192612614
Short name T317
Test name
Test status
Simulation time 155851776 ps
CPU time 1.47 seconds
Started Jul 30 06:01:51 PM PDT 24
Finished Jul 30 06:01:53 PM PDT 24
Peak memory 197592 kb
Host smart-d3341693-f6b8-440d-bf1f-d39ac6380218
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192612614 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_intr_rand_pgm.3192612614
Directory /workspace/0.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/0.gpio_intr_with_filter_rand_intr_event.838959458
Short name T602
Test name
Test status
Simulation time 48330532 ps
CPU time 2 seconds
Started Jul 30 06:01:46 PM PDT 24
Finished Jul 30 06:01:48 PM PDT 24
Peak memory 198508 kb
Host smart-9b811ec9-3dd4-4644-b9eb-465fdf4f4b39
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838959458 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 0.gpio_intr_with_filter_rand_intr_event.838959458
Directory /workspace/0.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/0.gpio_rand_intr_trigger.3445682779
Short name T258
Test name
Test status
Simulation time 154016605 ps
CPU time 3.49 seconds
Started Jul 30 06:01:45 PM PDT 24
Finished Jul 30 06:01:49 PM PDT 24
Peak memory 198632 kb
Host smart-820772ed-578a-4d0d-80f6-6540c9ef3c6b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445682779 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_rand_intr_trigger.
3445682779
Directory /workspace/0.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din.1081361631
Short name T706
Test name
Test status
Simulation time 77819101 ps
CPU time 1.44 seconds
Started Jul 30 06:01:46 PM PDT 24
Finished Jul 30 06:01:47 PM PDT 24
Peak memory 197632 kb
Host smart-bbe512e4-035c-4c38-8a20-6b7f216d6bf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081361631 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din.1081361631
Directory /workspace/0.gpio_random_dout_din/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din_no_pullup_pulldown.981344562
Short name T476
Test name
Test status
Simulation time 76708597 ps
CPU time 0.74 seconds
Started Jul 30 06:01:38 PM PDT 24
Finished Jul 30 06:01:39 PM PDT 24
Peak memory 196020 kb
Host smart-a722d27f-ff91-48f7-8921-db241e77d1c5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981344562 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din_no_pullup_
pulldown.981344562
Directory /workspace/0.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_random_long_reg_writes_reg_reads.1448395839
Short name T8
Test name
Test status
Simulation time 334727375 ps
CPU time 4.13 seconds
Started Jul 30 06:01:40 PM PDT 24
Finished Jul 30 06:01:44 PM PDT 24
Peak memory 198628 kb
Host smart-e7b2405c-0a1f-42ab-8a7c-926a5da6c04e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448395839 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_ran
dom_long_reg_writes_reg_reads.1448395839
Directory /workspace/0.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/0.gpio_sec_cm.3556646190
Short name T36
Test name
Test status
Simulation time 56164191 ps
CPU time 0.83 seconds
Started Jul 30 06:01:50 PM PDT 24
Finished Jul 30 06:01:51 PM PDT 24
Peak memory 214456 kb
Host smart-373d3aba-5478-4e89-af81-a8fbf6523117
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556646190 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_sec_cm.3556646190
Directory /workspace/0.gpio_sec_cm/latest

Test location /workspace/coverage/default/0.gpio_smoke.1338538741
Short name T359
Test name
Test status
Simulation time 127948072 ps
CPU time 0.87 seconds
Started Jul 30 06:01:44 PM PDT 24
Finished Jul 30 06:01:45 PM PDT 24
Peak memory 195952 kb
Host smart-089b4836-07e4-4d65-bec4-ccf6995df48c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1338538741 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke.1338538741
Directory /workspace/0.gpio_smoke/latest

Test location /workspace/coverage/default/0.gpio_smoke_no_pullup_pulldown.303249204
Short name T283
Test name
Test status
Simulation time 34574551 ps
CPU time 0.92 seconds
Started Jul 30 06:01:46 PM PDT 24
Finished Jul 30 06:01:47 PM PDT 24
Peak memory 196656 kb
Host smart-a31430bb-0950-4019-85d9-cfd69684da71
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303249204 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown.303249204
Directory /workspace/0.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_stress_all.3652371132
Short name T29
Test name
Test status
Simulation time 4430229023 ps
CPU time 62.61 seconds
Started Jul 30 06:01:47 PM PDT 24
Finished Jul 30 06:02:50 PM PDT 24
Peak memory 198788 kb
Host smart-67286f35-9cdd-46dd-bf81-981f029f7f06
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652371132 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.g
pio_stress_all.3652371132
Directory /workspace/0.gpio_stress_all/latest

Test location /workspace/coverage/default/1.gpio_alert_test.4226506272
Short name T234
Test name
Test status
Simulation time 11812274 ps
CPU time 0.64 seconds
Started Jul 30 06:01:49 PM PDT 24
Finished Jul 30 06:01:50 PM PDT 24
Peak memory 195200 kb
Host smart-3b53cb1d-171a-4ec2-ae7b-54221a46835a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226506272 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_alert_test.4226506272
Directory /workspace/1.gpio_alert_test/latest

Test location /workspace/coverage/default/1.gpio_dout_din_regs_random_rw.681963454
Short name T141
Test name
Test status
Simulation time 29723852 ps
CPU time 0.61 seconds
Started Jul 30 06:01:44 PM PDT 24
Finished Jul 30 06:01:44 PM PDT 24
Peak memory 194412 kb
Host smart-7f0aa9eb-4de3-47c3-b12f-68e34a1ddcd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=681963454 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_dout_din_regs_random_rw.681963454
Directory /workspace/1.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/1.gpio_filter_stress.1740171076
Short name T143
Test name
Test status
Simulation time 2468444285 ps
CPU time 21.92 seconds
Started Jul 30 06:01:46 PM PDT 24
Finished Jul 30 06:02:08 PM PDT 24
Peak memory 197568 kb
Host smart-93fad1c6-e87d-4ab2-8831-7cbbb2eae28d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740171076 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_filter_stres
s.1740171076
Directory /workspace/1.gpio_filter_stress/latest

Test location /workspace/coverage/default/1.gpio_full_random.737486071
Short name T323
Test name
Test status
Simulation time 489440518 ps
CPU time 0.91 seconds
Started Jul 30 06:01:44 PM PDT 24
Finished Jul 30 06:01:45 PM PDT 24
Peak memory 197220 kb
Host smart-680c6c81-35ba-4783-a13a-1d1eaa9dc41e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737486071 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_full_random.737486071
Directory /workspace/1.gpio_full_random/latest

Test location /workspace/coverage/default/1.gpio_intr_rand_pgm.2762411307
Short name T349
Test name
Test status
Simulation time 88550505 ps
CPU time 0.94 seconds
Started Jul 30 06:01:40 PM PDT 24
Finished Jul 30 06:01:41 PM PDT 24
Peak memory 196632 kb
Host smart-0655f618-0474-4c79-9262-58d716a0e958
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762411307 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_intr_rand_pgm.2762411307
Directory /workspace/1.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/1.gpio_intr_with_filter_rand_intr_event.24219143
Short name T389
Test name
Test status
Simulation time 26629587 ps
CPU time 1.08 seconds
Started Jul 30 06:01:46 PM PDT 24
Finished Jul 30 06:01:47 PM PDT 24
Peak memory 197640 kb
Host smart-56fcf28b-fb81-4e34-b84e-c802d72beaa5
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24219143 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 1.gpio_intr_with_filter_rand_intr_event.24219143
Directory /workspace/1.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/1.gpio_rand_intr_trigger.647839266
Short name T120
Test name
Test status
Simulation time 89602783 ps
CPU time 2.19 seconds
Started Jul 30 06:01:44 PM PDT 24
Finished Jul 30 06:01:46 PM PDT 24
Peak memory 197552 kb
Host smart-dda7a435-3b7b-4296-a6bc-198c4b178ac3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647839266 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_rand_intr_trigger.647839266
Directory /workspace/1.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din.3407756665
Short name T492
Test name
Test status
Simulation time 64387104 ps
CPU time 0.85 seconds
Started Jul 30 06:01:42 PM PDT 24
Finished Jul 30 06:01:43 PM PDT 24
Peak memory 196084 kb
Host smart-2e5c5b7f-f6f2-4975-8bd2-758c692449f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3407756665 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din.3407756665
Directory /workspace/1.gpio_random_dout_din/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din_no_pullup_pulldown.1613294956
Short name T671
Test name
Test status
Simulation time 25981417 ps
CPU time 0.81 seconds
Started Jul 30 06:02:01 PM PDT 24
Finished Jul 30 06:02:02 PM PDT 24
Peak memory 196616 kb
Host smart-410d71d2-ebd8-49c7-9777-56b13aea8502
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613294956 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din_no_pullup
_pulldown.1613294956
Directory /workspace/1.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_random_long_reg_writes_reg_reads.1050378980
Short name T568
Test name
Test status
Simulation time 227278002 ps
CPU time 3.96 seconds
Started Jul 30 06:01:34 PM PDT 24
Finished Jul 30 06:01:38 PM PDT 24
Peak memory 198600 kb
Host smart-3d0bacae-3834-4c57-816f-4914e1418a85
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050378980 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_ran
dom_long_reg_writes_reg_reads.1050378980
Directory /workspace/1.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/1.gpio_sec_cm.1318844274
Short name T51
Test name
Test status
Simulation time 1124347743 ps
CPU time 1.15 seconds
Started Jul 30 06:01:51 PM PDT 24
Finished Jul 30 06:01:52 PM PDT 24
Peak memory 215496 kb
Host smart-3a110891-abe1-430e-8028-2f8a7cf345cb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318844274 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_sec_cm.1318844274
Directory /workspace/1.gpio_sec_cm/latest

Test location /workspace/coverage/default/1.gpio_smoke.338830661
Short name T428
Test name
Test status
Simulation time 306624416 ps
CPU time 1.25 seconds
Started Jul 30 06:01:46 PM PDT 24
Finished Jul 30 06:01:47 PM PDT 24
Peak memory 197288 kb
Host smart-43bd6ff8-6d9b-4a4b-bc6e-a4c3cff5bd1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=338830661 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke.338830661
Directory /workspace/1.gpio_smoke/latest

Test location /workspace/coverage/default/1.gpio_smoke_no_pullup_pulldown.9694077
Short name T437
Test name
Test status
Simulation time 51191492 ps
CPU time 1.23 seconds
Started Jul 30 06:01:36 PM PDT 24
Finished Jul 30 06:01:37 PM PDT 24
Peak memory 197412 kb
Host smart-62cdbfc6-3ce7-42c6-84d8-49a6281b734c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9694077 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown.9694077
Directory /workspace/1.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_stress_all.862980044
Short name T136
Test name
Test status
Simulation time 9207723195 ps
CPU time 55.49 seconds
Started Jul 30 06:01:46 PM PDT 24
Finished Jul 30 06:02:41 PM PDT 24
Peak memory 198696 kb
Host smart-17a0ca01-d7bb-4018-b97d-705033c132e2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862980044 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gp
io_stress_all.862980044
Directory /workspace/1.gpio_stress_all/latest

Test location /workspace/coverage/default/10.gpio_alert_test.447594279
Short name T361
Test name
Test status
Simulation time 13027079 ps
CPU time 0.57 seconds
Started Jul 30 06:01:58 PM PDT 24
Finished Jul 30 06:01:59 PM PDT 24
Peak memory 194524 kb
Host smart-4bd681ab-bfa0-4022-bddb-01e69bbe8ad3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447594279 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_alert_test.447594279
Directory /workspace/10.gpio_alert_test/latest

Test location /workspace/coverage/default/10.gpio_dout_din_regs_random_rw.1487092419
Short name T216
Test name
Test status
Simulation time 45959848 ps
CPU time 0.78 seconds
Started Jul 30 06:01:56 PM PDT 24
Finished Jul 30 06:01:57 PM PDT 24
Peak memory 197092 kb
Host smart-1eaaeb85-ca4c-4ed8-a140-eac64f2fbf56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1487092419 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_dout_din_regs_random_rw.1487092419
Directory /workspace/10.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/10.gpio_filter_stress.3705112260
Short name T71
Test name
Test status
Simulation time 1596371351 ps
CPU time 11.64 seconds
Started Jul 30 06:02:00 PM PDT 24
Finished Jul 30 06:02:13 PM PDT 24
Peak memory 197520 kb
Host smart-2c62954b-c032-42a7-8bcb-416f6f5161d9
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705112260 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_filter_stre
ss.3705112260
Directory /workspace/10.gpio_filter_stress/latest

Test location /workspace/coverage/default/10.gpio_full_random.1513156764
Short name T497
Test name
Test status
Simulation time 544869598 ps
CPU time 0.97 seconds
Started Jul 30 06:02:01 PM PDT 24
Finished Jul 30 06:02:02 PM PDT 24
Peak memory 197700 kb
Host smart-b81aa2b8-7820-4bc1-bde1-248f99bac8c7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513156764 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_full_random.1513156764
Directory /workspace/10.gpio_full_random/latest

Test location /workspace/coverage/default/10.gpio_intr_rand_pgm.2426701670
Short name T478
Test name
Test status
Simulation time 151903367 ps
CPU time 1.52 seconds
Started Jul 30 06:02:00 PM PDT 24
Finished Jul 30 06:02:01 PM PDT 24
Peak memory 197688 kb
Host smart-17be5ab8-fa6b-4342-869f-101059265e21
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426701670 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_intr_rand_pgm.2426701670
Directory /workspace/10.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/10.gpio_intr_with_filter_rand_intr_event.443315930
Short name T640
Test name
Test status
Simulation time 86417628 ps
CPU time 1.73 seconds
Started Jul 30 06:01:55 PM PDT 24
Finished Jul 30 06:01:57 PM PDT 24
Peak memory 197972 kb
Host smart-fce580d5-c7fc-4694-8a44-90701e0e330b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443315930 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 10.gpio_intr_with_filter_rand_intr_event.443315930
Directory /workspace/10.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/10.gpio_rand_intr_trigger.4275247010
Short name T500
Test name
Test status
Simulation time 842024189 ps
CPU time 1.61 seconds
Started Jul 30 06:02:01 PM PDT 24
Finished Jul 30 06:02:03 PM PDT 24
Peak memory 196288 kb
Host smart-4480b576-6e44-4aaf-a06d-89763166a490
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275247010 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_rand_intr_trigger
.4275247010
Directory /workspace/10.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din.3644386582
Short name T164
Test name
Test status
Simulation time 29443399 ps
CPU time 0.68 seconds
Started Jul 30 06:02:01 PM PDT 24
Finished Jul 30 06:02:02 PM PDT 24
Peak memory 194768 kb
Host smart-e9058bb1-2951-4d07-93a8-87d3bab5b907
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3644386582 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din.3644386582
Directory /workspace/10.gpio_random_dout_din/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din_no_pullup_pulldown.3775514472
Short name T313
Test name
Test status
Simulation time 29310156 ps
CPU time 0.64 seconds
Started Jul 30 06:01:49 PM PDT 24
Finished Jul 30 06:01:49 PM PDT 24
Peak memory 194752 kb
Host smart-5427d33a-00f4-4410-9653-94fb88030353
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775514472 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din_no_pullu
p_pulldown.3775514472
Directory /workspace/10.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_random_long_reg_writes_reg_reads.412933557
Short name T658
Test name
Test status
Simulation time 393802857 ps
CPU time 4.47 seconds
Started Jul 30 06:01:53 PM PDT 24
Finished Jul 30 06:01:57 PM PDT 24
Peak memory 198484 kb
Host smart-176e0a77-2736-4be0-aaa6-b66a07a5b190
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412933557 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_ran
dom_long_reg_writes_reg_reads.412933557
Directory /workspace/10.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/10.gpio_smoke.2219794343
Short name T108
Test name
Test status
Simulation time 285863086 ps
CPU time 0.94 seconds
Started Jul 30 06:01:57 PM PDT 24
Finished Jul 30 06:01:58 PM PDT 24
Peak memory 196872 kb
Host smart-17044778-0725-42d0-9419-cc16a166a772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2219794343 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke.2219794343
Directory /workspace/10.gpio_smoke/latest

Test location /workspace/coverage/default/10.gpio_smoke_no_pullup_pulldown.3991590204
Short name T616
Test name
Test status
Simulation time 87737091 ps
CPU time 0.89 seconds
Started Jul 30 06:01:56 PM PDT 24
Finished Jul 30 06:01:57 PM PDT 24
Peak memory 196928 kb
Host smart-e1f53a63-9b33-4cf0-b23f-9977c26cf32f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991590204 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown.3991590204
Directory /workspace/10.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_stress_all.2775467876
Short name T481
Test name
Test status
Simulation time 3196817384 ps
CPU time 24.12 seconds
Started Jul 30 06:02:01 PM PDT 24
Finished Jul 30 06:02:26 PM PDT 24
Peak memory 198764 kb
Host smart-5b998238-51d3-471e-916b-000dac041501
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775467876 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.
gpio_stress_all.2775467876
Directory /workspace/10.gpio_stress_all/latest

Test location /workspace/coverage/default/11.gpio_dout_din_regs_random_rw.2173718830
Short name T446
Test name
Test status
Simulation time 58252283 ps
CPU time 0.64 seconds
Started Jul 30 06:01:55 PM PDT 24
Finished Jul 30 06:01:56 PM PDT 24
Peak memory 194432 kb
Host smart-59e28eba-e5d4-497b-96e3-c2f1d6049a6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2173718830 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_dout_din_regs_random_rw.2173718830
Directory /workspace/11.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/11.gpio_filter_stress.4007891263
Short name T448
Test name
Test status
Simulation time 263960032 ps
CPU time 8.91 seconds
Started Jul 30 06:02:00 PM PDT 24
Finished Jul 30 06:02:09 PM PDT 24
Peak memory 197532 kb
Host smart-ce9f8da1-16d9-4fec-8aee-b3e0eeed412d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007891263 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_filter_stre
ss.4007891263
Directory /workspace/11.gpio_filter_stress/latest

Test location /workspace/coverage/default/11.gpio_full_random.2739712997
Short name T112
Test name
Test status
Simulation time 148417334 ps
CPU time 0.89 seconds
Started Jul 30 06:02:02 PM PDT 24
Finished Jul 30 06:02:04 PM PDT 24
Peak memory 196548 kb
Host smart-b447bbd5-6a5d-41e5-990b-efed4956cb68
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739712997 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_full_random.2739712997
Directory /workspace/11.gpio_full_random/latest

Test location /workspace/coverage/default/11.gpio_intr_rand_pgm.2137602575
Short name T708
Test name
Test status
Simulation time 38422459 ps
CPU time 0.71 seconds
Started Jul 30 06:02:00 PM PDT 24
Finished Jul 30 06:02:01 PM PDT 24
Peak memory 195900 kb
Host smart-275e0d58-6a3c-410e-a4d5-83851f8021c9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137602575 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_intr_rand_pgm.2137602575
Directory /workspace/11.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/11.gpio_intr_with_filter_rand_intr_event.1949791567
Short name T622
Test name
Test status
Simulation time 38761014 ps
CPU time 1.07 seconds
Started Jul 30 06:02:01 PM PDT 24
Finished Jul 30 06:02:02 PM PDT 24
Peak memory 196464 kb
Host smart-7334b8de-b0e3-4c35-b5c4-46fe7f567c91
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949791567 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.gpio_intr_with_filter_rand_intr_event.1949791567
Directory /workspace/11.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/11.gpio_rand_intr_trigger.1284252389
Short name T532
Test name
Test status
Simulation time 306865697 ps
CPU time 1.78 seconds
Started Jul 30 06:01:54 PM PDT 24
Finished Jul 30 06:01:56 PM PDT 24
Peak memory 197384 kb
Host smart-526d8988-158d-445e-a1af-8edf807ada93
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284252389 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_rand_intr_trigger
.1284252389
Directory /workspace/11.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din.465382779
Short name T151
Test name
Test status
Simulation time 265450294 ps
CPU time 1.24 seconds
Started Jul 30 06:01:51 PM PDT 24
Finished Jul 30 06:01:53 PM PDT 24
Peak memory 197176 kb
Host smart-c1473d02-6b82-466f-9150-ae65db036433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=465382779 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din.465382779
Directory /workspace/11.gpio_random_dout_din/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din_no_pullup_pulldown.288772151
Short name T621
Test name
Test status
Simulation time 22093031 ps
CPU time 0.84 seconds
Started Jul 30 06:01:58 PM PDT 24
Finished Jul 30 06:01:59 PM PDT 24
Peak memory 196668 kb
Host smart-a0772f36-88a6-499a-a610-b9b0549711ac
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288772151 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din_no_pullup
_pulldown.288772151
Directory /workspace/11.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_random_long_reg_writes_reg_reads.2240249938
Short name T477
Test name
Test status
Simulation time 149687695 ps
CPU time 2.3 seconds
Started Jul 30 06:02:02 PM PDT 24
Finished Jul 30 06:02:04 PM PDT 24
Peak memory 198604 kb
Host smart-ea840fb5-306d-4ece-92c0-32da840ab1d0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240249938 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_ra
ndom_long_reg_writes_reg_reads.2240249938
Directory /workspace/11.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/11.gpio_smoke.1556324154
Short name T193
Test name
Test status
Simulation time 447885476 ps
CPU time 0.72 seconds
Started Jul 30 06:02:05 PM PDT 24
Finished Jul 30 06:02:06 PM PDT 24
Peak memory 196536 kb
Host smart-3cf6ca7d-6517-4305-86b4-89659273de0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556324154 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke.1556324154
Directory /workspace/11.gpio_smoke/latest

Test location /workspace/coverage/default/11.gpio_smoke_no_pullup_pulldown.3286182919
Short name T345
Test name
Test status
Simulation time 49493211 ps
CPU time 1.25 seconds
Started Jul 30 06:01:59 PM PDT 24
Finished Jul 30 06:02:00 PM PDT 24
Peak memory 197328 kb
Host smart-11d88005-182b-445f-ade1-cb80e8651b4e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286182919 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown.3286182919
Directory /workspace/11.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_stress_all.839417506
Short name T144
Test name
Test status
Simulation time 9885059379 ps
CPU time 155.17 seconds
Started Jul 30 06:01:59 PM PDT 24
Finished Jul 30 06:04:35 PM PDT 24
Peak memory 198580 kb
Host smart-a29cb242-dfe5-450b-91a9-67cd1ec35f24
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839417506 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.g
pio_stress_all.839417506
Directory /workspace/11.gpio_stress_all/latest

Test location /workspace/coverage/default/11.gpio_stress_all_with_rand_reset.2925758501
Short name T98
Test name
Test status
Simulation time 44792996170 ps
CPU time 1177.15 seconds
Started Jul 30 06:02:05 PM PDT 24
Finished Jul 30 06:21:43 PM PDT 24
Peak memory 198808 kb
Host smart-9b69a211-b6bc-4e42-a72e-4982db0df7ce
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2925758501 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_stress_all_with_rand_reset.2925758501
Directory /workspace/11.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.gpio_alert_test.1495749863
Short name T155
Test name
Test status
Simulation time 18378329 ps
CPU time 0.65 seconds
Started Jul 30 06:02:02 PM PDT 24
Finished Jul 30 06:02:03 PM PDT 24
Peak memory 194752 kb
Host smart-cb1d9887-a574-49a3-b65f-c7e72043105f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495749863 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_alert_test.1495749863
Directory /workspace/12.gpio_alert_test/latest

Test location /workspace/coverage/default/12.gpio_dout_din_regs_random_rw.1068721540
Short name T570
Test name
Test status
Simulation time 30790407 ps
CPU time 0.72 seconds
Started Jul 30 06:02:01 PM PDT 24
Finished Jul 30 06:02:02 PM PDT 24
Peak memory 196424 kb
Host smart-42d604c8-116f-4cdb-9c22-56c9f8f1d1b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1068721540 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_dout_din_regs_random_rw.1068721540
Directory /workspace/12.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/12.gpio_filter_stress.995265119
Short name T560
Test name
Test status
Simulation time 12867052096 ps
CPU time 22.64 seconds
Started Jul 30 06:02:01 PM PDT 24
Finished Jul 30 06:02:24 PM PDT 24
Peak memory 197504 kb
Host smart-e4a98cf5-b1f3-4981-9ba1-98adbf154355
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995265119 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_filter_stres
s.995265119
Directory /workspace/12.gpio_filter_stress/latest

Test location /workspace/coverage/default/12.gpio_full_random.3355635055
Short name T712
Test name
Test status
Simulation time 63159910 ps
CPU time 0.95 seconds
Started Jul 30 06:01:56 PM PDT 24
Finished Jul 30 06:01:57 PM PDT 24
Peak memory 197096 kb
Host smart-89be2ef6-53ef-4f61-a72c-0efcab489811
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355635055 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_full_random.3355635055
Directory /workspace/12.gpio_full_random/latest

Test location /workspace/coverage/default/12.gpio_intr_rand_pgm.174570575
Short name T297
Test name
Test status
Simulation time 75538056 ps
CPU time 1.25 seconds
Started Jul 30 06:01:59 PM PDT 24
Finished Jul 30 06:02:00 PM PDT 24
Peak memory 196352 kb
Host smart-1f8d1933-c661-4276-905f-6db48dd4940d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174570575 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_intr_rand_pgm.174570575
Directory /workspace/12.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/12.gpio_intr_with_filter_rand_intr_event.617294780
Short name T146
Test name
Test status
Simulation time 43790196 ps
CPU time 1.87 seconds
Started Jul 30 06:02:02 PM PDT 24
Finished Jul 30 06:02:04 PM PDT 24
Peak memory 198752 kb
Host smart-76159c40-0819-40d4-a4f9-fc005a4fbd81
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617294780 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 12.gpio_intr_with_filter_rand_intr_event.617294780
Directory /workspace/12.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/12.gpio_rand_intr_trigger.1001742938
Short name T546
Test name
Test status
Simulation time 114299960 ps
CPU time 1.08 seconds
Started Jul 30 06:02:03 PM PDT 24
Finished Jul 30 06:02:04 PM PDT 24
Peak memory 196080 kb
Host smart-dd57c71c-f3be-458c-ba12-ac6ac5d2c9ed
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001742938 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_rand_intr_trigger
.1001742938
Directory /workspace/12.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din.558121815
Short name T461
Test name
Test status
Simulation time 201082924 ps
CPU time 0.97 seconds
Started Jul 30 06:01:59 PM PDT 24
Finished Jul 30 06:02:00 PM PDT 24
Peak memory 196632 kb
Host smart-aa250fc8-00b3-4921-a69d-6cdc46c61bdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=558121815 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din.558121815
Directory /workspace/12.gpio_random_dout_din/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din_no_pullup_pulldown.2069022031
Short name T668
Test name
Test status
Simulation time 155917927 ps
CPU time 1.14 seconds
Started Jul 30 06:01:57 PM PDT 24
Finished Jul 30 06:01:58 PM PDT 24
Peak memory 196380 kb
Host smart-4a505c43-f00a-4695-942c-beef7f58f1c0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069022031 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din_no_pullu
p_pulldown.2069022031
Directory /workspace/12.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_random_long_reg_writes_reg_reads.453907560
Short name T388
Test name
Test status
Simulation time 174878590 ps
CPU time 5.74 seconds
Started Jul 30 06:02:02 PM PDT 24
Finished Jul 30 06:02:08 PM PDT 24
Peak memory 198584 kb
Host smart-06e36ff6-bc53-4858-8384-371396cb455e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453907560 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_ran
dom_long_reg_writes_reg_reads.453907560
Directory /workspace/12.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/12.gpio_smoke.3586419393
Short name T518
Test name
Test status
Simulation time 839736417 ps
CPU time 1.14 seconds
Started Jul 30 06:01:56 PM PDT 24
Finished Jul 30 06:01:58 PM PDT 24
Peak memory 196964 kb
Host smart-d621178e-8866-4b15-9bb0-c137e6443530
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3586419393 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke.3586419393
Directory /workspace/12.gpio_smoke/latest

Test location /workspace/coverage/default/12.gpio_smoke_no_pullup_pulldown.569851588
Short name T539
Test name
Test status
Simulation time 309924652 ps
CPU time 0.96 seconds
Started Jul 30 06:02:01 PM PDT 24
Finished Jul 30 06:02:03 PM PDT 24
Peak memory 195892 kb
Host smart-d2315f89-27bf-4622-8db8-306a47e31e59
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569851588 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown.569851588
Directory /workspace/12.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_stress_all.1200465240
Short name T6
Test name
Test status
Simulation time 8573228201 ps
CPU time 100.13 seconds
Started Jul 30 06:02:03 PM PDT 24
Finished Jul 30 06:03:43 PM PDT 24
Peak memory 198760 kb
Host smart-cad6c241-2411-4b1d-ab43-3ba2ef8c2b88
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200465240 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.
gpio_stress_all.1200465240
Directory /workspace/12.gpio_stress_all/latest

Test location /workspace/coverage/default/12.gpio_stress_all_with_rand_reset.871355847
Short name T60
Test name
Test status
Simulation time 846041308174 ps
CPU time 2172.74 seconds
Started Jul 30 06:01:55 PM PDT 24
Finished Jul 30 06:38:08 PM PDT 24
Peak memory 198920 kb
Host smart-74eafdf6-4114-4c97-b591-6d1c57f58da1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=871355847 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_stress_all_with_rand_reset.871355847
Directory /workspace/12.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.gpio_alert_test.319096193
Short name T412
Test name
Test status
Simulation time 24142595 ps
CPU time 0.6 seconds
Started Jul 30 06:01:57 PM PDT 24
Finished Jul 30 06:01:58 PM PDT 24
Peak memory 194712 kb
Host smart-f91ff1bd-27e3-4c5c-837b-47b952fbe9ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319096193 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_alert_test.319096193
Directory /workspace/13.gpio_alert_test/latest

Test location /workspace/coverage/default/13.gpio_dout_din_regs_random_rw.2591589670
Short name T11
Test name
Test status
Simulation time 98437792 ps
CPU time 0.9 seconds
Started Jul 30 06:01:57 PM PDT 24
Finished Jul 30 06:01:58 PM PDT 24
Peak memory 197888 kb
Host smart-7389ff32-3247-4307-9f83-fd0d76deeaa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2591589670 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_dout_din_regs_random_rw.2591589670
Directory /workspace/13.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/13.gpio_filter_stress.3296480459
Short name T116
Test name
Test status
Simulation time 676541104 ps
CPU time 22.53 seconds
Started Jul 30 06:02:00 PM PDT 24
Finished Jul 30 06:02:23 PM PDT 24
Peak memory 196176 kb
Host smart-2b89408d-cefd-4f71-a834-7e821fb93c56
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296480459 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_filter_stre
ss.3296480459
Directory /workspace/13.gpio_filter_stress/latest

Test location /workspace/coverage/default/13.gpio_full_random.2357867548
Short name T321
Test name
Test status
Simulation time 57876666 ps
CPU time 0.9 seconds
Started Jul 30 06:01:59 PM PDT 24
Finished Jul 30 06:02:00 PM PDT 24
Peak memory 198176 kb
Host smart-17e3f150-267c-4bb9-8921-18a4f878eff9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357867548 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_full_random.2357867548
Directory /workspace/13.gpio_full_random/latest

Test location /workspace/coverage/default/13.gpio_intr_rand_pgm.3130504135
Short name T277
Test name
Test status
Simulation time 75931271 ps
CPU time 1.15 seconds
Started Jul 30 06:01:59 PM PDT 24
Finished Jul 30 06:02:00 PM PDT 24
Peak memory 197228 kb
Host smart-eaf43e4a-daae-4864-8983-8b29088800d7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130504135 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_intr_rand_pgm.3130504135
Directory /workspace/13.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/13.gpio_intr_with_filter_rand_intr_event.3953827820
Short name T266
Test name
Test status
Simulation time 170073801 ps
CPU time 1.88 seconds
Started Jul 30 06:02:05 PM PDT 24
Finished Jul 30 06:02:07 PM PDT 24
Peak memory 198564 kb
Host smart-0de9ae9a-fe29-4b74-8caf-eda313976bc7
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953827820 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 13.gpio_intr_with_filter_rand_intr_event.3953827820
Directory /workspace/13.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/13.gpio_rand_intr_trigger.1517010221
Short name T587
Test name
Test status
Simulation time 165094223 ps
CPU time 1.46 seconds
Started Jul 30 06:01:51 PM PDT 24
Finished Jul 30 06:01:53 PM PDT 24
Peak memory 196664 kb
Host smart-72a67795-df8e-4fe7-bed3-adeb5667bcf1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517010221 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_rand_intr_trigger
.1517010221
Directory /workspace/13.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din.2564449168
Short name T55
Test name
Test status
Simulation time 20028277 ps
CPU time 0.73 seconds
Started Jul 30 06:01:59 PM PDT 24
Finished Jul 30 06:02:00 PM PDT 24
Peak memory 195904 kb
Host smart-1aebdd86-4039-4646-a8ff-61526c06df65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2564449168 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din.2564449168
Directory /workspace/13.gpio_random_dout_din/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din_no_pullup_pulldown.2614905780
Short name T646
Test name
Test status
Simulation time 93186057 ps
CPU time 1.16 seconds
Started Jul 30 06:01:56 PM PDT 24
Finished Jul 30 06:01:57 PM PDT 24
Peak memory 197472 kb
Host smart-c00f4128-568e-460d-afe4-dad0e67520ca
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614905780 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din_no_pullu
p_pulldown.2614905780
Directory /workspace/13.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_random_long_reg_writes_reg_reads.3599837568
Short name T557
Test name
Test status
Simulation time 379104948 ps
CPU time 5.32 seconds
Started Jul 30 06:01:57 PM PDT 24
Finished Jul 30 06:02:03 PM PDT 24
Peak memory 198528 kb
Host smart-7e58e7a9-aa25-4245-a77a-d47057855f78
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599837568 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_ra
ndom_long_reg_writes_reg_reads.3599837568
Directory /workspace/13.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/13.gpio_smoke.3655524402
Short name T221
Test name
Test status
Simulation time 80704127 ps
CPU time 1.27 seconds
Started Jul 30 06:01:56 PM PDT 24
Finished Jul 30 06:01:57 PM PDT 24
Peak memory 196432 kb
Host smart-9dd6e23d-d65b-4438-bf48-daef9dc05d84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3655524402 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke.3655524402
Directory /workspace/13.gpio_smoke/latest

Test location /workspace/coverage/default/13.gpio_smoke_no_pullup_pulldown.2522063320
Short name T215
Test name
Test status
Simulation time 366925523 ps
CPU time 1.02 seconds
Started Jul 30 06:01:57 PM PDT 24
Finished Jul 30 06:01:59 PM PDT 24
Peak memory 196860 kb
Host smart-6e71b9be-2146-45cd-bd8f-8dbf5ebcf87e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522063320 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown.2522063320
Directory /workspace/13.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_stress_all.643254195
Short name T432
Test name
Test status
Simulation time 1535678501 ps
CPU time 21.15 seconds
Started Jul 30 06:02:01 PM PDT 24
Finished Jul 30 06:02:23 PM PDT 24
Peak memory 198540 kb
Host smart-ed7a900c-fd04-4de6-bdf4-c082e2a5835e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643254195 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.g
pio_stress_all.643254195
Directory /workspace/13.gpio_stress_all/latest

Test location /workspace/coverage/default/14.gpio_alert_test.766050496
Short name T659
Test name
Test status
Simulation time 15660727 ps
CPU time 0.58 seconds
Started Jul 30 06:01:59 PM PDT 24
Finished Jul 30 06:02:00 PM PDT 24
Peak memory 194484 kb
Host smart-035486c9-67e7-4a97-9c89-1b4fc29f4458
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766050496 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_alert_test.766050496
Directory /workspace/14.gpio_alert_test/latest

Test location /workspace/coverage/default/14.gpio_dout_din_regs_random_rw.57240924
Short name T672
Test name
Test status
Simulation time 71679734 ps
CPU time 0.86 seconds
Started Jul 30 06:01:57 PM PDT 24
Finished Jul 30 06:01:58 PM PDT 24
Peak memory 196668 kb
Host smart-5c82d8b2-91f2-432c-b532-cdcec934f648
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57240924 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_dout_din_regs_random_rw.57240924
Directory /workspace/14.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/14.gpio_filter_stress.806498624
Short name T403
Test name
Test status
Simulation time 213649169 ps
CPU time 10.23 seconds
Started Jul 30 06:01:59 PM PDT 24
Finished Jul 30 06:02:10 PM PDT 24
Peak memory 197652 kb
Host smart-3e33855c-7f7d-4426-89ed-e8517ca6b2d6
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806498624 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_filter_stres
s.806498624
Directory /workspace/14.gpio_filter_stress/latest

Test location /workspace/coverage/default/14.gpio_full_random.1312368284
Short name T222
Test name
Test status
Simulation time 34319156 ps
CPU time 0.71 seconds
Started Jul 30 06:02:03 PM PDT 24
Finished Jul 30 06:02:03 PM PDT 24
Peak memory 195956 kb
Host smart-0060ec2e-204f-4417-9bab-07859e66022d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312368284 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_full_random.1312368284
Directory /workspace/14.gpio_full_random/latest

Test location /workspace/coverage/default/14.gpio_intr_rand_pgm.1917262609
Short name T19
Test name
Test status
Simulation time 91626197 ps
CPU time 1.28 seconds
Started Jul 30 06:01:55 PM PDT 24
Finished Jul 30 06:01:56 PM PDT 24
Peak memory 197676 kb
Host smart-825b187d-aae1-48a7-8c77-9b83284c78db
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917262609 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_intr_rand_pgm.1917262609
Directory /workspace/14.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/14.gpio_intr_with_filter_rand_intr_event.3222741092
Short name T623
Test name
Test status
Simulation time 24462530 ps
CPU time 1.07 seconds
Started Jul 30 06:01:57 PM PDT 24
Finished Jul 30 06:01:58 PM PDT 24
Peak memory 197628 kb
Host smart-652c1a9f-2eea-449b-87c5-977eaebfee6b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222741092 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.gpio_intr_with_filter_rand_intr_event.3222741092
Directory /workspace/14.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/14.gpio_rand_intr_trigger.1439161637
Short name T113
Test name
Test status
Simulation time 295128345 ps
CPU time 2.04 seconds
Started Jul 30 06:02:01 PM PDT 24
Finished Jul 30 06:02:03 PM PDT 24
Peak memory 196652 kb
Host smart-fc3bc92a-626c-4fce-b821-eb125b1e4533
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439161637 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_rand_intr_trigger
.1439161637
Directory /workspace/14.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din.3586345401
Short name T386
Test name
Test status
Simulation time 40315038 ps
CPU time 0.84 seconds
Started Jul 30 06:01:56 PM PDT 24
Finished Jul 30 06:01:57 PM PDT 24
Peak memory 196812 kb
Host smart-9c7dec38-a80a-46f0-9bee-a4f85c4d386c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3586345401 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din.3586345401
Directory /workspace/14.gpio_random_dout_din/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din_no_pullup_pulldown.4038667382
Short name T595
Test name
Test status
Simulation time 21102450 ps
CPU time 0.69 seconds
Started Jul 30 06:02:03 PM PDT 24
Finished Jul 30 06:02:04 PM PDT 24
Peak memory 195912 kb
Host smart-100b63a7-15ce-4ff7-b930-f2f6f9dfc897
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038667382 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din_no_pullu
p_pulldown.4038667382
Directory /workspace/14.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_random_long_reg_writes_reg_reads.2916810173
Short name T600
Test name
Test status
Simulation time 126801624 ps
CPU time 2.82 seconds
Started Jul 30 06:01:57 PM PDT 24
Finished Jul 30 06:02:00 PM PDT 24
Peak memory 198536 kb
Host smart-a77a224e-d256-4522-856d-c9714ddab3d3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916810173 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_ra
ndom_long_reg_writes_reg_reads.2916810173
Directory /workspace/14.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/14.gpio_smoke.4094126550
Short name T650
Test name
Test status
Simulation time 98842390 ps
CPU time 1.01 seconds
Started Jul 30 06:02:03 PM PDT 24
Finished Jul 30 06:02:05 PM PDT 24
Peak memory 197056 kb
Host smart-c9687ef2-d365-4fce-b579-98b1ebe6448f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4094126550 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke.4094126550
Directory /workspace/14.gpio_smoke/latest

Test location /workspace/coverage/default/14.gpio_smoke_no_pullup_pulldown.3756092044
Short name T397
Test name
Test status
Simulation time 730406180 ps
CPU time 1.44 seconds
Started Jul 30 06:01:53 PM PDT 24
Finished Jul 30 06:01:54 PM PDT 24
Peak memory 197328 kb
Host smart-464a5cba-7744-401d-98c5-56186b4996fe
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756092044 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown.3756092044
Directory /workspace/14.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_stress_all.1913546324
Short name T711
Test name
Test status
Simulation time 24317148441 ps
CPU time 166.69 seconds
Started Jul 30 06:02:05 PM PDT 24
Finished Jul 30 06:04:52 PM PDT 24
Peak memory 198672 kb
Host smart-183199ce-f42c-4c77-97f0-473ce4b15494
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913546324 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.
gpio_stress_all.1913546324
Directory /workspace/14.gpio_stress_all/latest

Test location /workspace/coverage/default/15.gpio_alert_test.2895864882
Short name T579
Test name
Test status
Simulation time 25077291 ps
CPU time 0.59 seconds
Started Jul 30 06:01:59 PM PDT 24
Finished Jul 30 06:02:00 PM PDT 24
Peak memory 194464 kb
Host smart-912271b6-b8c4-46f1-bc8d-c983fc28f64d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895864882 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_alert_test.2895864882
Directory /workspace/15.gpio_alert_test/latest

Test location /workspace/coverage/default/15.gpio_dout_din_regs_random_rw.1911138050
Short name T670
Test name
Test status
Simulation time 63060910 ps
CPU time 1.01 seconds
Started Jul 30 06:02:03 PM PDT 24
Finished Jul 30 06:02:04 PM PDT 24
Peak memory 196344 kb
Host smart-b92b2651-8c34-4bb5-8665-ad4fbf4e02cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1911138050 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_dout_din_regs_random_rw.1911138050
Directory /workspace/15.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/15.gpio_filter_stress.1537420665
Short name T523
Test name
Test status
Simulation time 3623587297 ps
CPU time 22.86 seconds
Started Jul 30 06:02:00 PM PDT 24
Finished Jul 30 06:02:24 PM PDT 24
Peak memory 198148 kb
Host smart-56f47dc6-0122-4ad2-bfde-58531af27a5b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537420665 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_filter_stre
ss.1537420665
Directory /workspace/15.gpio_filter_stress/latest

Test location /workspace/coverage/default/15.gpio_full_random.1892149256
Short name T597
Test name
Test status
Simulation time 307985361 ps
CPU time 0.89 seconds
Started Jul 30 06:01:57 PM PDT 24
Finished Jul 30 06:01:58 PM PDT 24
Peak memory 196436 kb
Host smart-113f7b8e-5c9c-43fe-bc17-87775af82206
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892149256 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_full_random.1892149256
Directory /workspace/15.gpio_full_random/latest

Test location /workspace/coverage/default/15.gpio_intr_rand_pgm.1915792893
Short name T270
Test name
Test status
Simulation time 32493659 ps
CPU time 0.91 seconds
Started Jul 30 06:01:54 PM PDT 24
Finished Jul 30 06:01:55 PM PDT 24
Peak memory 196392 kb
Host smart-7d3f1de8-26a1-42fb-8e6d-8ef4ffe130fc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915792893 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_intr_rand_pgm.1915792893
Directory /workspace/15.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/15.gpio_intr_with_filter_rand_intr_event.3832363016
Short name T689
Test name
Test status
Simulation time 80258064 ps
CPU time 3.05 seconds
Started Jul 30 06:01:53 PM PDT 24
Finished Jul 30 06:01:56 PM PDT 24
Peak memory 198760 kb
Host smart-14c04653-8071-4212-8d4a-47a80b1a8bb2
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832363016 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.gpio_intr_with_filter_rand_intr_event.3832363016
Directory /workspace/15.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/15.gpio_rand_intr_trigger.840143069
Short name T521
Test name
Test status
Simulation time 1529658900 ps
CPU time 2.85 seconds
Started Jul 30 06:02:02 PM PDT 24
Finished Jul 30 06:02:05 PM PDT 24
Peak memory 197552 kb
Host smart-7d2679a1-52c3-4ed2-8b20-9f62a05ba24f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840143069 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_rand_intr_trigger.
840143069
Directory /workspace/15.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din.65993122
Short name T522
Test name
Test status
Simulation time 144921637 ps
CPU time 1.29 seconds
Started Jul 30 06:02:05 PM PDT 24
Finished Jul 30 06:02:06 PM PDT 24
Peak memory 197512 kb
Host smart-1f504fa1-3932-4c21-a296-e51dc8155774
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65993122 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din.65993122
Directory /workspace/15.gpio_random_dout_din/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din_no_pullup_pulldown.3081358441
Short name T455
Test name
Test status
Simulation time 32708569 ps
CPU time 1.07 seconds
Started Jul 30 06:02:06 PM PDT 24
Finished Jul 30 06:02:07 PM PDT 24
Peak memory 196636 kb
Host smart-b34ab45a-2258-48c0-8fed-36c99d0328c0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081358441 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din_no_pullu
p_pulldown.3081358441
Directory /workspace/15.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_random_long_reg_writes_reg_reads.2463924248
Short name T633
Test name
Test status
Simulation time 244006479 ps
CPU time 4.45 seconds
Started Jul 30 06:02:00 PM PDT 24
Finished Jul 30 06:02:05 PM PDT 24
Peak memory 198508 kb
Host smart-205e4143-bf30-4e9d-82f2-dac4c51d8dc3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463924248 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_ra
ndom_long_reg_writes_reg_reads.2463924248
Directory /workspace/15.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/15.gpio_smoke.3171805447
Short name T110
Test name
Test status
Simulation time 58098202 ps
CPU time 1.15 seconds
Started Jul 30 06:02:03 PM PDT 24
Finished Jul 30 06:02:04 PM PDT 24
Peak memory 196916 kb
Host smart-435e66f7-404d-4ad0-b0b3-8c58aa2ea69e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3171805447 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke.3171805447
Directory /workspace/15.gpio_smoke/latest

Test location /workspace/coverage/default/15.gpio_smoke_no_pullup_pulldown.2198666403
Short name T37
Test name
Test status
Simulation time 135265839 ps
CPU time 1.14 seconds
Started Jul 30 06:01:51 PM PDT 24
Finished Jul 30 06:01:52 PM PDT 24
Peak memory 197016 kb
Host smart-c7f9fe39-da13-4eee-9415-c0a75d951582
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198666403 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown.2198666403
Directory /workspace/15.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_stress_all.4145118543
Short name T210
Test name
Test status
Simulation time 3514332605 ps
CPU time 91.23 seconds
Started Jul 30 06:01:57 PM PDT 24
Finished Jul 30 06:03:28 PM PDT 24
Peak memory 198688 kb
Host smart-9aabc4ce-23de-4b29-8b33-ee0fd6b6e4cf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145118543 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.
gpio_stress_all.4145118543
Directory /workspace/15.gpio_stress_all/latest

Test location /workspace/coverage/default/16.gpio_alert_test.1176032068
Short name T201
Test name
Test status
Simulation time 62351507 ps
CPU time 0.61 seconds
Started Jul 30 06:02:01 PM PDT 24
Finished Jul 30 06:02:02 PM PDT 24
Peak memory 194316 kb
Host smart-7452b615-c00e-461e-97d6-e167df48ee05
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176032068 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_alert_test.1176032068
Directory /workspace/16.gpio_alert_test/latest

Test location /workspace/coverage/default/16.gpio_dout_din_regs_random_rw.3870337236
Short name T314
Test name
Test status
Simulation time 58744463 ps
CPU time 0.66 seconds
Started Jul 30 06:01:59 PM PDT 24
Finished Jul 30 06:02:00 PM PDT 24
Peak memory 195140 kb
Host smart-f6e1b286-a022-4033-95e1-162917f564a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3870337236 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_dout_din_regs_random_rw.3870337236
Directory /workspace/16.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/16.gpio_filter_stress.2849681220
Short name T205
Test name
Test status
Simulation time 2151991588 ps
CPU time 27.56 seconds
Started Jul 30 06:02:05 PM PDT 24
Finished Jul 30 06:02:32 PM PDT 24
Peak memory 198540 kb
Host smart-bed92078-ed00-4e41-a9df-fb940a737ea9
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849681220 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_filter_stre
ss.2849681220
Directory /workspace/16.gpio_filter_stress/latest

Test location /workspace/coverage/default/16.gpio_full_random.2460287490
Short name T510
Test name
Test status
Simulation time 142571220 ps
CPU time 0.93 seconds
Started Jul 30 06:01:57 PM PDT 24
Finished Jul 30 06:01:58 PM PDT 24
Peak memory 198360 kb
Host smart-fc6bac79-e029-470a-8b48-003fa7c711c2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460287490 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_full_random.2460287490
Directory /workspace/16.gpio_full_random/latest

Test location /workspace/coverage/default/16.gpio_intr_rand_pgm.4089925467
Short name T431
Test name
Test status
Simulation time 109232537 ps
CPU time 1.1 seconds
Started Jul 30 06:02:01 PM PDT 24
Finished Jul 30 06:02:02 PM PDT 24
Peak memory 197392 kb
Host smart-3367bc72-0150-4072-8afb-7446af5823a6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089925467 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_intr_rand_pgm.4089925467
Directory /workspace/16.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/16.gpio_intr_with_filter_rand_intr_event.1202704351
Short name T311
Test name
Test status
Simulation time 223112462 ps
CPU time 2.62 seconds
Started Jul 30 06:01:57 PM PDT 24
Finished Jul 30 06:02:00 PM PDT 24
Peak memory 198536 kb
Host smart-bf810eff-27fa-49fe-87a7-b176b78c2cf8
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202704351 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.gpio_intr_with_filter_rand_intr_event.1202704351
Directory /workspace/16.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/16.gpio_rand_intr_trigger.2382672344
Short name T453
Test name
Test status
Simulation time 85448616 ps
CPU time 1.84 seconds
Started Jul 30 06:01:56 PM PDT 24
Finished Jul 30 06:01:58 PM PDT 24
Peak memory 196016 kb
Host smart-1d3f1444-971c-4f40-9536-0092c6662aae
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382672344 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_rand_intr_trigger
.2382672344
Directory /workspace/16.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din.4278527769
Short name T680
Test name
Test status
Simulation time 22615001 ps
CPU time 0.91 seconds
Started Jul 30 06:02:01 PM PDT 24
Finished Jul 30 06:02:03 PM PDT 24
Peak memory 197316 kb
Host smart-c18cd7dd-716f-4fa3-8fcb-6a6ca9d49001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4278527769 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din.4278527769
Directory /workspace/16.gpio_random_dout_din/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din_no_pullup_pulldown.3620239740
Short name T410
Test name
Test status
Simulation time 66875718 ps
CPU time 0.74 seconds
Started Jul 30 06:02:01 PM PDT 24
Finished Jul 30 06:02:02 PM PDT 24
Peak memory 195984 kb
Host smart-1c3096d8-0f91-4170-81d9-f0e183bb518d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620239740 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din_no_pullu
p_pulldown.3620239740
Directory /workspace/16.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_random_long_reg_writes_reg_reads.110167990
Short name T651
Test name
Test status
Simulation time 3607082230 ps
CPU time 6.31 seconds
Started Jul 30 06:02:03 PM PDT 24
Finished Jul 30 06:02:10 PM PDT 24
Peak memory 198860 kb
Host smart-402fd7e0-d565-439a-81fa-48da6c79cef7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110167990 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_ran
dom_long_reg_writes_reg_reads.110167990
Directory /workspace/16.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/16.gpio_smoke.843246765
Short name T68
Test name
Test status
Simulation time 140623563 ps
CPU time 1.44 seconds
Started Jul 30 06:01:59 PM PDT 24
Finished Jul 30 06:02:00 PM PDT 24
Peak memory 197180 kb
Host smart-f682cc9b-93df-47d2-a921-4a64c4ca9126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843246765 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke.843246765
Directory /workspace/16.gpio_smoke/latest

Test location /workspace/coverage/default/16.gpio_smoke_no_pullup_pulldown.2883736763
Short name T642
Test name
Test status
Simulation time 28449880 ps
CPU time 0.9 seconds
Started Jul 30 06:02:03 PM PDT 24
Finished Jul 30 06:02:04 PM PDT 24
Peak memory 197076 kb
Host smart-56b8b122-4e76-44a7-9bda-aa556c075872
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883736763 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown.2883736763
Directory /workspace/16.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_stress_all.1479631843
Short name T475
Test name
Test status
Simulation time 47635739788 ps
CPU time 26.17 seconds
Started Jul 30 06:02:00 PM PDT 24
Finished Jul 30 06:02:27 PM PDT 24
Peak memory 198776 kb
Host smart-b1e96da3-fe98-4c92-9b28-e41db0afbeb8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479631843 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.
gpio_stress_all.1479631843
Directory /workspace/16.gpio_stress_all/latest

Test location /workspace/coverage/default/16.gpio_stress_all_with_rand_reset.3947561146
Short name T440
Test name
Test status
Simulation time 284120245492 ps
CPU time 1361.22 seconds
Started Jul 30 06:01:58 PM PDT 24
Finished Jul 30 06:24:39 PM PDT 24
Peak memory 198860 kb
Host smart-b416304b-aec5-44e7-b71d-593fa321a1ce
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3947561146 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_stress_all_with_rand_reset.3947561146
Directory /workspace/16.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.gpio_alert_test.2356934810
Short name T156
Test name
Test status
Simulation time 13344260 ps
CPU time 0.58 seconds
Started Jul 30 06:02:04 PM PDT 24
Finished Jul 30 06:02:04 PM PDT 24
Peak memory 194712 kb
Host smart-6f23e7ef-8aff-4931-be98-4c18b125da11
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356934810 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_alert_test.2356934810
Directory /workspace/17.gpio_alert_test/latest

Test location /workspace/coverage/default/17.gpio_dout_din_regs_random_rw.1879078282
Short name T468
Test name
Test status
Simulation time 47114412 ps
CPU time 0.74 seconds
Started Jul 30 06:02:01 PM PDT 24
Finished Jul 30 06:02:02 PM PDT 24
Peak memory 194592 kb
Host smart-b8b7bd72-1a7a-4313-842b-99532899f790
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1879078282 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_dout_din_regs_random_rw.1879078282
Directory /workspace/17.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/17.gpio_filter_stress.3913433189
Short name T198
Test name
Test status
Simulation time 724796142 ps
CPU time 7.4 seconds
Started Jul 30 06:02:03 PM PDT 24
Finished Jul 30 06:02:10 PM PDT 24
Peak memory 197440 kb
Host smart-aad9ed83-7d86-4db5-8a33-19615866ff6c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913433189 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_filter_stre
ss.3913433189
Directory /workspace/17.gpio_filter_stress/latest

Test location /workspace/coverage/default/17.gpio_full_random.896815868
Short name T230
Test name
Test status
Simulation time 41205912 ps
CPU time 0.7 seconds
Started Jul 30 06:02:01 PM PDT 24
Finished Jul 30 06:02:02 PM PDT 24
Peak memory 195200 kb
Host smart-8d1dd59c-ab60-4747-9e93-8ff0479a7189
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896815868 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_full_random.896815868
Directory /workspace/17.gpio_full_random/latest

Test location /workspace/coverage/default/17.gpio_intr_rand_pgm.2901811927
Short name T299
Test name
Test status
Simulation time 55582262 ps
CPU time 1.3 seconds
Started Jul 30 06:01:54 PM PDT 24
Finished Jul 30 06:01:56 PM PDT 24
Peak memory 197680 kb
Host smart-a2cfd2b4-fb8c-43b8-b883-ec2e84b825ff
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901811927 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_intr_rand_pgm.2901811927
Directory /workspace/17.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/17.gpio_intr_with_filter_rand_intr_event.464985909
Short name T678
Test name
Test status
Simulation time 201921827 ps
CPU time 2.2 seconds
Started Jul 30 06:02:02 PM PDT 24
Finished Jul 30 06:02:04 PM PDT 24
Peak memory 198660 kb
Host smart-e93bcd6e-575d-47c7-8aab-6d54854595b9
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464985909 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 17.gpio_intr_with_filter_rand_intr_event.464985909
Directory /workspace/17.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/17.gpio_rand_intr_trigger.3656784227
Short name T343
Test name
Test status
Simulation time 77392906 ps
CPU time 2.42 seconds
Started Jul 30 06:02:01 PM PDT 24
Finished Jul 30 06:02:04 PM PDT 24
Peak memory 197740 kb
Host smart-6d22f3a1-2656-42e6-b249-90b68db1437b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656784227 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_rand_intr_trigger
.3656784227
Directory /workspace/17.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din.563588786
Short name T213
Test name
Test status
Simulation time 65149309 ps
CPU time 0.77 seconds
Started Jul 30 06:02:00 PM PDT 24
Finished Jul 30 06:02:02 PM PDT 24
Peak memory 195980 kb
Host smart-7f9ec018-b62d-4d69-a138-f8c83a3a3844
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=563588786 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din.563588786
Directory /workspace/17.gpio_random_dout_din/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din_no_pullup_pulldown.2708839879
Short name T635
Test name
Test status
Simulation time 151111670 ps
CPU time 0.89 seconds
Started Jul 30 06:02:03 PM PDT 24
Finished Jul 30 06:02:04 PM PDT 24
Peak memory 196568 kb
Host smart-a7bcbbd4-a46c-409d-b3f6-ed9a57e4cd3f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708839879 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din_no_pullu
p_pulldown.2708839879
Directory /workspace/17.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_random_long_reg_writes_reg_reads.2355901464
Short name T575
Test name
Test status
Simulation time 679272438 ps
CPU time 5.76 seconds
Started Jul 30 06:02:04 PM PDT 24
Finished Jul 30 06:02:09 PM PDT 24
Peak memory 198604 kb
Host smart-83998b96-2727-4e65-bb20-d9190e8ed472
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355901464 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_ra
ndom_long_reg_writes_reg_reads.2355901464
Directory /workspace/17.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/17.gpio_smoke.3835335420
Short name T549
Test name
Test status
Simulation time 66384539 ps
CPU time 0.79 seconds
Started Jul 30 06:02:00 PM PDT 24
Finished Jul 30 06:02:01 PM PDT 24
Peak memory 195748 kb
Host smart-df7892c3-dd2e-409d-9839-846269cfca7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3835335420 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke.3835335420
Directory /workspace/17.gpio_smoke/latest

Test location /workspace/coverage/default/17.gpio_smoke_no_pullup_pulldown.4174493302
Short name T447
Test name
Test status
Simulation time 92246105 ps
CPU time 1.42 seconds
Started Jul 30 06:02:00 PM PDT 24
Finished Jul 30 06:02:02 PM PDT 24
Peak memory 197440 kb
Host smart-ee1e9771-d58e-4626-b51b-47fbbcfdf035
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174493302 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown.4174493302
Directory /workspace/17.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_stress_all.1105141232
Short name T408
Test name
Test status
Simulation time 8965523929 ps
CPU time 119.69 seconds
Started Jul 30 06:02:08 PM PDT 24
Finished Jul 30 06:04:08 PM PDT 24
Peak memory 198816 kb
Host smart-8958a9b4-8b31-45f4-8f84-f96a97766f62
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105141232 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.
gpio_stress_all.1105141232
Directory /workspace/17.gpio_stress_all/latest

Test location /workspace/coverage/default/18.gpio_alert_test.882649211
Short name T367
Test name
Test status
Simulation time 12356660 ps
CPU time 0.58 seconds
Started Jul 30 06:02:03 PM PDT 24
Finished Jul 30 06:02:03 PM PDT 24
Peak memory 194492 kb
Host smart-c16ba408-c006-4528-9a09-bf7819fc2558
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882649211 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_alert_test.882649211
Directory /workspace/18.gpio_alert_test/latest

Test location /workspace/coverage/default/18.gpio_dout_din_regs_random_rw.3937245957
Short name T524
Test name
Test status
Simulation time 76957499 ps
CPU time 0.69 seconds
Started Jul 30 06:02:05 PM PDT 24
Finished Jul 30 06:02:06 PM PDT 24
Peak memory 195424 kb
Host smart-752474a8-32d2-4ec1-b79d-35f7515b4b4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937245957 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_dout_din_regs_random_rw.3937245957
Directory /workspace/18.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/18.gpio_filter_stress.1292996517
Short name T209
Test name
Test status
Simulation time 236299101 ps
CPU time 11.96 seconds
Started Jul 30 06:01:56 PM PDT 24
Finished Jul 30 06:02:08 PM PDT 24
Peak memory 197556 kb
Host smart-2323fef6-dee6-4c3f-a035-7d0ea6c0d64e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292996517 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_filter_stre
ss.1292996517
Directory /workspace/18.gpio_filter_stress/latest

Test location /workspace/coverage/default/18.gpio_full_random.2290888631
Short name T558
Test name
Test status
Simulation time 53113247 ps
CPU time 0.86 seconds
Started Jul 30 06:02:01 PM PDT 24
Finished Jul 30 06:02:02 PM PDT 24
Peak memory 197204 kb
Host smart-dc45b6f5-892b-4b3a-b38f-e3bc8dcb49c1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290888631 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_full_random.2290888631
Directory /workspace/18.gpio_full_random/latest

Test location /workspace/coverage/default/18.gpio_intr_rand_pgm.1990161242
Short name T407
Test name
Test status
Simulation time 75149447 ps
CPU time 0.75 seconds
Started Jul 30 06:02:05 PM PDT 24
Finished Jul 30 06:02:06 PM PDT 24
Peak memory 196048 kb
Host smart-1f031a61-650a-47fc-b751-d03cd7b89393
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990161242 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_intr_rand_pgm.1990161242
Directory /workspace/18.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/18.gpio_intr_with_filter_rand_intr_event.2699581018
Short name T598
Test name
Test status
Simulation time 70975037 ps
CPU time 2.75 seconds
Started Jul 30 06:02:01 PM PDT 24
Finished Jul 30 06:02:04 PM PDT 24
Peak memory 198716 kb
Host smart-564da7cb-8111-4e71-8ff8-d50551ffddfb
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699581018 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 18.gpio_intr_with_filter_rand_intr_event.2699581018
Directory /workspace/18.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/18.gpio_rand_intr_trigger.3516619036
Short name T334
Test name
Test status
Simulation time 580820030 ps
CPU time 2.91 seconds
Started Jul 30 06:01:59 PM PDT 24
Finished Jul 30 06:02:02 PM PDT 24
Peak memory 197928 kb
Host smart-0debd7bb-4104-4117-b647-92f4acf9fa4e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516619036 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_rand_intr_trigger
.3516619036
Directory /workspace/18.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din.3066359210
Short name T368
Test name
Test status
Simulation time 15599539 ps
CPU time 0.65 seconds
Started Jul 30 06:02:02 PM PDT 24
Finished Jul 30 06:02:03 PM PDT 24
Peak memory 194736 kb
Host smart-c4ddd9ea-9bb8-4ebd-9a86-3e503d66f8f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066359210 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din.3066359210
Directory /workspace/18.gpio_random_dout_din/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din_no_pullup_pulldown.354987461
Short name T350
Test name
Test status
Simulation time 554921886 ps
CPU time 0.9 seconds
Started Jul 30 06:01:58 PM PDT 24
Finished Jul 30 06:01:59 PM PDT 24
Peak memory 196404 kb
Host smart-ed8ede86-4f93-4439-9a68-ae4d542d7536
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354987461 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din_no_pullup
_pulldown.354987461
Directory /workspace/18.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_random_long_reg_writes_reg_reads.3810717132
Short name T296
Test name
Test status
Simulation time 350240621 ps
CPU time 6.1 seconds
Started Jul 30 06:02:00 PM PDT 24
Finished Jul 30 06:02:07 PM PDT 24
Peak memory 198656 kb
Host smart-a63fc003-b782-4b0c-8217-4e43a8f8b9c8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810717132 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_ra
ndom_long_reg_writes_reg_reads.3810717132
Directory /workspace/18.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/18.gpio_smoke.2109556178
Short name T142
Test name
Test status
Simulation time 126801697 ps
CPU time 1.26 seconds
Started Jul 30 06:01:59 PM PDT 24
Finished Jul 30 06:02:00 PM PDT 24
Peak memory 196808 kb
Host smart-0d62c144-9b16-4b97-9050-ac8e3c7ee26c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2109556178 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke.2109556178
Directory /workspace/18.gpio_smoke/latest

Test location /workspace/coverage/default/18.gpio_smoke_no_pullup_pulldown.2149871222
Short name T176
Test name
Test status
Simulation time 83469007 ps
CPU time 0.84 seconds
Started Jul 30 06:02:08 PM PDT 24
Finished Jul 30 06:02:09 PM PDT 24
Peak memory 196544 kb
Host smart-221d4190-62aa-4148-b1f8-62e748254bd3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149871222 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown.2149871222
Directory /workspace/18.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_stress_all.3539202518
Short name T576
Test name
Test status
Simulation time 21249949972 ps
CPU time 76.25 seconds
Started Jul 30 06:02:00 PM PDT 24
Finished Jul 30 06:03:17 PM PDT 24
Peak memory 198720 kb
Host smart-39c8cff3-7a22-4e95-a287-46f6a1ac030d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539202518 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.
gpio_stress_all.3539202518
Directory /workspace/18.gpio_stress_all/latest

Test location /workspace/coverage/default/19.gpio_alert_test.4222080238
Short name T268
Test name
Test status
Simulation time 136718085 ps
CPU time 0.57 seconds
Started Jul 30 06:02:11 PM PDT 24
Finished Jul 30 06:02:11 PM PDT 24
Peak memory 195196 kb
Host smart-01ae914f-d6bd-4aef-a1aa-86546b98c116
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222080238 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_alert_test.4222080238
Directory /workspace/19.gpio_alert_test/latest

Test location /workspace/coverage/default/19.gpio_dout_din_regs_random_rw.3318790405
Short name T217
Test name
Test status
Simulation time 26033376 ps
CPU time 0.9 seconds
Started Jul 30 06:02:09 PM PDT 24
Finished Jul 30 06:02:10 PM PDT 24
Peak memory 196032 kb
Host smart-cb563b8e-f1bd-4b44-a46d-e77f77d119dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3318790405 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_dout_din_regs_random_rw.3318790405
Directory /workspace/19.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/19.gpio_filter_stress.2777300922
Short name T326
Test name
Test status
Simulation time 772656964 ps
CPU time 22.58 seconds
Started Jul 30 06:02:21 PM PDT 24
Finished Jul 30 06:02:44 PM PDT 24
Peak memory 197844 kb
Host smart-d8fdb309-eb8f-44d7-a406-b7c9c7130201
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777300922 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_filter_stre
ss.2777300922
Directory /workspace/19.gpio_filter_stress/latest

Test location /workspace/coverage/default/19.gpio_full_random.2366642286
Short name T401
Test name
Test status
Simulation time 60856168 ps
CPU time 0.86 seconds
Started Jul 30 06:02:10 PM PDT 24
Finished Jul 30 06:02:11 PM PDT 24
Peak memory 196568 kb
Host smart-cb295d5a-1240-4d34-a455-95f53b01da4f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366642286 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_full_random.2366642286
Directory /workspace/19.gpio_full_random/latest

Test location /workspace/coverage/default/19.gpio_intr_rand_pgm.882368561
Short name T594
Test name
Test status
Simulation time 106035926 ps
CPU time 0.75 seconds
Started Jul 30 06:02:06 PM PDT 24
Finished Jul 30 06:02:06 PM PDT 24
Peak memory 196548 kb
Host smart-55f0b31d-3dc2-4d77-b2c0-c0cc051f8355
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882368561 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_intr_rand_pgm.882368561
Directory /workspace/19.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/19.gpio_intr_with_filter_rand_intr_event.321304560
Short name T436
Test name
Test status
Simulation time 589647219 ps
CPU time 2.2 seconds
Started Jul 30 06:02:10 PM PDT 24
Finished Jul 30 06:02:12 PM PDT 24
Peak memory 198616 kb
Host smart-2b9e02cc-3583-4bee-bc78-60a8235eea2e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321304560 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 19.gpio_intr_with_filter_rand_intr_event.321304560
Directory /workspace/19.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/19.gpio_rand_intr_trigger.3284822895
Short name T567
Test name
Test status
Simulation time 198805286 ps
CPU time 2.16 seconds
Started Jul 30 06:02:29 PM PDT 24
Finished Jul 30 06:02:31 PM PDT 24
Peak memory 197708 kb
Host smart-36fc707a-c4c5-4f09-bb05-46cd2d7823c5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284822895 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_rand_intr_trigger
.3284822895
Directory /workspace/19.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din.2065108477
Short name T56
Test name
Test status
Simulation time 148325606 ps
CPU time 1.23 seconds
Started Jul 30 06:02:06 PM PDT 24
Finished Jul 30 06:02:07 PM PDT 24
Peak memory 197484 kb
Host smart-bddfb310-d8d0-4772-96da-8b80f469356f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065108477 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din.2065108477
Directory /workspace/19.gpio_random_dout_din/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din_no_pullup_pulldown.464521833
Short name T542
Test name
Test status
Simulation time 22479090 ps
CPU time 0.87 seconds
Started Jul 30 06:02:07 PM PDT 24
Finished Jul 30 06:02:08 PM PDT 24
Peak memory 197216 kb
Host smart-b63545be-7308-4fc1-8726-1b2f955ff8ab
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464521833 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din_no_pullup
_pulldown.464521833
Directory /workspace/19.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_random_long_reg_writes_reg_reads.971193892
Short name T378
Test name
Test status
Simulation time 1542389746 ps
CPU time 5.88 seconds
Started Jul 30 06:02:09 PM PDT 24
Finished Jul 30 06:02:14 PM PDT 24
Peak memory 198636 kb
Host smart-0aac9af6-d006-4284-86b8-d225eea4a1c7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971193892 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_ran
dom_long_reg_writes_reg_reads.971193892
Directory /workspace/19.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/19.gpio_smoke.884727805
Short name T304
Test name
Test status
Simulation time 141712026 ps
CPU time 1.2 seconds
Started Jul 30 06:02:01 PM PDT 24
Finished Jul 30 06:02:03 PM PDT 24
Peak memory 196428 kb
Host smart-2890ee20-adff-4c42-bd3e-9e2e75dd6d0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=884727805 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke.884727805
Directory /workspace/19.gpio_smoke/latest

Test location /workspace/coverage/default/19.gpio_smoke_no_pullup_pulldown.3229839026
Short name T178
Test name
Test status
Simulation time 125659445 ps
CPU time 1.02 seconds
Started Jul 30 06:02:02 PM PDT 24
Finished Jul 30 06:02:03 PM PDT 24
Peak memory 196132 kb
Host smart-513fb144-51e6-4200-b9a6-34d7f78afae6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229839026 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown.3229839026
Directory /workspace/19.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_stress_all.1526700968
Short name T126
Test name
Test status
Simulation time 1960680875 ps
CPU time 39.33 seconds
Started Jul 30 06:02:26 PM PDT 24
Finished Jul 30 06:03:05 PM PDT 24
Peak memory 198628 kb
Host smart-88711a4e-3797-4e92-9c8e-b2e091b942dd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526700968 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.
gpio_stress_all.1526700968
Directory /workspace/19.gpio_stress_all/latest

Test location /workspace/coverage/default/19.gpio_stress_all_with_rand_reset.3280336848
Short name T551
Test name
Test status
Simulation time 194678353406 ps
CPU time 1175.24 seconds
Started Jul 30 06:02:27 PM PDT 24
Finished Jul 30 06:22:03 PM PDT 24
Peak memory 198848 kb
Host smart-7ed3a24c-a8b6-4ce5-8e63-28a710a101b3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3280336848 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_stress_all_with_rand_reset.3280336848
Directory /workspace/19.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.gpio_alert_test.2571459067
Short name T396
Test name
Test status
Simulation time 25067454 ps
CPU time 0.59 seconds
Started Jul 30 06:01:43 PM PDT 24
Finished Jul 30 06:01:44 PM PDT 24
Peak memory 195240 kb
Host smart-7b3e9d24-73e3-43df-a44d-951c4ad8e138
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571459067 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_alert_test.2571459067
Directory /workspace/2.gpio_alert_test/latest

Test location /workspace/coverage/default/2.gpio_dout_din_regs_random_rw.2205605676
Short name T535
Test name
Test status
Simulation time 25508077 ps
CPU time 0.77 seconds
Started Jul 30 06:01:46 PM PDT 24
Finished Jul 30 06:01:47 PM PDT 24
Peak memory 195804 kb
Host smart-eadfc1cc-b4d6-4517-a727-dcbc806b1e8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2205605676 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_dout_din_regs_random_rw.2205605676
Directory /workspace/2.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/2.gpio_filter_stress.3097905818
Short name T121
Test name
Test status
Simulation time 1030879086 ps
CPU time 16.69 seconds
Started Jul 30 06:02:03 PM PDT 24
Finished Jul 30 06:02:20 PM PDT 24
Peak memory 197464 kb
Host smart-88d634bd-49bc-4bc4-bd25-d29d303a5178
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097905818 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_filter_stres
s.3097905818
Directory /workspace/2.gpio_filter_stress/latest

Test location /workspace/coverage/default/2.gpio_full_random.1429814911
Short name T22
Test name
Test status
Simulation time 83819274 ps
CPU time 1 seconds
Started Jul 30 06:01:57 PM PDT 24
Finished Jul 30 06:01:58 PM PDT 24
Peak memory 197084 kb
Host smart-83656f8e-f97b-4e1b-bb39-aeb45b37340d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429814911 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_full_random.1429814911
Directory /workspace/2.gpio_full_random/latest

Test location /workspace/coverage/default/2.gpio_intr_rand_pgm.3759764084
Short name T449
Test name
Test status
Simulation time 174157350 ps
CPU time 0.91 seconds
Started Jul 30 06:01:50 PM PDT 24
Finished Jul 30 06:01:51 PM PDT 24
Peak memory 197452 kb
Host smart-09647b07-f9b6-4f64-8641-a0e6e79ff0a1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759764084 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_intr_rand_pgm.3759764084
Directory /workspace/2.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/2.gpio_intr_with_filter_rand_intr_event.1037944882
Short name T285
Test name
Test status
Simulation time 206292095 ps
CPU time 0.99 seconds
Started Jul 30 06:01:46 PM PDT 24
Finished Jul 30 06:01:47 PM PDT 24
Peak memory 196664 kb
Host smart-60e6fdaa-df55-489b-a2ca-823a0425cf35
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037944882 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.gpio_intr_with_filter_rand_intr_event.1037944882
Directory /workspace/2.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/2.gpio_rand_intr_trigger.888344345
Short name T226
Test name
Test status
Simulation time 42019814 ps
CPU time 1.38 seconds
Started Jul 30 06:01:49 PM PDT 24
Finished Jul 30 06:01:50 PM PDT 24
Peak memory 196484 kb
Host smart-55fa5987-f42e-4ba2-ac3c-c5b6deb35ac8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888344345 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_rand_intr_trigger.888344345
Directory /workspace/2.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din.2027152976
Short name T174
Test name
Test status
Simulation time 121230714 ps
CPU time 0.99 seconds
Started Jul 30 06:01:50 PM PDT 24
Finished Jul 30 06:01:51 PM PDT 24
Peak memory 196592 kb
Host smart-37747e41-30f5-488c-a229-39ae4b0624ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2027152976 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din.2027152976
Directory /workspace/2.gpio_random_dout_din/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din_no_pullup_pulldown.3379006860
Short name T444
Test name
Test status
Simulation time 200925763 ps
CPU time 0.88 seconds
Started Jul 30 06:01:44 PM PDT 24
Finished Jul 30 06:01:45 PM PDT 24
Peak memory 197108 kb
Host smart-c7cc9d68-a945-4fc5-9964-505ec96fe82c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379006860 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din_no_pullup
_pulldown.3379006860
Directory /workspace/2.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_random_long_reg_writes_reg_reads.1787275486
Short name T370
Test name
Test status
Simulation time 263602391 ps
CPU time 4.25 seconds
Started Jul 30 06:01:49 PM PDT 24
Finished Jul 30 06:01:53 PM PDT 24
Peak memory 198608 kb
Host smart-e6dbbb54-ee28-4aba-a10f-182e0d6b2715
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787275486 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_ran
dom_long_reg_writes_reg_reads.1787275486
Directory /workspace/2.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/2.gpio_sec_cm.776452535
Short name T50
Test name
Test status
Simulation time 62874993 ps
CPU time 0.89 seconds
Started Jul 30 06:01:52 PM PDT 24
Finished Jul 30 06:01:53 PM PDT 24
Peak memory 214380 kb
Host smart-479932f0-5ed8-4acb-96be-36e6d7965019
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776452535 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_sec_cm.776452535
Directory /workspace/2.gpio_sec_cm/latest

Test location /workspace/coverage/default/2.gpio_smoke.3022322733
Short name T685
Test name
Test status
Simulation time 245442652 ps
CPU time 1.12 seconds
Started Jul 30 06:01:57 PM PDT 24
Finished Jul 30 06:01:58 PM PDT 24
Peak memory 196240 kb
Host smart-7dbfa05b-d66b-4fb5-a286-44e24829f3c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3022322733 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke.3022322733
Directory /workspace/2.gpio_smoke/latest

Test location /workspace/coverage/default/2.gpio_smoke_no_pullup_pulldown.1162438413
Short name T207
Test name
Test status
Simulation time 45535409 ps
CPU time 1.01 seconds
Started Jul 30 06:01:53 PM PDT 24
Finished Jul 30 06:01:54 PM PDT 24
Peak memory 196084 kb
Host smart-52b5ad99-8860-4b4f-a693-5b97c4c1789b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162438413 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown.1162438413
Directory /workspace/2.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_stress_all.3014222981
Short name T495
Test name
Test status
Simulation time 67111348554 ps
CPU time 102.2 seconds
Started Jul 30 06:01:51 PM PDT 24
Finished Jul 30 06:03:33 PM PDT 24
Peak memory 198644 kb
Host smart-d82b16c3-4658-45ab-b3cc-d4bf7cda305b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014222981 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.g
pio_stress_all.3014222981
Directory /workspace/2.gpio_stress_all/latest

Test location /workspace/coverage/default/2.gpio_stress_all_with_rand_reset.1580244177
Short name T457
Test name
Test status
Simulation time 770808937316 ps
CPU time 1535.4 seconds
Started Jul 30 06:01:53 PM PDT 24
Finished Jul 30 06:27:29 PM PDT 24
Peak memory 207016 kb
Host smart-2adeece9-90e7-44b2-8421-bb281351a7e3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1580244177 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_stress_all_with_rand_reset.1580244177
Directory /workspace/2.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.gpio_alert_test.4080997708
Short name T38
Test name
Test status
Simulation time 23806931 ps
CPU time 0.61 seconds
Started Jul 30 06:02:28 PM PDT 24
Finished Jul 30 06:02:29 PM PDT 24
Peak memory 194492 kb
Host smart-e3f9a2f7-c980-4331-b6b7-a9f1ff952683
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080997708 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_alert_test.4080997708
Directory /workspace/20.gpio_alert_test/latest

Test location /workspace/coverage/default/20.gpio_dout_din_regs_random_rw.2924843416
Short name T53
Test name
Test status
Simulation time 40054270 ps
CPU time 0.84 seconds
Started Jul 30 06:02:18 PM PDT 24
Finished Jul 30 06:02:19 PM PDT 24
Peak memory 197556 kb
Host smart-89b69864-f7d2-4b4b-bfa3-2b91a73ae196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2924843416 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_dout_din_regs_random_rw.2924843416
Directory /workspace/20.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/20.gpio_filter_stress.1706321619
Short name T262
Test name
Test status
Simulation time 5065748034 ps
CPU time 24.76 seconds
Started Jul 30 06:02:12 PM PDT 24
Finished Jul 30 06:02:37 PM PDT 24
Peak memory 197664 kb
Host smart-e7061bbc-52bb-4cf4-9c61-10a39b9b726f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706321619 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_filter_stre
ss.1706321619
Directory /workspace/20.gpio_filter_stress/latest

Test location /workspace/coverage/default/20.gpio_full_random.2193837748
Short name T694
Test name
Test status
Simulation time 130264746 ps
CPU time 1.03 seconds
Started Jul 30 06:02:35 PM PDT 24
Finished Jul 30 06:02:36 PM PDT 24
Peak memory 196932 kb
Host smart-e681e195-f023-44b9-ad8b-df1ef192996a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193837748 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_full_random.2193837748
Directory /workspace/20.gpio_full_random/latest

Test location /workspace/coverage/default/20.gpio_intr_rand_pgm.1494542247
Short name T276
Test name
Test status
Simulation time 43142164 ps
CPU time 1.1 seconds
Started Jul 30 06:02:09 PM PDT 24
Finished Jul 30 06:02:11 PM PDT 24
Peak memory 196288 kb
Host smart-9901dd15-491f-439c-935a-40857f6c4393
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494542247 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_intr_rand_pgm.1494542247
Directory /workspace/20.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/20.gpio_intr_with_filter_rand_intr_event.1784657138
Short name T48
Test name
Test status
Simulation time 139604429 ps
CPU time 2.92 seconds
Started Jul 30 06:02:13 PM PDT 24
Finished Jul 30 06:02:16 PM PDT 24
Peak memory 198576 kb
Host smart-2cb6748c-3afe-4201-ae35-431ce5084baf
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784657138 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 20.gpio_intr_with_filter_rand_intr_event.1784657138
Directory /workspace/20.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/20.gpio_rand_intr_trigger.588534891
Short name T682
Test name
Test status
Simulation time 152379783 ps
CPU time 1.44 seconds
Started Jul 30 06:02:12 PM PDT 24
Finished Jul 30 06:02:14 PM PDT 24
Peak memory 196764 kb
Host smart-b95da259-e233-48c2-aea4-ed9c0e6566da
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588534891 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_rand_intr_trigger.
588534891
Directory /workspace/20.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din.850706076
Short name T637
Test name
Test status
Simulation time 130748044 ps
CPU time 1.18 seconds
Started Jul 30 06:02:18 PM PDT 24
Finished Jul 30 06:02:20 PM PDT 24
Peak memory 198588 kb
Host smart-2f0445f2-06a1-407b-8173-c9b28151c823
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=850706076 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din.850706076
Directory /workspace/20.gpio_random_dout_din/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din_no_pullup_pulldown.2572123055
Short name T695
Test name
Test status
Simulation time 72871170 ps
CPU time 0.72 seconds
Started Jul 30 06:02:26 PM PDT 24
Finished Jul 30 06:02:27 PM PDT 24
Peak memory 196620 kb
Host smart-44d0798f-0154-4234-a9c7-9e01b758fac8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572123055 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din_no_pullu
p_pulldown.2572123055
Directory /workspace/20.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_random_long_reg_writes_reg_reads.2399454548
Short name T292
Test name
Test status
Simulation time 399163954 ps
CPU time 2.68 seconds
Started Jul 30 06:02:21 PM PDT 24
Finished Jul 30 06:02:23 PM PDT 24
Peak memory 198540 kb
Host smart-d6ebc726-1812-430d-9b6b-d87e55b048f1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399454548 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_ra
ndom_long_reg_writes_reg_reads.2399454548
Directory /workspace/20.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/20.gpio_smoke.3617107675
Short name T661
Test name
Test status
Simulation time 138831670 ps
CPU time 1.18 seconds
Started Jul 30 06:02:19 PM PDT 24
Finished Jul 30 06:02:20 PM PDT 24
Peak memory 196312 kb
Host smart-d736efb3-7a9e-4125-9cca-1be567f14912
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3617107675 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke.3617107675
Directory /workspace/20.gpio_smoke/latest

Test location /workspace/coverage/default/20.gpio_smoke_no_pullup_pulldown.3225463101
Short name T14
Test name
Test status
Simulation time 286885177 ps
CPU time 1.36 seconds
Started Jul 30 06:02:17 PM PDT 24
Finished Jul 30 06:02:19 PM PDT 24
Peak memory 196140 kb
Host smart-28783114-44a5-47fa-a024-eabaaad2a7be
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225463101 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown.3225463101
Directory /workspace/20.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_stress_all.3021229088
Short name T612
Test name
Test status
Simulation time 36788516729 ps
CPU time 132.32 seconds
Started Jul 30 06:02:12 PM PDT 24
Finished Jul 30 06:04:24 PM PDT 24
Peak memory 198800 kb
Host smart-63320379-00c7-4dcd-bae9-8775c756bb9b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021229088 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.
gpio_stress_all.3021229088
Directory /workspace/20.gpio_stress_all/latest

Test location /workspace/coverage/default/21.gpio_alert_test.2076096877
Short name T429
Test name
Test status
Simulation time 38195448 ps
CPU time 0.58 seconds
Started Jul 30 06:02:36 PM PDT 24
Finished Jul 30 06:02:37 PM PDT 24
Peak memory 195212 kb
Host smart-ee22fea2-6c11-4172-bf29-208fb480ac62
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076096877 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_alert_test.2076096877
Directory /workspace/21.gpio_alert_test/latest

Test location /workspace/coverage/default/21.gpio_dout_din_regs_random_rw.3553700189
Short name T211
Test name
Test status
Simulation time 51859628 ps
CPU time 0.87 seconds
Started Jul 30 06:02:15 PM PDT 24
Finished Jul 30 06:02:16 PM PDT 24
Peak memory 197768 kb
Host smart-255b94f8-e68a-483a-bceb-5036474c3b73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553700189 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_dout_din_regs_random_rw.3553700189
Directory /workspace/21.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/21.gpio_filter_stress.2167385599
Short name T182
Test name
Test status
Simulation time 1316852444 ps
CPU time 22.1 seconds
Started Jul 30 06:02:34 PM PDT 24
Finished Jul 30 06:02:57 PM PDT 24
Peak memory 197444 kb
Host smart-8622e5a2-cc35-44ee-ac98-371c000a65cb
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167385599 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_filter_stre
ss.2167385599
Directory /workspace/21.gpio_filter_stress/latest

Test location /workspace/coverage/default/21.gpio_full_random.2440772001
Short name T413
Test name
Test status
Simulation time 164970134 ps
CPU time 0.98 seconds
Started Jul 30 06:02:29 PM PDT 24
Finished Jul 30 06:02:30 PM PDT 24
Peak memory 197240 kb
Host smart-42be325d-a19b-4ab5-a835-0718a019a827
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440772001 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_full_random.2440772001
Directory /workspace/21.gpio_full_random/latest

Test location /workspace/coverage/default/21.gpio_intr_rand_pgm.1768508040
Short name T554
Test name
Test status
Simulation time 1039726043 ps
CPU time 1.36 seconds
Started Jul 30 06:02:13 PM PDT 24
Finished Jul 30 06:02:15 PM PDT 24
Peak memory 196472 kb
Host smart-517a8c51-df27-48f8-aee3-1e9d5d66460d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768508040 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_intr_rand_pgm.1768508040
Directory /workspace/21.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/21.gpio_intr_with_filter_rand_intr_event.1858180555
Short name T365
Test name
Test status
Simulation time 311396379 ps
CPU time 2.86 seconds
Started Jul 30 06:02:23 PM PDT 24
Finished Jul 30 06:02:26 PM PDT 24
Peak memory 197064 kb
Host smart-9a5a77b3-af65-4348-b2de-cfdcbf741061
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858180555 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 21.gpio_intr_with_filter_rand_intr_event.1858180555
Directory /workspace/21.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/21.gpio_rand_intr_trigger.1155681293
Short name T186
Test name
Test status
Simulation time 251299575 ps
CPU time 3.02 seconds
Started Jul 30 06:02:21 PM PDT 24
Finished Jul 30 06:02:25 PM PDT 24
Peak memory 197572 kb
Host smart-aeb2145d-0554-40b1-9eaf-a65b6e1b710f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155681293 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_rand_intr_trigger
.1155681293
Directory /workspace/21.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din.3641964838
Short name T248
Test name
Test status
Simulation time 70523870 ps
CPU time 1.04 seconds
Started Jul 30 06:02:31 PM PDT 24
Finished Jul 30 06:02:32 PM PDT 24
Peak memory 196428 kb
Host smart-0848fd9f-73c5-4a42-b398-dd0d470f4035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3641964838 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din.3641964838
Directory /workspace/21.gpio_random_dout_din/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din_no_pullup_pulldown.1793872388
Short name T363
Test name
Test status
Simulation time 35847800 ps
CPU time 0.85 seconds
Started Jul 30 06:02:21 PM PDT 24
Finished Jul 30 06:02:22 PM PDT 24
Peak memory 196432 kb
Host smart-dc5627e0-9f6c-4d2c-83a1-a75bb4c2a7ab
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793872388 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din_no_pullu
p_pulldown.1793872388
Directory /workspace/21.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_random_long_reg_writes_reg_reads.3186909155
Short name T148
Test name
Test status
Simulation time 122606042 ps
CPU time 5.89 seconds
Started Jul 30 06:02:25 PM PDT 24
Finished Jul 30 06:02:31 PM PDT 24
Peak memory 198520 kb
Host smart-bac3b2ab-2636-490b-9d39-c305ddd84ca9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186909155 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_ra
ndom_long_reg_writes_reg_reads.3186909155
Directory /workspace/21.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/21.gpio_smoke.3806002836
Short name T704
Test name
Test status
Simulation time 77329235 ps
CPU time 1.19 seconds
Started Jul 30 06:02:32 PM PDT 24
Finished Jul 30 06:02:34 PM PDT 24
Peak memory 196360 kb
Host smart-77cb8d42-4cae-4e93-9e20-6e4747b9db74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3806002836 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke.3806002836
Directory /workspace/21.gpio_smoke/latest

Test location /workspace/coverage/default/21.gpio_smoke_no_pullup_pulldown.3881060024
Short name T516
Test name
Test status
Simulation time 43331951 ps
CPU time 0.84 seconds
Started Jul 30 06:02:26 PM PDT 24
Finished Jul 30 06:02:27 PM PDT 24
Peak memory 195644 kb
Host smart-cffe444b-34b3-4d90-965a-a3610585b766
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881060024 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown.3881060024
Directory /workspace/21.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_stress_all.906175860
Short name T656
Test name
Test status
Simulation time 6575317749 ps
CPU time 170.3 seconds
Started Jul 30 06:02:35 PM PDT 24
Finished Jul 30 06:05:25 PM PDT 24
Peak memory 198796 kb
Host smart-90756aa1-3323-4075-9cc0-ad437ce7e47b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906175860 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.g
pio_stress_all.906175860
Directory /workspace/21.gpio_stress_all/latest

Test location /workspace/coverage/default/22.gpio_alert_test.204013601
Short name T39
Test name
Test status
Simulation time 24596712 ps
CPU time 0.56 seconds
Started Jul 30 06:02:27 PM PDT 24
Finished Jul 30 06:02:28 PM PDT 24
Peak memory 194488 kb
Host smart-409698d3-4c74-4cb5-9e07-4f5cc20ee52f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204013601 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_alert_test.204013601
Directory /workspace/22.gpio_alert_test/latest

Test location /workspace/coverage/default/22.gpio_dout_din_regs_random_rw.2928738093
Short name T137
Test name
Test status
Simulation time 31967153 ps
CPU time 0.9 seconds
Started Jul 30 06:02:36 PM PDT 24
Finished Jul 30 06:02:37 PM PDT 24
Peak memory 196988 kb
Host smart-91d057a5-4b7e-4fe8-8b6a-ec9f512b9483
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928738093 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_dout_din_regs_random_rw.2928738093
Directory /workspace/22.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/22.gpio_filter_stress.3640657921
Short name T617
Test name
Test status
Simulation time 138437417 ps
CPU time 6.84 seconds
Started Jul 30 06:02:36 PM PDT 24
Finished Jul 30 06:02:43 PM PDT 24
Peak memory 197384 kb
Host smart-4d520883-56e7-433b-ae3f-fae6ca43c998
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640657921 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_filter_stre
ss.3640657921
Directory /workspace/22.gpio_filter_stress/latest

Test location /workspace/coverage/default/22.gpio_full_random.311317595
Short name T701
Test name
Test status
Simulation time 112688339 ps
CPU time 0.72 seconds
Started Jul 30 06:02:42 PM PDT 24
Finished Jul 30 06:02:42 PM PDT 24
Peak memory 195300 kb
Host smart-ec4bf4e2-1d9e-4596-a4cf-01b49756c718
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311317595 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_full_random.311317595
Directory /workspace/22.gpio_full_random/latest

Test location /workspace/coverage/default/22.gpio_intr_rand_pgm.3107114643
Short name T439
Test name
Test status
Simulation time 204258249 ps
CPU time 1.02 seconds
Started Jul 30 06:02:25 PM PDT 24
Finished Jul 30 06:02:26 PM PDT 24
Peak memory 196652 kb
Host smart-e2b8cab3-fc7c-4546-b83b-a1927bc2db22
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107114643 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_intr_rand_pgm.3107114643
Directory /workspace/22.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/22.gpio_intr_with_filter_rand_intr_event.3907233444
Short name T543
Test name
Test status
Simulation time 71064843 ps
CPU time 3.1 seconds
Started Jul 30 06:02:40 PM PDT 24
Finished Jul 30 06:02:43 PM PDT 24
Peak memory 198604 kb
Host smart-a13c2f91-6758-496b-8a6a-a2b10fd2fefc
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907233444 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 22.gpio_intr_with_filter_rand_intr_event.3907233444
Directory /workspace/22.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/22.gpio_rand_intr_trigger.3387356241
Short name T548
Test name
Test status
Simulation time 27709453 ps
CPU time 1.1 seconds
Started Jul 30 06:02:39 PM PDT 24
Finished Jul 30 06:02:41 PM PDT 24
Peak memory 196888 kb
Host smart-124d144e-12fa-457a-91f3-391424c8532f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387356241 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_rand_intr_trigger
.3387356241
Directory /workspace/22.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din.2108021025
Short name T426
Test name
Test status
Simulation time 104118776 ps
CPU time 1.14 seconds
Started Jul 30 06:02:30 PM PDT 24
Finished Jul 30 06:02:32 PM PDT 24
Peak memory 197624 kb
Host smart-89257210-391d-499c-923b-08ab5fb9c16e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2108021025 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din.2108021025
Directory /workspace/22.gpio_random_dout_din/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din_no_pullup_pulldown.1140129740
Short name T180
Test name
Test status
Simulation time 27362703 ps
CPU time 0.75 seconds
Started Jul 30 06:02:34 PM PDT 24
Finished Jul 30 06:02:35 PM PDT 24
Peak memory 196652 kb
Host smart-8bed8478-790d-4e00-b648-3001f6e1e98f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140129740 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din_no_pullu
p_pulldown.1140129740
Directory /workspace/22.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_random_long_reg_writes_reg_reads.2691395100
Short name T308
Test name
Test status
Simulation time 66208855 ps
CPU time 1.21 seconds
Started Jul 30 06:02:40 PM PDT 24
Finished Jul 30 06:02:41 PM PDT 24
Peak memory 197064 kb
Host smart-bc6e4e33-60fe-40d0-bdb1-a0b1e2be2d01
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691395100 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_ra
ndom_long_reg_writes_reg_reads.2691395100
Directory /workspace/22.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/22.gpio_smoke.1426940200
Short name T324
Test name
Test status
Simulation time 638852191 ps
CPU time 1.39 seconds
Started Jul 30 06:02:26 PM PDT 24
Finished Jul 30 06:02:27 PM PDT 24
Peak memory 196092 kb
Host smart-f65c87b1-5faa-48e3-a31a-dbcf11a30e99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426940200 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke.1426940200
Directory /workspace/22.gpio_smoke/latest

Test location /workspace/coverage/default/22.gpio_smoke_no_pullup_pulldown.3405192816
Short name T339
Test name
Test status
Simulation time 111638264 ps
CPU time 1 seconds
Started Jul 30 06:02:25 PM PDT 24
Finished Jul 30 06:02:26 PM PDT 24
Peak memory 196268 kb
Host smart-cbb24c5d-3265-420e-abcf-e13733d1e04f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405192816 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown.3405192816
Directory /workspace/22.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_stress_all.1707065424
Short name T235
Test name
Test status
Simulation time 19366919668 ps
CPU time 144.47 seconds
Started Jul 30 06:02:37 PM PDT 24
Finished Jul 30 06:05:02 PM PDT 24
Peak memory 198700 kb
Host smart-e892812c-ca6d-4b8c-b6ba-1534b4cb624e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707065424 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.
gpio_stress_all.1707065424
Directory /workspace/22.gpio_stress_all/latest

Test location /workspace/coverage/default/23.gpio_alert_test.1259748106
Short name T66
Test name
Test status
Simulation time 13296869 ps
CPU time 0.57 seconds
Started Jul 30 06:02:25 PM PDT 24
Finished Jul 30 06:02:26 PM PDT 24
Peak memory 194636 kb
Host smart-b8321810-0776-4e2d-b6b4-1685b70fbace
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259748106 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_alert_test.1259748106
Directory /workspace/23.gpio_alert_test/latest

Test location /workspace/coverage/default/23.gpio_dout_din_regs_random_rw.3573428177
Short name T290
Test name
Test status
Simulation time 18961849 ps
CPU time 0.6 seconds
Started Jul 30 06:02:28 PM PDT 24
Finished Jul 30 06:02:29 PM PDT 24
Peak memory 194404 kb
Host smart-6ba2e53d-dd4c-4e91-9767-2d3c41212dc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3573428177 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_dout_din_regs_random_rw.3573428177
Directory /workspace/23.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/23.gpio_filter_stress.863231953
Short name T459
Test name
Test status
Simulation time 2070437458 ps
CPU time 29.48 seconds
Started Jul 30 06:02:49 PM PDT 24
Finished Jul 30 06:03:19 PM PDT 24
Peak memory 197336 kb
Host smart-e43c5511-a598-43f5-88ca-fc66c6a036c7
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863231953 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_filter_stres
s.863231953
Directory /workspace/23.gpio_filter_stress/latest

Test location /workspace/coverage/default/23.gpio_full_random.3925199621
Short name T153
Test name
Test status
Simulation time 201862468 ps
CPU time 0.85 seconds
Started Jul 30 06:02:33 PM PDT 24
Finished Jul 30 06:02:34 PM PDT 24
Peak memory 196620 kb
Host smart-b9f46739-f416-493b-a873-2bcfe6b69fec
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925199621 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_full_random.3925199621
Directory /workspace/23.gpio_full_random/latest

Test location /workspace/coverage/default/23.gpio_intr_rand_pgm.3828002619
Short name T133
Test name
Test status
Simulation time 30100964 ps
CPU time 0.74 seconds
Started Jul 30 06:02:22 PM PDT 24
Finished Jul 30 06:02:23 PM PDT 24
Peak memory 195904 kb
Host smart-7681918a-17df-46b8-bd10-55a26e54f6c1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828002619 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_intr_rand_pgm.3828002619
Directory /workspace/23.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/23.gpio_intr_with_filter_rand_intr_event.2625840872
Short name T118
Test name
Test status
Simulation time 50959257 ps
CPU time 2.03 seconds
Started Jul 30 06:02:27 PM PDT 24
Finished Jul 30 06:02:29 PM PDT 24
Peak memory 198736 kb
Host smart-a1272d2c-f2ae-4906-9341-5dd56fc857de
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625840872 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 23.gpio_intr_with_filter_rand_intr_event.2625840872
Directory /workspace/23.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/23.gpio_rand_intr_trigger.674038764
Short name T104
Test name
Test status
Simulation time 454864022 ps
CPU time 2.51 seconds
Started Jul 30 06:02:25 PM PDT 24
Finished Jul 30 06:02:28 PM PDT 24
Peak memory 196456 kb
Host smart-58c747ed-9247-4c81-b2a9-6efaa6253d11
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674038764 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_rand_intr_trigger.
674038764
Directory /workspace/23.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din.1356895405
Short name T70
Test name
Test status
Simulation time 46281032 ps
CPU time 1.01 seconds
Started Jul 30 06:02:29 PM PDT 24
Finished Jul 30 06:02:30 PM PDT 24
Peak memory 196388 kb
Host smart-2482a37a-f90a-4d68-aa57-92656cd99f06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1356895405 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din.1356895405
Directory /workspace/23.gpio_random_dout_din/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din_no_pullup_pulldown.266328932
Short name T238
Test name
Test status
Simulation time 74243650 ps
CPU time 1.26 seconds
Started Jul 30 06:02:28 PM PDT 24
Finished Jul 30 06:02:30 PM PDT 24
Peak memory 196428 kb
Host smart-ad1ada59-10b0-46fd-b987-ee9a96e9d9a7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266328932 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din_no_pullup
_pulldown.266328932
Directory /workspace/23.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_random_long_reg_writes_reg_reads.1650923922
Short name T330
Test name
Test status
Simulation time 85233940 ps
CPU time 3.91 seconds
Started Jul 30 06:02:38 PM PDT 24
Finished Jul 30 06:02:42 PM PDT 24
Peak memory 198560 kb
Host smart-80252f9b-af9f-4745-9c55-cc86a510886b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650923922 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_ra
ndom_long_reg_writes_reg_reads.1650923922
Directory /workspace/23.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/23.gpio_smoke.4108977086
Short name T385
Test name
Test status
Simulation time 217348280 ps
CPU time 1.54 seconds
Started Jul 30 06:02:24 PM PDT 24
Finished Jul 30 06:02:26 PM PDT 24
Peak memory 198572 kb
Host smart-1516215c-2ca6-4b41-b3c1-eefaab22284f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4108977086 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke.4108977086
Directory /workspace/23.gpio_smoke/latest

Test location /workspace/coverage/default/23.gpio_smoke_no_pullup_pulldown.1830000441
Short name T628
Test name
Test status
Simulation time 175662678 ps
CPU time 1.35 seconds
Started Jul 30 06:02:36 PM PDT 24
Finished Jul 30 06:02:38 PM PDT 24
Peak memory 197444 kb
Host smart-1c86db1c-7ea7-4c55-a250-6afdf0d5410d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830000441 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown.1830000441
Directory /workspace/23.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_stress_all.2627055482
Short name T196
Test name
Test status
Simulation time 29486730802 ps
CPU time 211.7 seconds
Started Jul 30 06:02:43 PM PDT 24
Finished Jul 30 06:06:15 PM PDT 24
Peak memory 198748 kb
Host smart-a86f0913-9aaa-45f4-8630-b18a373c8e89
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627055482 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.
gpio_stress_all.2627055482
Directory /workspace/23.gpio_stress_all/latest

Test location /workspace/coverage/default/24.gpio_alert_test.1779774698
Short name T316
Test name
Test status
Simulation time 32719765 ps
CPU time 0.56 seconds
Started Jul 30 06:02:24 PM PDT 24
Finished Jul 30 06:02:24 PM PDT 24
Peak memory 194532 kb
Host smart-4060957e-d360-40d0-b416-7c31937ed398
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779774698 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_alert_test.1779774698
Directory /workspace/24.gpio_alert_test/latest

Test location /workspace/coverage/default/24.gpio_dout_din_regs_random_rw.1097174503
Short name T402
Test name
Test status
Simulation time 37114359 ps
CPU time 0.77 seconds
Started Jul 30 06:02:37 PM PDT 24
Finished Jul 30 06:02:38 PM PDT 24
Peak memory 195812 kb
Host smart-7cb7a87e-0cec-4582-964f-02ab1bbf1da5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1097174503 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_dout_din_regs_random_rw.1097174503
Directory /workspace/24.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/24.gpio_filter_stress.2865800417
Short name T279
Test name
Test status
Simulation time 4901443789 ps
CPU time 22.56 seconds
Started Jul 30 06:02:29 PM PDT 24
Finished Jul 30 06:02:52 PM PDT 24
Peak memory 197592 kb
Host smart-4c6361fc-8507-4984-8f7b-534352c26ad3
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865800417 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_filter_stre
ss.2865800417
Directory /workspace/24.gpio_filter_stress/latest

Test location /workspace/coverage/default/24.gpio_full_random.3704059506
Short name T147
Test name
Test status
Simulation time 239876630 ps
CPU time 0.91 seconds
Started Jul 30 06:02:37 PM PDT 24
Finished Jul 30 06:02:38 PM PDT 24
Peak memory 197768 kb
Host smart-88de1ea4-00ad-4375-b518-f963adf3238c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704059506 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_full_random.3704059506
Directory /workspace/24.gpio_full_random/latest

Test location /workspace/coverage/default/24.gpio_intr_rand_pgm.2224393771
Short name T592
Test name
Test status
Simulation time 218519377 ps
CPU time 1.07 seconds
Started Jul 30 06:02:35 PM PDT 24
Finished Jul 30 06:02:36 PM PDT 24
Peak memory 196456 kb
Host smart-75e69ae7-7213-45e3-8efe-22b160dec4d7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224393771 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_intr_rand_pgm.2224393771
Directory /workspace/24.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/24.gpio_intr_with_filter_rand_intr_event.4091133658
Short name T197
Test name
Test status
Simulation time 35286736 ps
CPU time 1.53 seconds
Started Jul 30 06:02:30 PM PDT 24
Finished Jul 30 06:02:31 PM PDT 24
Peak memory 197544 kb
Host smart-d671dd6b-bfce-4ad5-bb09-d3e4e1f2d567
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091133658 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 24.gpio_intr_with_filter_rand_intr_event.4091133658
Directory /workspace/24.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/24.gpio_rand_intr_trigger.1813297180
Short name T619
Test name
Test status
Simulation time 118477919 ps
CPU time 1.06 seconds
Started Jul 30 06:02:25 PM PDT 24
Finished Jul 30 06:02:26 PM PDT 24
Peak memory 196852 kb
Host smart-6c5d1a31-a687-4173-9223-6909a56b1345
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813297180 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_rand_intr_trigger
.1813297180
Directory /workspace/24.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din.920237111
Short name T540
Test name
Test status
Simulation time 233587996 ps
CPU time 1.24 seconds
Started Jul 30 06:02:30 PM PDT 24
Finished Jul 30 06:02:32 PM PDT 24
Peak memory 198604 kb
Host smart-a68d572c-b09f-448a-a000-0912c5942658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=920237111 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din.920237111
Directory /workspace/24.gpio_random_dout_din/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din_no_pullup_pulldown.504284708
Short name T520
Test name
Test status
Simulation time 46203991 ps
CPU time 0.74 seconds
Started Jul 30 06:02:46 PM PDT 24
Finished Jul 30 06:02:47 PM PDT 24
Peak memory 195892 kb
Host smart-502bcdaf-4f86-40e8-a7ec-947625bb4814
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504284708 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din_no_pullup
_pulldown.504284708
Directory /workspace/24.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_random_long_reg_writes_reg_reads.3995762116
Short name T229
Test name
Test status
Simulation time 1479066928 ps
CPU time 4.45 seconds
Started Jul 30 06:02:33 PM PDT 24
Finished Jul 30 06:02:37 PM PDT 24
Peak memory 198612 kb
Host smart-87f3038c-59f0-4c4e-90ca-907b95108824
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995762116 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_ra
ndom_long_reg_writes_reg_reads.3995762116
Directory /workspace/24.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/24.gpio_smoke.3285395527
Short name T329
Test name
Test status
Simulation time 85700236 ps
CPU time 1.34 seconds
Started Jul 30 06:02:39 PM PDT 24
Finished Jul 30 06:02:40 PM PDT 24
Peak memory 196316 kb
Host smart-d564e729-0eea-4d51-93f3-c1f706de07e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3285395527 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke.3285395527
Directory /workspace/24.gpio_smoke/latest

Test location /workspace/coverage/default/24.gpio_smoke_no_pullup_pulldown.2053053589
Short name T374
Test name
Test status
Simulation time 120773955 ps
CPU time 1.12 seconds
Started Jul 30 06:02:28 PM PDT 24
Finished Jul 30 06:02:29 PM PDT 24
Peak memory 196104 kb
Host smart-73a8934e-0282-4144-bf69-3211293f8b1e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053053589 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown.2053053589
Directory /workspace/24.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_stress_all.1466084582
Short name T271
Test name
Test status
Simulation time 6382253257 ps
CPU time 44.81 seconds
Started Jul 30 06:02:38 PM PDT 24
Finished Jul 30 06:03:23 PM PDT 24
Peak memory 198772 kb
Host smart-a53b27f4-444b-475f-9573-09a24b029b7a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466084582 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.
gpio_stress_all.1466084582
Directory /workspace/24.gpio_stress_all/latest

Test location /workspace/coverage/default/25.gpio_alert_test.3173450678
Short name T364
Test name
Test status
Simulation time 109626822 ps
CPU time 0.59 seconds
Started Jul 30 06:02:30 PM PDT 24
Finished Jul 30 06:02:31 PM PDT 24
Peak memory 194528 kb
Host smart-ff8f828d-b2f6-45b5-8fe0-91b78c541c98
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173450678 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_alert_test.3173450678
Directory /workspace/25.gpio_alert_test/latest

Test location /workspace/coverage/default/25.gpio_dout_din_regs_random_rw.762300889
Short name T445
Test name
Test status
Simulation time 24254262 ps
CPU time 0.77 seconds
Started Jul 30 06:02:41 PM PDT 24
Finished Jul 30 06:02:42 PM PDT 24
Peak memory 195908 kb
Host smart-7a2f070d-6c6e-41c0-b19a-895f53f69379
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762300889 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_dout_din_regs_random_rw.762300889
Directory /workspace/25.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/25.gpio_filter_stress.866138895
Short name T400
Test name
Test status
Simulation time 398479036 ps
CPU time 19.63 seconds
Started Jul 30 06:02:44 PM PDT 24
Finished Jul 30 06:03:04 PM PDT 24
Peak memory 196160 kb
Host smart-590d4e2e-70ac-44dd-957b-146398b4b32b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866138895 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_filter_stres
s.866138895
Directory /workspace/25.gpio_filter_stress/latest

Test location /workspace/coverage/default/25.gpio_full_random.956309543
Short name T362
Test name
Test status
Simulation time 89866844 ps
CPU time 1.16 seconds
Started Jul 30 06:02:33 PM PDT 24
Finished Jul 30 06:02:34 PM PDT 24
Peak memory 198384 kb
Host smart-71d3038b-a777-4eb1-8f75-4eb56e95324e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956309543 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_full_random.956309543
Directory /workspace/25.gpio_full_random/latest

Test location /workspace/coverage/default/25.gpio_intr_rand_pgm.546071789
Short name T351
Test name
Test status
Simulation time 76270230 ps
CPU time 0.76 seconds
Started Jul 30 06:02:34 PM PDT 24
Finished Jul 30 06:02:35 PM PDT 24
Peak memory 196092 kb
Host smart-136968b9-62ad-4082-b5ef-44f7a995929d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546071789 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_intr_rand_pgm.546071789
Directory /workspace/25.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/25.gpio_intr_with_filter_rand_intr_event.692062815
Short name T309
Test name
Test status
Simulation time 173817486 ps
CPU time 1.77 seconds
Started Jul 30 06:02:29 PM PDT 24
Finished Jul 30 06:02:31 PM PDT 24
Peak memory 198744 kb
Host smart-566ed50f-9126-42ec-9428-26e4dffbee27
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692062815 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 25.gpio_intr_with_filter_rand_intr_event.692062815
Directory /workspace/25.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/25.gpio_rand_intr_trigger.3650577815
Short name T552
Test name
Test status
Simulation time 283008447 ps
CPU time 1.2 seconds
Started Jul 30 06:02:27 PM PDT 24
Finished Jul 30 06:02:28 PM PDT 24
Peak memory 197024 kb
Host smart-252384cb-d711-482a-9b32-f7ff22500e39
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650577815 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_rand_intr_trigger
.3650577815
Directory /workspace/25.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din.2463782558
Short name T657
Test name
Test status
Simulation time 24880314 ps
CPU time 0.87 seconds
Started Jul 30 06:02:36 PM PDT 24
Finished Jul 30 06:02:37 PM PDT 24
Peak memory 196636 kb
Host smart-5aa4c1e3-6c3d-40d3-8f19-0bad2dca0efd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2463782558 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din.2463782558
Directory /workspace/25.gpio_random_dout_din/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din_no_pullup_pulldown.623418640
Short name T502
Test name
Test status
Simulation time 181032875 ps
CPU time 1.04 seconds
Started Jul 30 06:02:36 PM PDT 24
Finished Jul 30 06:02:38 PM PDT 24
Peak memory 197228 kb
Host smart-9672ab78-5ee0-49d4-a4cb-2221feb16dce
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623418640 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din_no_pullup
_pulldown.623418640
Directory /workspace/25.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_random_long_reg_writes_reg_reads.4055264223
Short name T282
Test name
Test status
Simulation time 1114301867 ps
CPU time 5.32 seconds
Started Jul 30 06:02:32 PM PDT 24
Finished Jul 30 06:02:37 PM PDT 24
Peak memory 198600 kb
Host smart-1d3ccc6f-0687-461d-b4d2-b230b2d98687
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055264223 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_ra
ndom_long_reg_writes_reg_reads.4055264223
Directory /workspace/25.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/25.gpio_smoke.2111195180
Short name T544
Test name
Test status
Simulation time 111515869 ps
CPU time 1.03 seconds
Started Jul 30 06:02:41 PM PDT 24
Finished Jul 30 06:02:42 PM PDT 24
Peak memory 197040 kb
Host smart-22668903-9b2a-40e5-b2b3-76a150d61c1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2111195180 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke.2111195180
Directory /workspace/25.gpio_smoke/latest

Test location /workspace/coverage/default/25.gpio_smoke_no_pullup_pulldown.3884075710
Short name T72
Test name
Test status
Simulation time 151933253 ps
CPU time 1.45 seconds
Started Jul 30 06:02:30 PM PDT 24
Finished Jul 30 06:02:32 PM PDT 24
Peak memory 197496 kb
Host smart-1a0848b8-d86b-494a-8fd6-800853cc8ed6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884075710 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown.3884075710
Directory /workspace/25.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_stress_all.3377127636
Short name T10
Test name
Test status
Simulation time 14523890373 ps
CPU time 66.25 seconds
Started Jul 30 06:02:34 PM PDT 24
Finished Jul 30 06:03:40 PM PDT 24
Peak memory 198792 kb
Host smart-568a7594-f073-403f-9cef-34dfecea943b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377127636 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.
gpio_stress_all.3377127636
Directory /workspace/25.gpio_stress_all/latest

Test location /workspace/coverage/default/26.gpio_alert_test.2581800508
Short name T424
Test name
Test status
Simulation time 40119996 ps
CPU time 0.55 seconds
Started Jul 30 06:02:37 PM PDT 24
Finished Jul 30 06:02:38 PM PDT 24
Peak memory 194472 kb
Host smart-aab08d20-18cf-4c5a-b051-6e82617ae56d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581800508 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_alert_test.2581800508
Directory /workspace/26.gpio_alert_test/latest

Test location /workspace/coverage/default/26.gpio_dout_din_regs_random_rw.1095392009
Short name T335
Test name
Test status
Simulation time 133654902 ps
CPU time 0.66 seconds
Started Jul 30 06:02:41 PM PDT 24
Finished Jul 30 06:02:41 PM PDT 24
Peak memory 194772 kb
Host smart-5dcd1994-a2f0-4909-824d-50d580279dea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1095392009 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_dout_din_regs_random_rw.1095392009
Directory /workspace/26.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/26.gpio_filter_stress.378600177
Short name T688
Test name
Test status
Simulation time 2372208206 ps
CPU time 27.68 seconds
Started Jul 30 06:02:34 PM PDT 24
Finished Jul 30 06:03:02 PM PDT 24
Peak memory 198100 kb
Host smart-282364bb-84c7-4dc6-87ef-0ace2a5c61a1
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378600177 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_filter_stres
s.378600177
Directory /workspace/26.gpio_filter_stress/latest

Test location /workspace/coverage/default/26.gpio_full_random.769142283
Short name T369
Test name
Test status
Simulation time 30244764 ps
CPU time 0.69 seconds
Started Jul 30 06:02:34 PM PDT 24
Finished Jul 30 06:02:34 PM PDT 24
Peak memory 195932 kb
Host smart-59b6c29b-fa5d-4e80-a32b-f7cd230c7676
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769142283 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_full_random.769142283
Directory /workspace/26.gpio_full_random/latest

Test location /workspace/coverage/default/26.gpio_intr_rand_pgm.153956066
Short name T654
Test name
Test status
Simulation time 77471735 ps
CPU time 1.18 seconds
Started Jul 30 06:02:47 PM PDT 24
Finished Jul 30 06:02:49 PM PDT 24
Peak memory 196608 kb
Host smart-00be04e8-718b-40d1-bbc4-2f9cb8f23a20
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153956066 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_intr_rand_pgm.153956066
Directory /workspace/26.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/26.gpio_intr_with_filter_rand_intr_event.862971699
Short name T256
Test name
Test status
Simulation time 106640160 ps
CPU time 2.11 seconds
Started Jul 30 06:02:42 PM PDT 24
Finished Jul 30 06:02:44 PM PDT 24
Peak memory 198652 kb
Host smart-f15cd7d6-9add-4a72-9065-a9d8f055902b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862971699 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 26.gpio_intr_with_filter_rand_intr_event.862971699
Directory /workspace/26.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/26.gpio_rand_intr_trigger.141076458
Short name T509
Test name
Test status
Simulation time 44240868 ps
CPU time 1.16 seconds
Started Jul 30 06:02:35 PM PDT 24
Finished Jul 30 06:02:36 PM PDT 24
Peak memory 196104 kb
Host smart-5d0d3e4c-057d-4d6d-9bed-c89509548a02
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141076458 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_rand_intr_trigger.
141076458
Directory /workspace/26.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din.1615144168
Short name T152
Test name
Test status
Simulation time 126324647 ps
CPU time 1.21 seconds
Started Jul 30 06:02:38 PM PDT 24
Finished Jul 30 06:02:39 PM PDT 24
Peak memory 197612 kb
Host smart-0ad9a3fd-95b8-492e-9907-372ddf9ad573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1615144168 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din.1615144168
Directory /workspace/26.gpio_random_dout_din/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din_no_pullup_pulldown.4134139679
Short name T150
Test name
Test status
Simulation time 25192187 ps
CPU time 0.73 seconds
Started Jul 30 06:02:46 PM PDT 24
Finished Jul 30 06:02:47 PM PDT 24
Peak memory 194800 kb
Host smart-cb73ca55-a907-421e-8816-bb33f3d460ac
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134139679 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din_no_pullu
p_pulldown.4134139679
Directory /workspace/26.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_random_long_reg_writes_reg_reads.1328717345
Short name T591
Test name
Test status
Simulation time 697890757 ps
CPU time 5.47 seconds
Started Jul 30 06:02:34 PM PDT 24
Finished Jul 30 06:02:40 PM PDT 24
Peak memory 198572 kb
Host smart-aa5db7f0-b218-4c16-9fa8-89fa13217213
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328717345 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_ra
ndom_long_reg_writes_reg_reads.1328717345
Directory /workspace/26.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/26.gpio_smoke.3122126115
Short name T669
Test name
Test status
Simulation time 71503485 ps
CPU time 0.71 seconds
Started Jul 30 06:02:34 PM PDT 24
Finished Jul 30 06:02:35 PM PDT 24
Peak memory 195424 kb
Host smart-f5a7a250-71e2-42f7-9078-bc8ae0a4f400
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3122126115 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke.3122126115
Directory /workspace/26.gpio_smoke/latest

Test location /workspace/coverage/default/26.gpio_smoke_no_pullup_pulldown.3319957900
Short name T327
Test name
Test status
Simulation time 253040713 ps
CPU time 1.17 seconds
Started Jul 30 06:02:30 PM PDT 24
Finished Jul 30 06:02:36 PM PDT 24
Peak memory 197080 kb
Host smart-eccc53ce-efcb-4226-9199-fbb675501afa
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319957900 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown.3319957900
Directory /workspace/26.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_stress_all.3228976926
Short name T662
Test name
Test status
Simulation time 8506101469 ps
CPU time 124.14 seconds
Started Jul 30 06:02:29 PM PDT 24
Finished Jul 30 06:04:34 PM PDT 24
Peak memory 198816 kb
Host smart-24304a4b-e6e9-4cf9-9a81-930fe391a22d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228976926 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.
gpio_stress_all.3228976926
Directory /workspace/26.gpio_stress_all/latest

Test location /workspace/coverage/default/27.gpio_alert_test.2278167696
Short name T644
Test name
Test status
Simulation time 14414004 ps
CPU time 0.61 seconds
Started Jul 30 06:02:49 PM PDT 24
Finished Jul 30 06:02:49 PM PDT 24
Peak memory 194560 kb
Host smart-119174bb-b7ae-4a3d-83c4-4a6bff36c53f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278167696 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_alert_test.2278167696
Directory /workspace/27.gpio_alert_test/latest

Test location /workspace/coverage/default/27.gpio_dout_din_regs_random_rw.1280097826
Short name T125
Test name
Test status
Simulation time 45456421 ps
CPU time 0.96 seconds
Started Jul 30 06:02:28 PM PDT 24
Finished Jul 30 06:02:29 PM PDT 24
Peak memory 197308 kb
Host smart-efaf0d3a-700e-44f7-b5b1-5e36c2edb70c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1280097826 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_dout_din_regs_random_rw.1280097826
Directory /workspace/27.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/27.gpio_filter_stress.3444818197
Short name T545
Test name
Test status
Simulation time 505207953 ps
CPU time 4.24 seconds
Started Jul 30 06:02:35 PM PDT 24
Finished Jul 30 06:02:40 PM PDT 24
Peak memory 197104 kb
Host smart-1378dab3-3c82-4277-bd8b-53998f696716
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444818197 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_filter_stre
ss.3444818197
Directory /workspace/27.gpio_filter_stress/latest

Test location /workspace/coverage/default/27.gpio_full_random.4123295044
Short name T667
Test name
Test status
Simulation time 82350229 ps
CPU time 1.04 seconds
Started Jul 30 06:02:43 PM PDT 24
Finished Jul 30 06:02:45 PM PDT 24
Peak memory 197020 kb
Host smart-c1944a9b-a2d2-4648-957a-76f2ea09fd1c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123295044 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_full_random.4123295044
Directory /workspace/27.gpio_full_random/latest

Test location /workspace/coverage/default/27.gpio_intr_rand_pgm.3970725312
Short name T405
Test name
Test status
Simulation time 469312497 ps
CPU time 1.1 seconds
Started Jul 30 06:02:51 PM PDT 24
Finished Jul 30 06:02:52 PM PDT 24
Peak memory 196404 kb
Host smart-82eb1b10-a50d-4993-a205-4553a738ff0b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970725312 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_intr_rand_pgm.3970725312
Directory /workspace/27.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/27.gpio_intr_with_filter_rand_intr_event.1024301239
Short name T372
Test name
Test status
Simulation time 36337915 ps
CPU time 1.6 seconds
Started Jul 30 06:02:47 PM PDT 24
Finished Jul 30 06:02:48 PM PDT 24
Peak memory 198816 kb
Host smart-99962a7b-4edb-46e9-8004-d3f51678d1cb
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024301239 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 27.gpio_intr_with_filter_rand_intr_event.1024301239
Directory /workspace/27.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/27.gpio_rand_intr_trigger.3839752449
Short name T249
Test name
Test status
Simulation time 90859402 ps
CPU time 2.55 seconds
Started Jul 30 06:02:28 PM PDT 24
Finished Jul 30 06:02:31 PM PDT 24
Peak memory 197596 kb
Host smart-ea852269-042d-4de6-b84c-d1624bf6e2e3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839752449 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_rand_intr_trigger
.3839752449
Directory /workspace/27.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din.98620726
Short name T54
Test name
Test status
Simulation time 64636399 ps
CPU time 1.29 seconds
Started Jul 30 06:02:36 PM PDT 24
Finished Jul 30 06:02:38 PM PDT 24
Peak memory 197448 kb
Host smart-c7cff14b-524f-435c-a342-805e9a00ac8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98620726 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din.98620726
Directory /workspace/27.gpio_random_dout_din/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din_no_pullup_pulldown.73903261
Short name T603
Test name
Test status
Simulation time 22594756 ps
CPU time 0.75 seconds
Started Jul 30 06:02:42 PM PDT 24
Finished Jul 30 06:02:43 PM PDT 24
Peak memory 195876 kb
Host smart-6e8caced-1ed5-4f14-b0f6-5efde346a1fa
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73903261 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din_no_pullup_
pulldown.73903261
Directory /workspace/27.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_random_long_reg_writes_reg_reads.3567786758
Short name T20
Test name
Test status
Simulation time 367721312 ps
CPU time 6.34 seconds
Started Jul 30 06:02:45 PM PDT 24
Finished Jul 30 06:02:51 PM PDT 24
Peak memory 198648 kb
Host smart-7d949b6f-e0aa-475b-bad9-28bb0294d535
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567786758 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_ra
ndom_long_reg_writes_reg_reads.3567786758
Directory /workspace/27.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/27.gpio_smoke.2158557041
Short name T630
Test name
Test status
Simulation time 49039842 ps
CPU time 0.87 seconds
Started Jul 30 06:02:32 PM PDT 24
Finished Jul 30 06:02:33 PM PDT 24
Peak memory 195972 kb
Host smart-d76e66bd-8395-46d9-892c-523afc0fe565
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2158557041 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke.2158557041
Directory /workspace/27.gpio_smoke/latest

Test location /workspace/coverage/default/27.gpio_smoke_no_pullup_pulldown.559403960
Short name T177
Test name
Test status
Simulation time 130085805 ps
CPU time 1.31 seconds
Started Jul 30 06:02:34 PM PDT 24
Finished Jul 30 06:02:36 PM PDT 24
Peak memory 197232 kb
Host smart-7f1b79f2-698a-4b32-9ce2-e1f8ddd599d3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559403960 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown.559403960
Directory /workspace/27.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_stress_all.3727365270
Short name T693
Test name
Test status
Simulation time 29766607736 ps
CPU time 186.56 seconds
Started Jul 30 06:02:40 PM PDT 24
Finished Jul 30 06:05:47 PM PDT 24
Peak memory 198784 kb
Host smart-0de30f1d-5e9d-4f52-a53f-4b2f35b70f93
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727365270 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.
gpio_stress_all.3727365270
Directory /workspace/27.gpio_stress_all/latest

Test location /workspace/coverage/default/27.gpio_stress_all_with_rand_reset.3907591344
Short name T653
Test name
Test status
Simulation time 41817120463 ps
CPU time 1182.53 seconds
Started Jul 30 06:02:47 PM PDT 24
Finished Jul 30 06:22:30 PM PDT 24
Peak memory 199072 kb
Host smart-93891058-2434-4d5f-ac94-ea6c96c927f1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3907591344 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_stress_all_with_rand_reset.3907591344
Directory /workspace/27.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.gpio_alert_test.3946921033
Short name T536
Test name
Test status
Simulation time 14300066 ps
CPU time 0.59 seconds
Started Jul 30 06:02:46 PM PDT 24
Finished Jul 30 06:02:47 PM PDT 24
Peak memory 195388 kb
Host smart-fc6d61d9-086b-4a64-b5a0-f118d30766ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946921033 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_alert_test.3946921033
Directory /workspace/28.gpio_alert_test/latest

Test location /workspace/coverage/default/28.gpio_dout_din_regs_random_rw.1600091146
Short name T301
Test name
Test status
Simulation time 39416413 ps
CPU time 0.62 seconds
Started Jul 30 06:02:44 PM PDT 24
Finished Jul 30 06:02:45 PM PDT 24
Peak memory 194432 kb
Host smart-869e3dbc-da30-4c1d-a830-350fc28422be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600091146 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_dout_din_regs_random_rw.1600091146
Directory /workspace/28.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/28.gpio_filter_stress.1232196611
Short name T528
Test name
Test status
Simulation time 1774016442 ps
CPU time 22.74 seconds
Started Jul 30 06:02:51 PM PDT 24
Finished Jul 30 06:03:13 PM PDT 24
Peak memory 197424 kb
Host smart-195b839a-dc78-4a87-a071-05052577efef
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232196611 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_filter_stre
ss.1232196611
Directory /workspace/28.gpio_filter_stress/latest

Test location /workspace/coverage/default/28.gpio_full_random.1175781395
Short name T472
Test name
Test status
Simulation time 190848377 ps
CPU time 1.15 seconds
Started Jul 30 06:02:34 PM PDT 24
Finished Jul 30 06:02:35 PM PDT 24
Peak memory 196916 kb
Host smart-c6b5f61e-5e93-48e2-b6e5-f2639fed3fa6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175781395 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_full_random.1175781395
Directory /workspace/28.gpio_full_random/latest

Test location /workspace/coverage/default/28.gpio_intr_rand_pgm.2169126287
Short name T615
Test name
Test status
Simulation time 90510159 ps
CPU time 0.95 seconds
Started Jul 30 06:02:49 PM PDT 24
Finished Jul 30 06:02:50 PM PDT 24
Peak memory 197336 kb
Host smart-399a12a7-b7fe-4f78-97e1-f0ae9037cef1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169126287 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_intr_rand_pgm.2169126287
Directory /workspace/28.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/28.gpio_intr_with_filter_rand_intr_event.1425351428
Short name T486
Test name
Test status
Simulation time 63498413 ps
CPU time 2.45 seconds
Started Jul 30 06:02:37 PM PDT 24
Finished Jul 30 06:02:39 PM PDT 24
Peak memory 198564 kb
Host smart-0a024f1e-1e36-4b58-bb46-5373230bc3ba
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425351428 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 28.gpio_intr_with_filter_rand_intr_event.1425351428
Directory /workspace/28.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/28.gpio_rand_intr_trigger.3634360023
Short name T303
Test name
Test status
Simulation time 59169442 ps
CPU time 1.5 seconds
Started Jul 30 06:02:34 PM PDT 24
Finished Jul 30 06:02:35 PM PDT 24
Peak memory 197416 kb
Host smart-6ab65e6b-81a9-4219-aa97-15cc0599a9bd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634360023 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_rand_intr_trigger
.3634360023
Directory /workspace/28.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din.3206590699
Short name T140
Test name
Test status
Simulation time 50269496 ps
CPU time 0.78 seconds
Started Jul 30 06:02:48 PM PDT 24
Finished Jul 30 06:02:49 PM PDT 24
Peak memory 196700 kb
Host smart-1435d307-d91a-4ff5-a56b-c7babb653156
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3206590699 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din.3206590699
Directory /workspace/28.gpio_random_dout_din/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din_no_pullup_pulldown.743338817
Short name T183
Test name
Test status
Simulation time 85602997 ps
CPU time 1.1 seconds
Started Jul 30 06:02:50 PM PDT 24
Finished Jul 30 06:02:51 PM PDT 24
Peak memory 196576 kb
Host smart-b12f801c-a9ca-411a-bf98-b906945db780
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743338817 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din_no_pullup
_pulldown.743338817
Directory /workspace/28.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_random_long_reg_writes_reg_reads.3694359368
Short name T2
Test name
Test status
Simulation time 355447196 ps
CPU time 4.35 seconds
Started Jul 30 06:02:45 PM PDT 24
Finished Jul 30 06:02:49 PM PDT 24
Peak memory 198472 kb
Host smart-4247d3a8-e63a-4242-99d3-88c710446d66
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694359368 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_ra
ndom_long_reg_writes_reg_reads.3694359368
Directory /workspace/28.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/28.gpio_smoke.409513657
Short name T514
Test name
Test status
Simulation time 91661493 ps
CPU time 1.09 seconds
Started Jul 30 06:02:48 PM PDT 24
Finished Jul 30 06:02:50 PM PDT 24
Peak memory 197004 kb
Host smart-18ea9168-6b31-4779-aed7-b0d96aa795b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=409513657 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke.409513657
Directory /workspace/28.gpio_smoke/latest

Test location /workspace/coverage/default/28.gpio_smoke_no_pullup_pulldown.1709379515
Short name T517
Test name
Test status
Simulation time 51503949 ps
CPU time 0.87 seconds
Started Jul 30 06:02:37 PM PDT 24
Finished Jul 30 06:02:38 PM PDT 24
Peak memory 196484 kb
Host smart-aef598ab-5559-40d8-b126-43fbac4426bb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709379515 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown.1709379515
Directory /workspace/28.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_stress_all.3539003280
Short name T474
Test name
Test status
Simulation time 5097876739 ps
CPU time 58.71 seconds
Started Jul 30 06:02:45 PM PDT 24
Finished Jul 30 06:03:44 PM PDT 24
Peak memory 198764 kb
Host smart-fa345059-06a7-42ff-9a2a-9250a14c5a3b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539003280 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.
gpio_stress_all.3539003280
Directory /workspace/28.gpio_stress_all/latest

Test location /workspace/coverage/default/28.gpio_stress_all_with_rand_reset.3691482908
Short name T31
Test name
Test status
Simulation time 48349396947 ps
CPU time 1306.19 seconds
Started Jul 30 06:02:50 PM PDT 24
Finished Jul 30 06:24:36 PM PDT 24
Peak memory 198976 kb
Host smart-55c291c0-e8c8-4147-afa6-c27cad145ad2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3691482908 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_stress_all_with_rand_reset.3691482908
Directory /workspace/28.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.gpio_alert_test.3223710706
Short name T512
Test name
Test status
Simulation time 46984866 ps
CPU time 0.57 seconds
Started Jul 30 06:02:43 PM PDT 24
Finished Jul 30 06:02:43 PM PDT 24
Peak memory 194476 kb
Host smart-c745ce62-ce17-43eb-9ed4-671f1648c66b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223710706 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_alert_test.3223710706
Directory /workspace/29.gpio_alert_test/latest

Test location /workspace/coverage/default/29.gpio_dout_din_regs_random_rw.1436749760
Short name T569
Test name
Test status
Simulation time 26401571 ps
CPU time 0.71 seconds
Started Jul 30 06:02:50 PM PDT 24
Finished Jul 30 06:02:51 PM PDT 24
Peak memory 194776 kb
Host smart-113c834c-7a2b-4111-9ced-69481a6f16dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436749760 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_dout_din_regs_random_rw.1436749760
Directory /workspace/29.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/29.gpio_filter_stress.2389580408
Short name T325
Test name
Test status
Simulation time 842555038 ps
CPU time 11.24 seconds
Started Jul 30 06:02:36 PM PDT 24
Finished Jul 30 06:02:47 PM PDT 24
Peak memory 198628 kb
Host smart-7084210f-4c43-48a9-8efd-92bc8e955347
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389580408 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_filter_stre
ss.2389580408
Directory /workspace/29.gpio_filter_stress/latest

Test location /workspace/coverage/default/29.gpio_full_random.1435099637
Short name T590
Test name
Test status
Simulation time 323790089 ps
CPU time 0.89 seconds
Started Jul 30 06:02:38 PM PDT 24
Finished Jul 30 06:02:39 PM PDT 24
Peak memory 197272 kb
Host smart-3411424f-cbdd-4f3b-ba6c-99c1e25f97bb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435099637 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_full_random.1435099637
Directory /workspace/29.gpio_full_random/latest

Test location /workspace/coverage/default/29.gpio_intr_rand_pgm.1632818288
Short name T269
Test name
Test status
Simulation time 801129768 ps
CPU time 1.51 seconds
Started Jul 30 06:02:48 PM PDT 24
Finished Jul 30 06:02:49 PM PDT 24
Peak memory 197632 kb
Host smart-e038d308-06a7-41d6-a49d-b8177649df52
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632818288 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_intr_rand_pgm.1632818288
Directory /workspace/29.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/29.gpio_intr_with_filter_rand_intr_event.2967188729
Short name T480
Test name
Test status
Simulation time 100369942 ps
CPU time 2.03 seconds
Started Jul 30 06:02:56 PM PDT 24
Finished Jul 30 06:02:58 PM PDT 24
Peak memory 198648 kb
Host smart-cc868570-978c-4f70-bdcb-e10f11b68227
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967188729 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 29.gpio_intr_with_filter_rand_intr_event.2967188729
Directory /workspace/29.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/29.gpio_rand_intr_trigger.906651618
Short name T493
Test name
Test status
Simulation time 616947102 ps
CPU time 2.52 seconds
Started Jul 30 06:02:44 PM PDT 24
Finished Jul 30 06:02:47 PM PDT 24
Peak memory 197516 kb
Host smart-e7909917-4511-4345-882a-66623722dddd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906651618 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_rand_intr_trigger.
906651618
Directory /workspace/29.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din.3318619078
Short name T663
Test name
Test status
Simulation time 20919683 ps
CPU time 0.84 seconds
Started Jul 30 06:02:45 PM PDT 24
Finished Jul 30 06:02:46 PM PDT 24
Peak memory 197900 kb
Host smart-cfc3fe39-dc99-4c8c-ba35-3952889e1669
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3318619078 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din.3318619078
Directory /workspace/29.gpio_random_dout_din/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din_no_pullup_pulldown.3585731485
Short name T348
Test name
Test status
Simulation time 38459156 ps
CPU time 0.93 seconds
Started Jul 30 06:02:46 PM PDT 24
Finished Jul 30 06:02:47 PM PDT 24
Peak memory 196592 kb
Host smart-99374f48-f029-4f90-9541-da2eb888fa8b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585731485 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din_no_pullu
p_pulldown.3585731485
Directory /workspace/29.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_random_long_reg_writes_reg_reads.1117587980
Short name T338
Test name
Test status
Simulation time 157196408 ps
CPU time 1.57 seconds
Started Jul 30 06:02:46 PM PDT 24
Finished Jul 30 06:02:48 PM PDT 24
Peak memory 198620 kb
Host smart-0026ae4c-16cb-4ba4-b8e5-700eb2074c86
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117587980 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_ra
ndom_long_reg_writes_reg_reads.1117587980
Directory /workspace/29.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/29.gpio_smoke.779113423
Short name T715
Test name
Test status
Simulation time 37592518 ps
CPU time 1.08 seconds
Started Jul 30 06:02:49 PM PDT 24
Finished Jul 30 06:02:50 PM PDT 24
Peak memory 196160 kb
Host smart-85ebde25-9483-4c8d-abd6-3ce7c8ca20fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=779113423 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke.779113423
Directory /workspace/29.gpio_smoke/latest

Test location /workspace/coverage/default/29.gpio_smoke_no_pullup_pulldown.1434689911
Short name T580
Test name
Test status
Simulation time 88373919 ps
CPU time 0.91 seconds
Started Jul 30 06:02:30 PM PDT 24
Finished Jul 30 06:02:31 PM PDT 24
Peak memory 196768 kb
Host smart-b112ac60-aa1e-4b96-ad1a-054265c64325
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434689911 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown.1434689911
Directory /workspace/29.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_stress_all.2338427829
Short name T450
Test name
Test status
Simulation time 2737409700 ps
CPU time 73.83 seconds
Started Jul 30 06:02:44 PM PDT 24
Finished Jul 30 06:03:58 PM PDT 24
Peak memory 198724 kb
Host smart-55787873-6efc-4386-a67e-ad26b573a294
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338427829 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.
gpio_stress_all.2338427829
Directory /workspace/29.gpio_stress_all/latest

Test location /workspace/coverage/default/3.gpio_alert_test.695334221
Short name T631
Test name
Test status
Simulation time 14030150 ps
CPU time 0.58 seconds
Started Jul 30 06:01:50 PM PDT 24
Finished Jul 30 06:01:51 PM PDT 24
Peak memory 194536 kb
Host smart-2d650c18-43ab-4518-af65-2a99eb32cc89
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695334221 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_alert_test.695334221
Directory /workspace/3.gpio_alert_test/latest

Test location /workspace/coverage/default/3.gpio_filter_stress.1490628865
Short name T138
Test name
Test status
Simulation time 1798556817 ps
CPU time 24.83 seconds
Started Jul 30 06:01:56 PM PDT 24
Finished Jul 30 06:02:21 PM PDT 24
Peak memory 197052 kb
Host smart-598147c2-9037-4a05-b2e5-52cf82dacc48
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490628865 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_filter_stres
s.1490628865
Directory /workspace/3.gpio_filter_stress/latest

Test location /workspace/coverage/default/3.gpio_full_random.552603766
Short name T18
Test name
Test status
Simulation time 77445188 ps
CPU time 0.71 seconds
Started Jul 30 06:01:52 PM PDT 24
Finished Jul 30 06:01:53 PM PDT 24
Peak memory 195148 kb
Host smart-b87dee03-d644-487b-909f-7903194e15d1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552603766 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_full_random.552603766
Directory /workspace/3.gpio_full_random/latest

Test location /workspace/coverage/default/3.gpio_intr_rand_pgm.2136630864
Short name T691
Test name
Test status
Simulation time 49475752 ps
CPU time 1.33 seconds
Started Jul 30 06:01:52 PM PDT 24
Finished Jul 30 06:01:53 PM PDT 24
Peak memory 197412 kb
Host smart-045a8f45-e1c8-4292-a1bd-74901c38c6b3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136630864 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_intr_rand_pgm.2136630864
Directory /workspace/3.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/3.gpio_intr_with_filter_rand_intr_event.3475607409
Short name T490
Test name
Test status
Simulation time 201618338 ps
CPU time 2.29 seconds
Started Jul 30 06:01:53 PM PDT 24
Finished Jul 30 06:01:55 PM PDT 24
Peak memory 197112 kb
Host smart-52c56d27-3f54-445d-8bd2-ce0c6c20d7ae
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475607409 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.gpio_intr_with_filter_rand_intr_event.3475607409
Directory /workspace/3.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/3.gpio_rand_intr_trigger.123422411
Short name T67
Test name
Test status
Simulation time 58642408 ps
CPU time 1.6 seconds
Started Jul 30 06:01:50 PM PDT 24
Finished Jul 30 06:01:52 PM PDT 24
Peak memory 197112 kb
Host smart-59ed77e1-bff0-45c4-9988-30e3bc3b1f12
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123422411 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_rand_intr_trigger.123422411
Directory /workspace/3.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din.1244792909
Short name T184
Test name
Test status
Simulation time 25862887 ps
CPU time 0.77 seconds
Started Jul 30 06:01:49 PM PDT 24
Finished Jul 30 06:01:50 PM PDT 24
Peak memory 195900 kb
Host smart-abb6e04f-4239-4ecf-8466-62910b85a954
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1244792909 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din.1244792909
Directory /workspace/3.gpio_random_dout_din/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din_no_pullup_pulldown.3855076465
Short name T322
Test name
Test status
Simulation time 62748576 ps
CPU time 0.76 seconds
Started Jul 30 06:01:51 PM PDT 24
Finished Jul 30 06:01:52 PM PDT 24
Peak memory 196656 kb
Host smart-cbb2db80-c910-4c17-b7f7-cbcc29e20931
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855076465 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din_no_pullup
_pulldown.3855076465
Directory /workspace/3.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_random_long_reg_writes_reg_reads.25838020
Short name T589
Test name
Test status
Simulation time 1969192224 ps
CPU time 4.61 seconds
Started Jul 30 06:01:49 PM PDT 24
Finished Jul 30 06:01:53 PM PDT 24
Peak memory 198480 kb
Host smart-e806882c-76d9-44dc-96ab-f8ec116a0e90
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25838020 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_w
rites_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_rando
m_long_reg_writes_reg_reads.25838020
Directory /workspace/3.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/3.gpio_sec_cm.3186564012
Short name T35
Test name
Test status
Simulation time 174319573 ps
CPU time 0.84 seconds
Started Jul 30 06:01:45 PM PDT 24
Finished Jul 30 06:01:46 PM PDT 24
Peak memory 214552 kb
Host smart-b0bcd734-84b3-44fc-ac43-90ce9bba97ad
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186564012 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_sec_cm.3186564012
Directory /workspace/3.gpio_sec_cm/latest

Test location /workspace/coverage/default/3.gpio_smoke.3760163151
Short name T161
Test name
Test status
Simulation time 37871217 ps
CPU time 0.8 seconds
Started Jul 30 06:01:54 PM PDT 24
Finished Jul 30 06:01:55 PM PDT 24
Peak memory 195728 kb
Host smart-eab762ae-1351-4208-ae94-d8ca0b3de5d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3760163151 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke.3760163151
Directory /workspace/3.gpio_smoke/latest

Test location /workspace/coverage/default/3.gpio_smoke_no_pullup_pulldown.536722583
Short name T387
Test name
Test status
Simulation time 104188102 ps
CPU time 0.72 seconds
Started Jul 30 06:01:55 PM PDT 24
Finished Jul 30 06:01:56 PM PDT 24
Peak memory 195496 kb
Host smart-3482d10a-45f9-4800-acb0-bc1ae3fff27a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536722583 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown.536722583
Directory /workspace/3.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_stress_all.1628916033
Short name T699
Test name
Test status
Simulation time 8919074594 ps
CPU time 62.73 seconds
Started Jul 30 06:01:50 PM PDT 24
Finished Jul 30 06:02:53 PM PDT 24
Peak memory 198756 kb
Host smart-fb145928-fda6-47c4-9941-61ed708f470f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628916033 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.g
pio_stress_all.1628916033
Directory /workspace/3.gpio_stress_all/latest

Test location /workspace/coverage/default/3.gpio_stress_all_with_rand_reset.2859619169
Short name T392
Test name
Test status
Simulation time 58160885104 ps
CPU time 460.86 seconds
Started Jul 30 06:01:47 PM PDT 24
Finished Jul 30 06:09:28 PM PDT 24
Peak memory 198900 kb
Host smart-96513d1b-4db4-4880-8d95-d3cbaa7717ac
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2859619169 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_stress_all_with_rand_reset.2859619169
Directory /workspace/3.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.gpio_alert_test.1634178721
Short name T443
Test name
Test status
Simulation time 36330100 ps
CPU time 0.55 seconds
Started Jul 30 06:02:40 PM PDT 24
Finished Jul 30 06:02:41 PM PDT 24
Peak memory 194452 kb
Host smart-7e6ea7a6-2d5b-4269-9655-e7b1c490f80f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634178721 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_alert_test.1634178721
Directory /workspace/30.gpio_alert_test/latest

Test location /workspace/coverage/default/30.gpio_dout_din_regs_random_rw.4115335799
Short name T583
Test name
Test status
Simulation time 53246976 ps
CPU time 0.92 seconds
Started Jul 30 06:02:46 PM PDT 24
Finished Jul 30 06:02:47 PM PDT 24
Peak memory 195960 kb
Host smart-2472318b-114f-4728-a17a-27cbc29ec28a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4115335799 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_dout_din_regs_random_rw.4115335799
Directory /workspace/30.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/30.gpio_filter_stress.4215915108
Short name T131
Test name
Test status
Simulation time 879535065 ps
CPU time 24.25 seconds
Started Jul 30 06:02:43 PM PDT 24
Finished Jul 30 06:03:07 PM PDT 24
Peak memory 197276 kb
Host smart-9d19285d-ef84-46e8-8eab-7bda3b41e305
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215915108 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_filter_stre
ss.4215915108
Directory /workspace/30.gpio_filter_stress/latest

Test location /workspace/coverage/default/30.gpio_full_random.2677041248
Short name T470
Test name
Test status
Simulation time 338452223 ps
CPU time 1.09 seconds
Started Jul 30 06:02:48 PM PDT 24
Finished Jul 30 06:02:49 PM PDT 24
Peak memory 198236 kb
Host smart-125a17b2-2350-4eee-b2f9-0ad281b31dde
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677041248 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_full_random.2677041248
Directory /workspace/30.gpio_full_random/latest

Test location /workspace/coverage/default/30.gpio_intr_rand_pgm.1076329600
Short name T195
Test name
Test status
Simulation time 95713418 ps
CPU time 1.19 seconds
Started Jul 30 06:02:48 PM PDT 24
Finished Jul 30 06:02:49 PM PDT 24
Peak memory 196448 kb
Host smart-9c0aa31f-960c-425a-af8d-79e0adc9f717
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076329600 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_intr_rand_pgm.1076329600
Directory /workspace/30.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/30.gpio_intr_with_filter_rand_intr_event.2570212146
Short name T383
Test name
Test status
Simulation time 62303478 ps
CPU time 2.28 seconds
Started Jul 30 06:02:48 PM PDT 24
Finished Jul 30 06:02:50 PM PDT 24
Peak memory 197100 kb
Host smart-b33a04b5-174f-4ace-b340-eb23fbf1b7c6
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570212146 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 30.gpio_intr_with_filter_rand_intr_event.2570212146
Directory /workspace/30.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/30.gpio_rand_intr_trigger.4178762886
Short name T565
Test name
Test status
Simulation time 99103617 ps
CPU time 2.1 seconds
Started Jul 30 06:02:43 PM PDT 24
Finished Jul 30 06:02:45 PM PDT 24
Peak memory 196436 kb
Host smart-81cb1953-8b35-4b1e-9d90-603a9349dd69
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178762886 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_rand_intr_trigger
.4178762886
Directory /workspace/30.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din.666226086
Short name T24
Test name
Test status
Simulation time 67552970 ps
CPU time 0.94 seconds
Started Jul 30 06:02:47 PM PDT 24
Finished Jul 30 06:02:48 PM PDT 24
Peak memory 197280 kb
Host smart-5be64a2d-b46b-4514-b328-e93781b8338c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=666226086 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din.666226086
Directory /workspace/30.gpio_random_dout_din/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din_no_pullup_pulldown.3436278382
Short name T346
Test name
Test status
Simulation time 59020101 ps
CPU time 1.26 seconds
Started Jul 30 06:02:47 PM PDT 24
Finished Jul 30 06:02:49 PM PDT 24
Peak memory 197600 kb
Host smart-2317913e-ae10-43b2-8230-6eb3ea3eed34
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436278382 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din_no_pullu
p_pulldown.3436278382
Directory /workspace/30.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_random_long_reg_writes_reg_reads.3475046590
Short name T16
Test name
Test status
Simulation time 371568539 ps
CPU time 4.5 seconds
Started Jul 30 06:02:47 PM PDT 24
Finished Jul 30 06:02:52 PM PDT 24
Peak memory 198608 kb
Host smart-23c2e404-0a6e-4f2c-a064-b8d234529472
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475046590 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_ra
ndom_long_reg_writes_reg_reads.3475046590
Directory /workspace/30.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/30.gpio_smoke.3413092760
Short name T218
Test name
Test status
Simulation time 280308591 ps
CPU time 1.41 seconds
Started Jul 30 06:02:52 PM PDT 24
Finished Jul 30 06:02:53 PM PDT 24
Peak memory 198492 kb
Host smart-9962add9-bab5-48b5-b378-5cfce6a3154f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3413092760 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke.3413092760
Directory /workspace/30.gpio_smoke/latest

Test location /workspace/coverage/default/30.gpio_smoke_no_pullup_pulldown.996115131
Short name T626
Test name
Test status
Simulation time 330723636 ps
CPU time 1.45 seconds
Started Jul 30 06:02:45 PM PDT 24
Finished Jul 30 06:02:46 PM PDT 24
Peak memory 198632 kb
Host smart-a85dd881-e606-40d6-bb75-cfd091b8a3b4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996115131 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown.996115131
Directory /workspace/30.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_stress_all.3155696380
Short name T134
Test name
Test status
Simulation time 7066191886 ps
CPU time 90.98 seconds
Started Jul 30 06:02:40 PM PDT 24
Finished Jul 30 06:04:11 PM PDT 24
Peak memory 198720 kb
Host smart-cc94a68c-d431-4fba-b971-003aa45bbc21
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155696380 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.
gpio_stress_all.3155696380
Directory /workspace/30.gpio_stress_all/latest

Test location /workspace/coverage/default/30.gpio_stress_all_with_rand_reset.2050638283
Short name T342
Test name
Test status
Simulation time 28033192525 ps
CPU time 842.92 seconds
Started Jul 30 06:02:51 PM PDT 24
Finished Jul 30 06:16:54 PM PDT 24
Peak memory 198860 kb
Host smart-26ffca31-bc1a-4b52-a34f-64f561421375
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2050638283 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_stress_all_with_rand_reset.2050638283
Directory /workspace/30.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.gpio_alert_test.4164819970
Short name T505
Test name
Test status
Simulation time 49232848 ps
CPU time 0.59 seconds
Started Jul 30 06:02:50 PM PDT 24
Finished Jul 30 06:02:51 PM PDT 24
Peak memory 194612 kb
Host smart-21bf5809-d578-4340-878f-48dff88f3cd9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164819970 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_alert_test.4164819970
Directory /workspace/31.gpio_alert_test/latest

Test location /workspace/coverage/default/31.gpio_dout_din_regs_random_rw.842964729
Short name T272
Test name
Test status
Simulation time 30635997 ps
CPU time 0.76 seconds
Started Jul 30 06:02:41 PM PDT 24
Finished Jul 30 06:02:41 PM PDT 24
Peak memory 195660 kb
Host smart-6980e199-5b2c-44ce-94ee-b5a84102f9f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=842964729 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_dout_din_regs_random_rw.842964729
Directory /workspace/31.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/31.gpio_filter_stress.1928101798
Short name T166
Test name
Test status
Simulation time 1931479993 ps
CPU time 28.29 seconds
Started Jul 30 06:02:50 PM PDT 24
Finished Jul 30 06:03:19 PM PDT 24
Peak memory 197576 kb
Host smart-ed8bf7af-7384-446e-a5d1-4f2ba7598b12
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928101798 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_filter_stre
ss.1928101798
Directory /workspace/31.gpio_filter_stress/latest

Test location /workspace/coverage/default/31.gpio_full_random.3731023766
Short name T442
Test name
Test status
Simulation time 222157479 ps
CPU time 0.85 seconds
Started Jul 30 06:02:47 PM PDT 24
Finished Jul 30 06:02:48 PM PDT 24
Peak memory 197760 kb
Host smart-adf6d04f-8bb2-4f3d-a7cc-3128ee2617ba
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731023766 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_full_random.3731023766
Directory /workspace/31.gpio_full_random/latest

Test location /workspace/coverage/default/31.gpio_intr_rand_pgm.4002415071
Short name T382
Test name
Test status
Simulation time 41625385 ps
CPU time 1.15 seconds
Started Jul 30 06:02:37 PM PDT 24
Finished Jul 30 06:02:39 PM PDT 24
Peak memory 196740 kb
Host smart-e876992d-8a31-475a-b2c3-4b0f5af984d4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002415071 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_intr_rand_pgm.4002415071
Directory /workspace/31.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/31.gpio_intr_with_filter_rand_intr_event.1596145099
Short name T128
Test name
Test status
Simulation time 67217471 ps
CPU time 1.82 seconds
Started Jul 30 06:02:48 PM PDT 24
Finished Jul 30 06:02:50 PM PDT 24
Peak memory 198732 kb
Host smart-2a255502-a6c3-45a3-89b7-bf40a1ea0144
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596145099 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 31.gpio_intr_with_filter_rand_intr_event.1596145099
Directory /workspace/31.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/31.gpio_rand_intr_trigger.1013198669
Short name T610
Test name
Test status
Simulation time 72653186 ps
CPU time 0.99 seconds
Started Jul 30 06:02:50 PM PDT 24
Finished Jul 30 06:02:51 PM PDT 24
Peak memory 196188 kb
Host smart-b1ac6b5a-fd1b-459d-9475-f769c5e92ee8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013198669 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_rand_intr_trigger
.1013198669
Directory /workspace/31.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din.2272526776
Short name T614
Test name
Test status
Simulation time 109352653 ps
CPU time 1.22 seconds
Started Jul 30 06:02:35 PM PDT 24
Finished Jul 30 06:02:36 PM PDT 24
Peak memory 197644 kb
Host smart-2b74ead4-5bda-45ed-91f0-8c6ec39b015a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272526776 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din.2272526776
Directory /workspace/31.gpio_random_dout_din/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din_no_pullup_pulldown.2364109864
Short name T275
Test name
Test status
Simulation time 87811747 ps
CPU time 0.93 seconds
Started Jul 30 06:02:46 PM PDT 24
Finished Jul 30 06:02:47 PM PDT 24
Peak memory 196420 kb
Host smart-558b9f88-492c-48a2-ae84-5b8c7642b0ec
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364109864 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din_no_pullu
p_pulldown.2364109864
Directory /workspace/31.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_random_long_reg_writes_reg_reads.1859727142
Short name T511
Test name
Test status
Simulation time 624932539 ps
CPU time 2.2 seconds
Started Jul 30 06:02:51 PM PDT 24
Finished Jul 30 06:02:53 PM PDT 24
Peak memory 198588 kb
Host smart-3346b770-398f-410c-ba0a-91a221fcb9bd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859727142 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_ra
ndom_long_reg_writes_reg_reads.1859727142
Directory /workspace/31.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/31.gpio_smoke.2423223631
Short name T122
Test name
Test status
Simulation time 51555502 ps
CPU time 1.06 seconds
Started Jul 30 06:02:47 PM PDT 24
Finished Jul 30 06:02:48 PM PDT 24
Peak memory 197060 kb
Host smart-1a41d66f-b758-4459-8373-d21fd88ddb6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2423223631 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke.2423223631
Directory /workspace/31.gpio_smoke/latest

Test location /workspace/coverage/default/31.gpio_smoke_no_pullup_pulldown.3505898071
Short name T188
Test name
Test status
Simulation time 37997088 ps
CPU time 0.92 seconds
Started Jul 30 06:02:41 PM PDT 24
Finished Jul 30 06:02:43 PM PDT 24
Peak memory 196996 kb
Host smart-9ee7f07c-9e98-438b-b659-dbfb9ee5041b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505898071 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown.3505898071
Directory /workspace/31.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_stress_all.3468739901
Short name T7
Test name
Test status
Simulation time 10461167347 ps
CPU time 30.85 seconds
Started Jul 30 06:02:47 PM PDT 24
Finished Jul 30 06:03:18 PM PDT 24
Peak memory 198756 kb
Host smart-74211e0b-a4fc-49ae-b2f6-14bd7bff1b31
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468739901 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.
gpio_stress_all.3468739901
Directory /workspace/31.gpio_stress_all/latest

Test location /workspace/coverage/default/31.gpio_stress_all_with_rand_reset.3882355781
Short name T63
Test name
Test status
Simulation time 14577873386 ps
CPU time 347.46 seconds
Started Jul 30 06:02:44 PM PDT 24
Finished Jul 30 06:08:32 PM PDT 24
Peak memory 198812 kb
Host smart-4ff40049-8f7d-4328-8588-a26f31b15d99
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3882355781 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_stress_all_with_rand_reset.3882355781
Directory /workspace/31.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.gpio_alert_test.3260185030
Short name T260
Test name
Test status
Simulation time 48586847 ps
CPU time 0.56 seconds
Started Jul 30 06:02:45 PM PDT 24
Finished Jul 30 06:02:46 PM PDT 24
Peak memory 195356 kb
Host smart-5b06c0ba-a7ac-4026-ad29-f6b8bc791ac6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260185030 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_alert_test.3260185030
Directory /workspace/32.gpio_alert_test/latest

Test location /workspace/coverage/default/32.gpio_dout_din_regs_random_rw.2681487852
Short name T430
Test name
Test status
Simulation time 15167902 ps
CPU time 0.57 seconds
Started Jul 30 06:02:43 PM PDT 24
Finished Jul 30 06:02:44 PM PDT 24
Peak memory 195160 kb
Host smart-4d469019-9683-462f-806f-c1707e122248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2681487852 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_dout_din_regs_random_rw.2681487852
Directory /workspace/32.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/32.gpio_filter_stress.2198089693
Short name T456
Test name
Test status
Simulation time 1690650576 ps
CPU time 15.8 seconds
Started Jul 30 06:02:50 PM PDT 24
Finished Jul 30 06:03:06 PM PDT 24
Peak memory 197544 kb
Host smart-bffde85b-ba6b-4d88-b52b-ebb80efd4155
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198089693 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_filter_stre
ss.2198089693
Directory /workspace/32.gpio_filter_stress/latest

Test location /workspace/coverage/default/32.gpio_full_random.2954063975
Short name T28
Test name
Test status
Simulation time 83048717 ps
CPU time 0.95 seconds
Started Jul 30 06:02:44 PM PDT 24
Finished Jul 30 06:02:45 PM PDT 24
Peak memory 196584 kb
Host smart-1ba65e5b-4d0e-4324-8889-c3f6cdb41fd7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954063975 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_full_random.2954063975
Directory /workspace/32.gpio_full_random/latest

Test location /workspace/coverage/default/32.gpio_intr_rand_pgm.1490508888
Short name T294
Test name
Test status
Simulation time 199580842 ps
CPU time 1.33 seconds
Started Jul 30 06:02:54 PM PDT 24
Finished Jul 30 06:02:55 PM PDT 24
Peak memory 197480 kb
Host smart-e3a93435-a613-47ac-a93d-a2ec2cae15ca
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490508888 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_intr_rand_pgm.1490508888
Directory /workspace/32.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/32.gpio_intr_with_filter_rand_intr_event.649216568
Short name T530
Test name
Test status
Simulation time 127862298 ps
CPU time 1.49 seconds
Started Jul 30 06:02:50 PM PDT 24
Finished Jul 30 06:02:52 PM PDT 24
Peak memory 197524 kb
Host smart-a254ac18-7428-473e-801d-c69ae07293f2
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649216568 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 32.gpio_intr_with_filter_rand_intr_event.649216568
Directory /workspace/32.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/32.gpio_rand_intr_trigger.521613021
Short name T550
Test name
Test status
Simulation time 83661314 ps
CPU time 1.06 seconds
Started Jul 30 06:02:51 PM PDT 24
Finished Jul 30 06:02:53 PM PDT 24
Peak memory 196104 kb
Host smart-378194cc-d613-4292-ac40-81865b7b53c8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521613021 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_rand_intr_trigger.
521613021
Directory /workspace/32.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din.3527422917
Short name T191
Test name
Test status
Simulation time 35058594 ps
CPU time 0.95 seconds
Started Jul 30 06:02:49 PM PDT 24
Finished Jul 30 06:02:50 PM PDT 24
Peak memory 196580 kb
Host smart-cbda6989-d00f-477d-a0ba-c116b5b8f226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3527422917 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din.3527422917
Directory /workspace/32.gpio_random_dout_din/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din_no_pullup_pulldown.2435116324
Short name T438
Test name
Test status
Simulation time 35910591 ps
CPU time 1.08 seconds
Started Jul 30 06:02:56 PM PDT 24
Finished Jul 30 06:02:57 PM PDT 24
Peak memory 197104 kb
Host smart-14c2f7d4-e7a1-4c58-ba0b-af35f46cdf44
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435116324 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din_no_pullu
p_pulldown.2435116324
Directory /workspace/32.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_random_long_reg_writes_reg_reads.975590284
Short name T320
Test name
Test status
Simulation time 1245497712 ps
CPU time 3.74 seconds
Started Jul 30 06:02:53 PM PDT 24
Finished Jul 30 06:02:57 PM PDT 24
Peak memory 198612 kb
Host smart-f8af26c6-2dbc-408e-8b81-ec8b19791417
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975590284 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_ran
dom_long_reg_writes_reg_reads.975590284
Directory /workspace/32.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/32.gpio_smoke.1823909075
Short name T243
Test name
Test status
Simulation time 151733246 ps
CPU time 1.41 seconds
Started Jul 30 06:02:53 PM PDT 24
Finished Jul 30 06:02:54 PM PDT 24
Peak memory 197404 kb
Host smart-49765f75-ce39-4630-a454-f7773ba55f84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1823909075 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke.1823909075
Directory /workspace/32.gpio_smoke/latest

Test location /workspace/coverage/default/32.gpio_smoke_no_pullup_pulldown.3407279825
Short name T280
Test name
Test status
Simulation time 35332235 ps
CPU time 0.87 seconds
Started Jul 30 06:02:46 PM PDT 24
Finished Jul 30 06:02:47 PM PDT 24
Peak memory 196820 kb
Host smart-9f6e8282-bf62-4ac3-a9f0-539871f305f9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407279825 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown.3407279825
Directory /workspace/32.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_stress_all.287384517
Short name T219
Test name
Test status
Simulation time 2739074143 ps
CPU time 42.01 seconds
Started Jul 30 06:02:39 PM PDT 24
Finished Jul 30 06:03:21 PM PDT 24
Peak memory 198752 kb
Host smart-dea40020-c849-4bda-a33d-0c06dc9eefd8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287384517 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.g
pio_stress_all.287384517
Directory /workspace/32.gpio_stress_all/latest

Test location /workspace/coverage/default/33.gpio_alert_test.644579380
Short name T648
Test name
Test status
Simulation time 190473062 ps
CPU time 0.57 seconds
Started Jul 30 06:02:49 PM PDT 24
Finished Jul 30 06:02:50 PM PDT 24
Peak memory 194472 kb
Host smart-87424d88-93a3-4eaa-b1a6-e17445b1468e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644579380 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_alert_test.644579380
Directory /workspace/33.gpio_alert_test/latest

Test location /workspace/coverage/default/33.gpio_dout_din_regs_random_rw.139692981
Short name T690
Test name
Test status
Simulation time 55252654 ps
CPU time 0.88 seconds
Started Jul 30 06:02:45 PM PDT 24
Finished Jul 30 06:02:46 PM PDT 24
Peak memory 196260 kb
Host smart-acf2bebf-341a-4bb5-9d49-6bc9d3b144dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=139692981 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_dout_din_regs_random_rw.139692981
Directory /workspace/33.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/33.gpio_filter_stress.2375370999
Short name T655
Test name
Test status
Simulation time 143319174 ps
CPU time 7.39 seconds
Started Jul 30 06:02:46 PM PDT 24
Finished Jul 30 06:02:53 PM PDT 24
Peak memory 197620 kb
Host smart-a1995c86-65a0-4b7e-a2ad-d6e3dbcb8703
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375370999 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_filter_stre
ss.2375370999
Directory /workspace/33.gpio_filter_stress/latest

Test location /workspace/coverage/default/33.gpio_full_random.1286809494
Short name T13
Test name
Test status
Simulation time 29589558 ps
CPU time 0.74 seconds
Started Jul 30 06:02:53 PM PDT 24
Finished Jul 30 06:02:55 PM PDT 24
Peak memory 195132 kb
Host smart-374d9c69-0671-407c-8d61-543e07955f6a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286809494 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_full_random.1286809494
Directory /workspace/33.gpio_full_random/latest

Test location /workspace/coverage/default/33.gpio_intr_rand_pgm.364532158
Short name T288
Test name
Test status
Simulation time 33135994 ps
CPU time 1.11 seconds
Started Jul 30 06:02:48 PM PDT 24
Finished Jul 30 06:02:49 PM PDT 24
Peak memory 196636 kb
Host smart-64d7bce5-2556-4f65-ae47-f1a8aa358ab1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364532158 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_intr_rand_pgm.364532158
Directory /workspace/33.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/33.gpio_intr_with_filter_rand_intr_event.3760442810
Short name T618
Test name
Test status
Simulation time 151075927 ps
CPU time 2.85 seconds
Started Jul 30 06:02:52 PM PDT 24
Finished Jul 30 06:02:55 PM PDT 24
Peak memory 198628 kb
Host smart-4b60f8c9-0251-4274-9f20-774fdc8f29d2
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760442810 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 33.gpio_intr_with_filter_rand_intr_event.3760442810
Directory /workspace/33.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/33.gpio_rand_intr_trigger.1198779668
Short name T501
Test name
Test status
Simulation time 75591954 ps
CPU time 1.89 seconds
Started Jul 30 06:02:45 PM PDT 24
Finished Jul 30 06:02:47 PM PDT 24
Peak memory 197288 kb
Host smart-514173da-dcc3-47e6-8078-6463165b6a0f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198779668 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_rand_intr_trigger
.1198779668
Directory /workspace/33.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din.2046401985
Short name T687
Test name
Test status
Simulation time 126803260 ps
CPU time 0.96 seconds
Started Jul 30 06:02:50 PM PDT 24
Finished Jul 30 06:02:51 PM PDT 24
Peak memory 196336 kb
Host smart-add75a3a-9acd-4547-a0cf-8aba78e985b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2046401985 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din.2046401985
Directory /workspace/33.gpio_random_dout_din/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din_no_pullup_pulldown.4154629388
Short name T462
Test name
Test status
Simulation time 21921333 ps
CPU time 0.9 seconds
Started Jul 30 06:02:48 PM PDT 24
Finished Jul 30 06:02:49 PM PDT 24
Peak memory 197344 kb
Host smart-fd9a6369-45be-4103-942b-58338cc1bff3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154629388 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din_no_pullu
p_pulldown.4154629388
Directory /workspace/33.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_random_long_reg_writes_reg_reads.1193042524
Short name T504
Test name
Test status
Simulation time 484460042 ps
CPU time 5.69 seconds
Started Jul 30 06:02:51 PM PDT 24
Finished Jul 30 06:02:56 PM PDT 24
Peak memory 198348 kb
Host smart-eed67a45-de9b-4131-b990-f661324f01c3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193042524 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_ra
ndom_long_reg_writes_reg_reads.1193042524
Directory /workspace/33.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/33.gpio_smoke.1285238631
Short name T332
Test name
Test status
Simulation time 101327958 ps
CPU time 0.72 seconds
Started Jul 30 06:02:52 PM PDT 24
Finished Jul 30 06:02:53 PM PDT 24
Peak memory 195812 kb
Host smart-7fc1b1c6-5276-4f57-8794-d5045f384a17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1285238631 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke.1285238631
Directory /workspace/33.gpio_smoke/latest

Test location /workspace/coverage/default/33.gpio_smoke_no_pullup_pulldown.1016761995
Short name T263
Test name
Test status
Simulation time 343340982 ps
CPU time 1.54 seconds
Started Jul 30 06:02:48 PM PDT 24
Finished Jul 30 06:02:50 PM PDT 24
Peak memory 198608 kb
Host smart-51a145b2-83f5-4c77-96c1-08b6c0180bf0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016761995 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown.1016761995
Directory /workspace/33.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_stress_all.690689281
Short name T555
Test name
Test status
Simulation time 4220850854 ps
CPU time 108.89 seconds
Started Jul 30 06:02:45 PM PDT 24
Finished Jul 30 06:04:34 PM PDT 24
Peak memory 198672 kb
Host smart-09c6839c-b9a2-464d-b87d-90455255ec0e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690689281 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.g
pio_stress_all.690689281
Directory /workspace/33.gpio_stress_all/latest

Test location /workspace/coverage/default/33.gpio_stress_all_with_rand_reset.2072447548
Short name T59
Test name
Test status
Simulation time 63138980931 ps
CPU time 658.11 seconds
Started Jul 30 06:02:54 PM PDT 24
Finished Jul 30 06:13:53 PM PDT 24
Peak memory 198900 kb
Host smart-eb703ecc-e3f2-4346-a332-0701a074fd6c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2072447548 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_stress_all_with_rand_reset.2072447548
Directory /workspace/33.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.gpio_alert_test.3851719016
Short name T596
Test name
Test status
Simulation time 12202959 ps
CPU time 0.56 seconds
Started Jul 30 06:02:53 PM PDT 24
Finished Jul 30 06:02:54 PM PDT 24
Peak memory 195472 kb
Host smart-a443b4fc-bafe-41e2-96ec-5c737e588814
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851719016 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_alert_test.3851719016
Directory /workspace/34.gpio_alert_test/latest

Test location /workspace/coverage/default/34.gpio_dout_din_regs_random_rw.1888482879
Short name T190
Test name
Test status
Simulation time 16486283 ps
CPU time 0.66 seconds
Started Jul 30 06:02:57 PM PDT 24
Finished Jul 30 06:02:58 PM PDT 24
Peak memory 194536 kb
Host smart-0ecfe714-2bc4-454a-a920-68063dcaa4f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1888482879 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_dout_din_regs_random_rw.1888482879
Directory /workspace/34.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/34.gpio_filter_stress.2589139893
Short name T604
Test name
Test status
Simulation time 4907515050 ps
CPU time 28.21 seconds
Started Jul 30 06:02:53 PM PDT 24
Finished Jul 30 06:03:22 PM PDT 24
Peak memory 197600 kb
Host smart-d4602f83-5072-4c03-b648-b9f060fecdb1
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589139893 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_filter_stre
ss.2589139893
Directory /workspace/34.gpio_filter_stress/latest

Test location /workspace/coverage/default/34.gpio_full_random.259274884
Short name T231
Test name
Test status
Simulation time 356455191 ps
CPU time 0.83 seconds
Started Jul 30 06:02:52 PM PDT 24
Finished Jul 30 06:02:54 PM PDT 24
Peak memory 197000 kb
Host smart-ff421cc5-2cd6-4c0c-83de-e39b31887d79
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259274884 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_full_random.259274884
Directory /workspace/34.gpio_full_random/latest

Test location /workspace/coverage/default/34.gpio_intr_rand_pgm.2369467709
Short name T223
Test name
Test status
Simulation time 96093950 ps
CPU time 0.89 seconds
Started Jul 30 06:02:55 PM PDT 24
Finished Jul 30 06:02:56 PM PDT 24
Peak memory 196184 kb
Host smart-aba2f05a-e522-44ef-a3ec-4990dadb4f67
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369467709 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_intr_rand_pgm.2369467709
Directory /workspace/34.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/34.gpio_intr_with_filter_rand_intr_event.3660806035
Short name T366
Test name
Test status
Simulation time 77493130 ps
CPU time 3.21 seconds
Started Jul 30 06:02:50 PM PDT 24
Finished Jul 30 06:02:54 PM PDT 24
Peak memory 198768 kb
Host smart-3b43dc4e-f19c-4bef-b4f7-bf7a89f71c25
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660806035 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.gpio_intr_with_filter_rand_intr_event.3660806035
Directory /workspace/34.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/34.gpio_rand_intr_trigger.3853336999
Short name T225
Test name
Test status
Simulation time 506737332 ps
CPU time 2.99 seconds
Started Jul 30 06:02:53 PM PDT 24
Finished Jul 30 06:02:56 PM PDT 24
Peak memory 198656 kb
Host smart-1eaef208-0eeb-4ad0-8a61-63df306d4b4d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853336999 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_rand_intr_trigger
.3853336999
Directory /workspace/34.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din.1287503510
Short name T679
Test name
Test status
Simulation time 333806707 ps
CPU time 1.06 seconds
Started Jul 30 06:02:52 PM PDT 24
Finished Jul 30 06:02:54 PM PDT 24
Peak memory 196368 kb
Host smart-5c66c390-d16d-4043-9b79-d8aab0736631
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1287503510 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din.1287503510
Directory /workspace/34.gpio_random_dout_din/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din_no_pullup_pulldown.1458546114
Short name T165
Test name
Test status
Simulation time 15922106 ps
CPU time 0.69 seconds
Started Jul 30 06:02:52 PM PDT 24
Finished Jul 30 06:02:53 PM PDT 24
Peak memory 195940 kb
Host smart-d189f1dc-e2b3-4423-96aa-c7796274ec22
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458546114 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din_no_pullu
p_pulldown.1458546114
Directory /workspace/34.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_random_long_reg_writes_reg_reads.607560929
Short name T232
Test name
Test status
Simulation time 401362151 ps
CPU time 2.04 seconds
Started Jul 30 06:02:53 PM PDT 24
Finished Jul 30 06:02:55 PM PDT 24
Peak memory 198516 kb
Host smart-4da21dc1-dadb-49a0-9fc6-39d43ad8eca5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607560929 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_ran
dom_long_reg_writes_reg_reads.607560929
Directory /workspace/34.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/34.gpio_smoke.208561361
Short name T608
Test name
Test status
Simulation time 41373900 ps
CPU time 1.13 seconds
Started Jul 30 06:02:46 PM PDT 24
Finished Jul 30 06:02:48 PM PDT 24
Peak memory 196836 kb
Host smart-26ce723a-a566-41e4-bb2f-69bbd2bf8ad2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=208561361 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke.208561361
Directory /workspace/34.gpio_smoke/latest

Test location /workspace/coverage/default/34.gpio_smoke_no_pullup_pulldown.3154987893
Short name T17
Test name
Test status
Simulation time 65544425 ps
CPU time 0.84 seconds
Started Jul 30 06:02:52 PM PDT 24
Finished Jul 30 06:02:53 PM PDT 24
Peak memory 195880 kb
Host smart-e986187d-7dc5-4cc9-af9a-745eaa4593cf
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154987893 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown.3154987893
Directory /workspace/34.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_stress_all.1871757251
Short name T111
Test name
Test status
Simulation time 13688145049 ps
CPU time 95.7 seconds
Started Jul 30 06:02:52 PM PDT 24
Finished Jul 30 06:04:28 PM PDT 24
Peak memory 198756 kb
Host smart-30ca1707-b0f1-495f-b556-6540d1cae784
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871757251 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.
gpio_stress_all.1871757251
Directory /workspace/34.gpio_stress_all/latest

Test location /workspace/coverage/default/34.gpio_stress_all_with_rand_reset.3602681290
Short name T62
Test name
Test status
Simulation time 272737432406 ps
CPU time 1620.68 seconds
Started Jul 30 06:02:51 PM PDT 24
Finished Jul 30 06:29:53 PM PDT 24
Peak memory 198908 kb
Host smart-2a5215f1-8596-41da-9d67-47bbc6e040c6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3602681290 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_stress_all_with_rand_reset.3602681290
Directory /workspace/34.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.gpio_alert_test.4085445896
Short name T452
Test name
Test status
Simulation time 47876103 ps
CPU time 0.57 seconds
Started Jul 30 06:02:52 PM PDT 24
Finished Jul 30 06:02:53 PM PDT 24
Peak memory 195416 kb
Host smart-7297bfa9-8e4a-42c5-aff4-db61b9b9768d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085445896 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_alert_test.4085445896
Directory /workspace/35.gpio_alert_test/latest

Test location /workspace/coverage/default/35.gpio_dout_din_regs_random_rw.1804512104
Short name T185
Test name
Test status
Simulation time 121981916 ps
CPU time 0.84 seconds
Started Jul 30 06:02:47 PM PDT 24
Finished Jul 30 06:02:48 PM PDT 24
Peak memory 196436 kb
Host smart-f5723481-064e-45ca-a913-9cc776476ad9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1804512104 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_dout_din_regs_random_rw.1804512104
Directory /workspace/35.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/35.gpio_filter_stress.3440984488
Short name T130
Test name
Test status
Simulation time 2131212686 ps
CPU time 7.28 seconds
Started Jul 30 06:02:51 PM PDT 24
Finished Jul 30 06:02:59 PM PDT 24
Peak memory 196848 kb
Host smart-302fd90b-54f2-4ded-936e-5f3c9ed7620b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440984488 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_filter_stre
ss.3440984488
Directory /workspace/35.gpio_filter_stress/latest

Test location /workspace/coverage/default/35.gpio_full_random.464527889
Short name T709
Test name
Test status
Simulation time 270828956 ps
CPU time 0.88 seconds
Started Jul 30 06:02:51 PM PDT 24
Finished Jul 30 06:02:53 PM PDT 24
Peak memory 196544 kb
Host smart-4f5ac3d0-3364-4a81-9f1f-8f6e4455dca3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464527889 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_full_random.464527889
Directory /workspace/35.gpio_full_random/latest

Test location /workspace/coverage/default/35.gpio_intr_rand_pgm.1803486484
Short name T337
Test name
Test status
Simulation time 31351820 ps
CPU time 0.78 seconds
Started Jul 30 06:02:44 PM PDT 24
Finished Jul 30 06:02:45 PM PDT 24
Peak memory 194880 kb
Host smart-6f630766-5f16-41f7-8a74-2fc80d776e6a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803486484 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_intr_rand_pgm.1803486484
Directory /workspace/35.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/35.gpio_intr_with_filter_rand_intr_event.2953508911
Short name T259
Test name
Test status
Simulation time 71209409 ps
CPU time 1.42 seconds
Started Jul 30 06:02:48 PM PDT 24
Finished Jul 30 06:02:50 PM PDT 24
Peak memory 196968 kb
Host smart-2d9ee025-93d3-4d8a-b9a5-0de016171799
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953508911 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 35.gpio_intr_with_filter_rand_intr_event.2953508911
Directory /workspace/35.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/35.gpio_rand_intr_trigger.236787970
Short name T454
Test name
Test status
Simulation time 643821509 ps
CPU time 3.65 seconds
Started Jul 30 06:02:52 PM PDT 24
Finished Jul 30 06:02:56 PM PDT 24
Peak memory 197916 kb
Host smart-38620a7e-a3e5-4928-b93b-eb0bd39706f7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236787970 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_rand_intr_trigger.
236787970
Directory /workspace/35.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din.3839697259
Short name T433
Test name
Test status
Simulation time 25719980 ps
CPU time 0.75 seconds
Started Jul 30 06:02:53 PM PDT 24
Finished Jul 30 06:02:54 PM PDT 24
Peak memory 196624 kb
Host smart-dd5d2fb5-c76b-48e1-892f-705128178518
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3839697259 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din.3839697259
Directory /workspace/35.gpio_random_dout_din/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din_no_pullup_pulldown.3622128069
Short name T482
Test name
Test status
Simulation time 47137668 ps
CPU time 0.67 seconds
Started Jul 30 06:02:52 PM PDT 24
Finished Jul 30 06:02:53 PM PDT 24
Peak memory 194752 kb
Host smart-19248c14-06f1-4f7b-b2b3-d2f64bcae831
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622128069 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din_no_pullu
p_pulldown.3622128069
Directory /workspace/35.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_random_long_reg_writes_reg_reads.531839335
Short name T489
Test name
Test status
Simulation time 254608418 ps
CPU time 3.58 seconds
Started Jul 30 06:02:53 PM PDT 24
Finished Jul 30 06:02:57 PM PDT 24
Peak memory 198592 kb
Host smart-0347345e-f4ed-40d6-b301-73f9eb383ee1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531839335 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_ran
dom_long_reg_writes_reg_reads.531839335
Directory /workspace/35.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/35.gpio_smoke.1919678473
Short name T584
Test name
Test status
Simulation time 35908741 ps
CPU time 1.09 seconds
Started Jul 30 06:02:51 PM PDT 24
Finished Jul 30 06:02:53 PM PDT 24
Peak memory 196216 kb
Host smart-b2e7f77d-4ef7-459e-b43a-53430972b3ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919678473 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke.1919678473
Directory /workspace/35.gpio_smoke/latest

Test location /workspace/coverage/default/35.gpio_smoke_no_pullup_pulldown.3053907975
Short name T496
Test name
Test status
Simulation time 157513055 ps
CPU time 0.89 seconds
Started Jul 30 06:02:46 PM PDT 24
Finished Jul 30 06:02:47 PM PDT 24
Peak memory 196724 kb
Host smart-56878052-1729-4b5f-8676-88a2ab0fec37
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053907975 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown.3053907975
Directory /workspace/35.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_stress_all.1117778211
Short name T64
Test name
Test status
Simulation time 3868182289 ps
CPU time 70.62 seconds
Started Jul 30 06:02:52 PM PDT 24
Finished Jul 30 06:04:03 PM PDT 24
Peak memory 198644 kb
Host smart-07a4e875-c265-41da-8e77-fe9d04535ece
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117778211 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.
gpio_stress_all.1117778211
Directory /workspace/35.gpio_stress_all/latest

Test location /workspace/coverage/default/36.gpio_alert_test.4215958479
Short name T415
Test name
Test status
Simulation time 12950876 ps
CPU time 0.64 seconds
Started Jul 30 06:02:54 PM PDT 24
Finished Jul 30 06:02:55 PM PDT 24
Peak memory 194540 kb
Host smart-a74dbe8c-7137-4d1a-972c-ea8ed817e0ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215958479 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_alert_test.4215958479
Directory /workspace/36.gpio_alert_test/latest

Test location /workspace/coverage/default/36.gpio_dout_din_regs_random_rw.110729661
Short name T601
Test name
Test status
Simulation time 85349516 ps
CPU time 0.77 seconds
Started Jul 30 06:02:51 PM PDT 24
Finished Jul 30 06:02:52 PM PDT 24
Peak memory 195892 kb
Host smart-bba589e6-11a8-4780-a168-dae1fefd131a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110729661 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_dout_din_regs_random_rw.110729661
Directory /workspace/36.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/36.gpio_filter_stress.2006428471
Short name T519
Test name
Test status
Simulation time 275816282 ps
CPU time 6.83 seconds
Started Jul 30 06:02:53 PM PDT 24
Finished Jul 30 06:03:00 PM PDT 24
Peak memory 196832 kb
Host smart-93607ae8-2551-4870-8a64-3acf8cc000bf
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006428471 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_filter_stre
ss.2006428471
Directory /workspace/36.gpio_filter_stress/latest

Test location /workspace/coverage/default/36.gpio_full_random.2219249116
Short name T307
Test name
Test status
Simulation time 157924288 ps
CPU time 1.12 seconds
Started Jul 30 06:02:50 PM PDT 24
Finished Jul 30 06:02:52 PM PDT 24
Peak memory 196984 kb
Host smart-134911fe-1200-49f9-97dc-cb571d2f9b28
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219249116 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_full_random.2219249116
Directory /workspace/36.gpio_full_random/latest

Test location /workspace/coverage/default/36.gpio_intr_rand_pgm.1764746130
Short name T613
Test name
Test status
Simulation time 25603723 ps
CPU time 0.82 seconds
Started Jul 30 06:02:42 PM PDT 24
Finished Jul 30 06:02:43 PM PDT 24
Peak memory 195948 kb
Host smart-6149c84a-8019-4d43-98f1-0f690d43aaf0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764746130 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_intr_rand_pgm.1764746130
Directory /workspace/36.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/36.gpio_intr_with_filter_rand_intr_event.1042966993
Short name T641
Test name
Test status
Simulation time 64512225 ps
CPU time 2.31 seconds
Started Jul 30 06:02:55 PM PDT 24
Finished Jul 30 06:02:58 PM PDT 24
Peak memory 198736 kb
Host smart-7dfbd7f0-5c8b-43a1-abf5-134257999cb4
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042966993 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 36.gpio_intr_with_filter_rand_intr_event.1042966993
Directory /workspace/36.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/36.gpio_rand_intr_trigger.3531627611
Short name T245
Test name
Test status
Simulation time 93419597 ps
CPU time 0.87 seconds
Started Jul 30 06:02:49 PM PDT 24
Finished Jul 30 06:02:50 PM PDT 24
Peak memory 195020 kb
Host smart-8c7ed310-ba36-4d68-bc7a-42ba685df852
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531627611 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_rand_intr_trigger
.3531627611
Directory /workspace/36.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din.3269374221
Short name T435
Test name
Test status
Simulation time 168049860 ps
CPU time 1.22 seconds
Started Jul 30 06:02:57 PM PDT 24
Finished Jul 30 06:02:58 PM PDT 24
Peak memory 197584 kb
Host smart-d015504b-16ef-4aa7-bfda-0433829a7984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3269374221 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din.3269374221
Directory /workspace/36.gpio_random_dout_din/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din_no_pullup_pulldown.2028329093
Short name T167
Test name
Test status
Simulation time 35926999 ps
CPU time 0.94 seconds
Started Jul 30 06:02:53 PM PDT 24
Finished Jul 30 06:02:54 PM PDT 24
Peak memory 196572 kb
Host smart-907156ed-f270-49c2-925b-fc31878bea0a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028329093 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din_no_pullu
p_pulldown.2028329093
Directory /workspace/36.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_random_long_reg_writes_reg_reads.650737161
Short name T634
Test name
Test status
Simulation time 260084922 ps
CPU time 1.44 seconds
Started Jul 30 06:02:55 PM PDT 24
Finished Jul 30 06:02:56 PM PDT 24
Peak memory 198588 kb
Host smart-6f59232b-a90f-48c7-82e4-67cc5c196fbe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650737161 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_ran
dom_long_reg_writes_reg_reads.650737161
Directory /workspace/36.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/36.gpio_smoke.3755410708
Short name T686
Test name
Test status
Simulation time 41243036 ps
CPU time 0.88 seconds
Started Jul 30 06:02:55 PM PDT 24
Finished Jul 30 06:02:56 PM PDT 24
Peak memory 195956 kb
Host smart-2d6d5e5c-e8fb-4b02-9a63-353c209f4a95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3755410708 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke.3755410708
Directory /workspace/36.gpio_smoke/latest

Test location /workspace/coverage/default/36.gpio_smoke_no_pullup_pulldown.2614459552
Short name T420
Test name
Test status
Simulation time 97599738 ps
CPU time 0.71 seconds
Started Jul 30 06:02:51 PM PDT 24
Finished Jul 30 06:02:53 PM PDT 24
Peak memory 194816 kb
Host smart-a6453856-7820-498b-899b-90b08cc7c312
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614459552 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown.2614459552
Directory /workspace/36.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_stress_all.1831695330
Short name T12
Test name
Test status
Simulation time 30795772557 ps
CPU time 48.45 seconds
Started Jul 30 06:02:50 PM PDT 24
Finished Jul 30 06:03:39 PM PDT 24
Peak memory 198856 kb
Host smart-f054dca9-c0cc-4920-8d8e-67e6799fb60d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831695330 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.
gpio_stress_all.1831695330
Directory /workspace/36.gpio_stress_all/latest

Test location /workspace/coverage/default/36.gpio_stress_all_with_rand_reset.4109471208
Short name T30
Test name
Test status
Simulation time 58084948456 ps
CPU time 979.43 seconds
Started Jul 30 06:02:52 PM PDT 24
Finished Jul 30 06:19:12 PM PDT 24
Peak memory 198832 kb
Host smart-5038e1bd-9859-4fa5-82f6-27e583c24dc5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4109471208 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_stress_all_with_rand_reset.4109471208
Directory /workspace/36.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.gpio_alert_test.2483399449
Short name T233
Test name
Test status
Simulation time 14915240 ps
CPU time 0.61 seconds
Started Jul 30 06:02:53 PM PDT 24
Finished Jul 30 06:02:54 PM PDT 24
Peak memory 194728 kb
Host smart-dcf77901-7a60-40a9-8090-ea816e035ad8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483399449 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_alert_test.2483399449
Directory /workspace/37.gpio_alert_test/latest

Test location /workspace/coverage/default/37.gpio_dout_din_regs_random_rw.2922504078
Short name T673
Test name
Test status
Simulation time 17607589 ps
CPU time 0.66 seconds
Started Jul 30 06:02:52 PM PDT 24
Finished Jul 30 06:02:53 PM PDT 24
Peak memory 194524 kb
Host smart-04826cf6-0553-4d47-bc8e-847adb4df6e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2922504078 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_dout_din_regs_random_rw.2922504078
Directory /workspace/37.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/37.gpio_filter_stress.2694812316
Short name T253
Test name
Test status
Simulation time 312208849 ps
CPU time 8.69 seconds
Started Jul 30 06:02:56 PM PDT 24
Finished Jul 30 06:03:05 PM PDT 24
Peak memory 197140 kb
Host smart-111898b6-fd42-4995-9559-8116c0606840
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694812316 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_filter_stre
ss.2694812316
Directory /workspace/37.gpio_filter_stress/latest

Test location /workspace/coverage/default/37.gpio_full_random.4251742555
Short name T5
Test name
Test status
Simulation time 74644029 ps
CPU time 0.95 seconds
Started Jul 30 06:02:53 PM PDT 24
Finished Jul 30 06:02:55 PM PDT 24
Peak memory 196488 kb
Host smart-a75d0783-c071-4aa0-9afb-85d58842778d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251742555 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_full_random.4251742555
Directory /workspace/37.gpio_full_random/latest

Test location /workspace/coverage/default/37.gpio_intr_rand_pgm.1983207773
Short name T240
Test name
Test status
Simulation time 478232682 ps
CPU time 1.08 seconds
Started Jul 30 06:02:46 PM PDT 24
Finished Jul 30 06:02:47 PM PDT 24
Peak memory 196440 kb
Host smart-51faf67e-c4e0-4348-9ec1-876928b123ea
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983207773 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_intr_rand_pgm.1983207773
Directory /workspace/37.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/37.gpio_intr_with_filter_rand_intr_event.514627680
Short name T356
Test name
Test status
Simulation time 197273057 ps
CPU time 2.03 seconds
Started Jul 30 06:02:53 PM PDT 24
Finished Jul 30 06:02:56 PM PDT 24
Peak memory 198696 kb
Host smart-66d26a32-5829-4e3d-ba4a-d64fbb1bdb7f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514627680 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 37.gpio_intr_with_filter_rand_intr_event.514627680
Directory /workspace/37.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/37.gpio_rand_intr_trigger.1055135605
Short name T127
Test name
Test status
Simulation time 433614664 ps
CPU time 2.64 seconds
Started Jul 30 06:02:53 PM PDT 24
Finished Jul 30 06:02:56 PM PDT 24
Peak memory 197104 kb
Host smart-b8368aff-6435-4fae-9055-83d58074a049
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055135605 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_rand_intr_trigger
.1055135605
Directory /workspace/37.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din.3672199030
Short name T208
Test name
Test status
Simulation time 21269315 ps
CPU time 0.68 seconds
Started Jul 30 06:02:54 PM PDT 24
Finished Jul 30 06:02:55 PM PDT 24
Peak memory 194864 kb
Host smart-6e7399a5-2729-40e5-bf2e-80114f312fa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672199030 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din.3672199030
Directory /workspace/37.gpio_random_dout_din/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din_no_pullup_pulldown.3178151140
Short name T204
Test name
Test status
Simulation time 101432150 ps
CPU time 1.19 seconds
Started Jul 30 06:02:54 PM PDT 24
Finished Jul 30 06:02:55 PM PDT 24
Peak memory 196736 kb
Host smart-0b913142-2a50-4252-a8ce-dd17eb99073e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178151140 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din_no_pullu
p_pulldown.3178151140
Directory /workspace/37.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_random_long_reg_writes_reg_reads.1394505629
Short name T264
Test name
Test status
Simulation time 775496828 ps
CPU time 4.79 seconds
Started Jul 30 06:02:49 PM PDT 24
Finished Jul 30 06:02:54 PM PDT 24
Peak memory 198536 kb
Host smart-7a953adf-f46e-4d75-b55d-1cc33c1084ee
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394505629 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_ra
ndom_long_reg_writes_reg_reads.1394505629
Directory /workspace/37.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/37.gpio_smoke.4258171526
Short name T354
Test name
Test status
Simulation time 300272033 ps
CPU time 1.01 seconds
Started Jul 30 06:02:53 PM PDT 24
Finished Jul 30 06:02:55 PM PDT 24
Peak memory 196856 kb
Host smart-e8d6b836-c22d-416d-9897-d96b08b844e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4258171526 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke.4258171526
Directory /workspace/37.gpio_smoke/latest

Test location /workspace/coverage/default/37.gpio_smoke_no_pullup_pulldown.1717227892
Short name T257
Test name
Test status
Simulation time 105207234 ps
CPU time 1.27 seconds
Started Jul 30 06:02:52 PM PDT 24
Finished Jul 30 06:02:54 PM PDT 24
Peak memory 197284 kb
Host smart-0d75c54e-5a4e-4355-b24b-515b918f258d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717227892 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown.1717227892
Directory /workspace/37.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_stress_all.2399983385
Short name T340
Test name
Test status
Simulation time 8687611061 ps
CPU time 59.21 seconds
Started Jul 30 06:02:53 PM PDT 24
Finished Jul 30 06:03:53 PM PDT 24
Peak memory 198760 kb
Host smart-51b7b1c4-2376-4af5-8e66-eda60bac30bd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399983385 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.
gpio_stress_all.2399983385
Directory /workspace/37.gpio_stress_all/latest

Test location /workspace/coverage/default/37.gpio_stress_all_with_rand_reset.2756114955
Short name T593
Test name
Test status
Simulation time 30994325772 ps
CPU time 568.7 seconds
Started Jul 30 06:02:47 PM PDT 24
Finished Jul 30 06:12:16 PM PDT 24
Peak memory 198896 kb
Host smart-e11e09aa-dbc7-4e07-aada-3c5c9ac7b3fa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2756114955 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_stress_all_with_rand_reset.2756114955
Directory /workspace/37.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.gpio_alert_test.418035521
Short name T404
Test name
Test status
Simulation time 14863967 ps
CPU time 0.59 seconds
Started Jul 30 06:02:55 PM PDT 24
Finished Jul 30 06:02:56 PM PDT 24
Peak memory 194112 kb
Host smart-e63a8652-1d58-425b-b61e-9aaef029fde4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418035521 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_alert_test.418035521
Directory /workspace/38.gpio_alert_test/latest

Test location /workspace/coverage/default/38.gpio_dout_din_regs_random_rw.1344181041
Short name T463
Test name
Test status
Simulation time 140971401 ps
CPU time 0.85 seconds
Started Jul 30 06:02:43 PM PDT 24
Finished Jul 30 06:02:44 PM PDT 24
Peak memory 196012 kb
Host smart-4ee80866-f3f7-43eb-8432-cdd90de4f0e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1344181041 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_dout_din_regs_random_rw.1344181041
Directory /workspace/38.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/38.gpio_filter_stress.1607921758
Short name T315
Test name
Test status
Simulation time 5957764937 ps
CPU time 26.07 seconds
Started Jul 30 06:02:47 PM PDT 24
Finished Jul 30 06:03:14 PM PDT 24
Peak memory 197596 kb
Host smart-e47a62a8-8d95-40f7-9663-624cdf547eb4
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607921758 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_filter_stre
ss.1607921758
Directory /workspace/38.gpio_filter_stress/latest

Test location /workspace/coverage/default/38.gpio_full_random.3184052410
Short name T607
Test name
Test status
Simulation time 671645717 ps
CPU time 1.14 seconds
Started Jul 30 06:02:47 PM PDT 24
Finished Jul 30 06:02:48 PM PDT 24
Peak memory 198612 kb
Host smart-d92d4576-b288-433a-ad2c-4edbc25553ae
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184052410 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_full_random.3184052410
Directory /workspace/38.gpio_full_random/latest

Test location /workspace/coverage/default/38.gpio_intr_rand_pgm.4032878721
Short name T507
Test name
Test status
Simulation time 18213728 ps
CPU time 0.65 seconds
Started Jul 30 06:02:50 PM PDT 24
Finished Jul 30 06:02:50 PM PDT 24
Peak memory 194752 kb
Host smart-9c8ae611-c132-4b5a-b889-600739490c52
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032878721 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_intr_rand_pgm.4032878721
Directory /workspace/38.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/38.gpio_intr_with_filter_rand_intr_event.3410388867
Short name T494
Test name
Test status
Simulation time 250950223 ps
CPU time 2.84 seconds
Started Jul 30 06:02:55 PM PDT 24
Finished Jul 30 06:02:58 PM PDT 24
Peak memory 198620 kb
Host smart-086c4f15-acbe-40c1-ad0f-36f69929430d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410388867 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 38.gpio_intr_with_filter_rand_intr_event.3410388867
Directory /workspace/38.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/38.gpio_rand_intr_trigger.4122860548
Short name T318
Test name
Test status
Simulation time 476866140 ps
CPU time 2.53 seconds
Started Jul 30 06:02:47 PM PDT 24
Finished Jul 30 06:02:49 PM PDT 24
Peak memory 198624 kb
Host smart-93f49c69-f7a1-4745-a729-e8484161e7df
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122860548 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_rand_intr_trigger
.4122860548
Directory /workspace/38.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din.197913415
Short name T353
Test name
Test status
Simulation time 57423024 ps
CPU time 0.71 seconds
Started Jul 30 06:02:51 PM PDT 24
Finished Jul 30 06:02:52 PM PDT 24
Peak memory 195872 kb
Host smart-fd60a398-d4d4-481f-ac36-b1ade5d56eca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=197913415 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din.197913415
Directory /workspace/38.gpio_random_dout_din/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din_no_pullup_pulldown.3362350740
Short name T115
Test name
Test status
Simulation time 192240695 ps
CPU time 1.13 seconds
Started Jul 30 06:02:51 PM PDT 24
Finished Jul 30 06:02:52 PM PDT 24
Peak memory 197268 kb
Host smart-8193f7fc-7209-4c96-8c68-6fd46ff4f546
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362350740 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din_no_pullu
p_pulldown.3362350740
Directory /workspace/38.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_random_long_reg_writes_reg_reads.153765455
Short name T344
Test name
Test status
Simulation time 456620325 ps
CPU time 3.92 seconds
Started Jul 30 06:02:47 PM PDT 24
Finished Jul 30 06:02:51 PM PDT 24
Peak memory 198576 kb
Host smart-70241897-89a1-4b52-992e-60bfff42466a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153765455 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_ran
dom_long_reg_writes_reg_reads.153765455
Directory /workspace/38.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/38.gpio_smoke.2352817104
Short name T293
Test name
Test status
Simulation time 274718137 ps
CPU time 1.26 seconds
Started Jul 30 06:02:52 PM PDT 24
Finished Jul 30 06:02:54 PM PDT 24
Peak memory 198536 kb
Host smart-59181064-2d15-4dd6-a830-ac7f1342968a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2352817104 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke.2352817104
Directory /workspace/38.gpio_smoke/latest

Test location /workspace/coverage/default/38.gpio_smoke_no_pullup_pulldown.3376813703
Short name T588
Test name
Test status
Simulation time 34033350 ps
CPU time 1.04 seconds
Started Jul 30 06:02:53 PM PDT 24
Finished Jul 30 06:02:55 PM PDT 24
Peak memory 196132 kb
Host smart-be90cbb7-cd7a-4205-8fd8-4c6825115ce0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376813703 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown.3376813703
Directory /workspace/38.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_stress_all.2596180130
Short name T537
Test name
Test status
Simulation time 29753942781 ps
CPU time 210.75 seconds
Started Jul 30 06:02:58 PM PDT 24
Finished Jul 30 06:06:34 PM PDT 24
Peak memory 198768 kb
Host smart-daaf2cf4-f648-4efd-98d1-b70cddf61441
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596180130 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.
gpio_stress_all.2596180130
Directory /workspace/38.gpio_stress_all/latest

Test location /workspace/coverage/default/39.gpio_alert_test.460608539
Short name T194
Test name
Test status
Simulation time 19518537 ps
CPU time 0.56 seconds
Started Jul 30 06:02:53 PM PDT 24
Finished Jul 30 06:02:54 PM PDT 24
Peak memory 194476 kb
Host smart-6f9f1498-3106-4826-bb06-11a9b58e4929
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460608539 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_alert_test.460608539
Directory /workspace/39.gpio_alert_test/latest

Test location /workspace/coverage/default/39.gpio_dout_din_regs_random_rw.2077548221
Short name T582
Test name
Test status
Simulation time 20680218 ps
CPU time 0.67 seconds
Started Jul 30 06:02:57 PM PDT 24
Finished Jul 30 06:02:58 PM PDT 24
Peak memory 194588 kb
Host smart-16602026-ec04-4f37-852b-c119a1c3387d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077548221 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_dout_din_regs_random_rw.2077548221
Directory /workspace/39.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/39.gpio_filter_stress.237236253
Short name T242
Test name
Test status
Simulation time 3256230643 ps
CPU time 27.05 seconds
Started Jul 30 06:02:58 PM PDT 24
Finished Jul 30 06:03:26 PM PDT 24
Peak memory 196152 kb
Host smart-f3d61522-fe0e-4662-855d-55c000a27043
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237236253 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_filter_stres
s.237236253
Directory /workspace/39.gpio_filter_stress/latest

Test location /workspace/coverage/default/39.gpio_full_random.2974863357
Short name T333
Test name
Test status
Simulation time 174408221 ps
CPU time 0.86 seconds
Started Jul 30 06:02:53 PM PDT 24
Finished Jul 30 06:02:54 PM PDT 24
Peak memory 197084 kb
Host smart-61a22153-7236-4394-a1eb-dffdb19679cb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974863357 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_full_random.2974863357
Directory /workspace/39.gpio_full_random/latest

Test location /workspace/coverage/default/39.gpio_intr_rand_pgm.509881085
Short name T220
Test name
Test status
Simulation time 114305753 ps
CPU time 1.55 seconds
Started Jul 30 06:02:52 PM PDT 24
Finished Jul 30 06:02:54 PM PDT 24
Peak memory 197572 kb
Host smart-0adde30c-ea65-486e-8aec-8c068a603525
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509881085 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_intr_rand_pgm.509881085
Directory /workspace/39.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/39.gpio_rand_intr_trigger.2695992675
Short name T649
Test name
Test status
Simulation time 633828522 ps
CPU time 3.25 seconds
Started Jul 30 06:02:51 PM PDT 24
Finished Jul 30 06:02:54 PM PDT 24
Peak memory 198640 kb
Host smart-2bd843ca-94d0-458b-b43c-f78376159d51
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695992675 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_rand_intr_trigger
.2695992675
Directory /workspace/39.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din.1658308930
Short name T154
Test name
Test status
Simulation time 85696386 ps
CPU time 1.19 seconds
Started Jul 30 06:02:51 PM PDT 24
Finished Jul 30 06:02:52 PM PDT 24
Peak memory 196660 kb
Host smart-b640897a-18f7-4c13-929d-955c727b8065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658308930 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din.1658308930
Directory /workspace/39.gpio_random_dout_din/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din_no_pullup_pulldown.3597898197
Short name T498
Test name
Test status
Simulation time 279814814 ps
CPU time 1.04 seconds
Started Jul 30 06:02:52 PM PDT 24
Finished Jul 30 06:02:54 PM PDT 24
Peak memory 197408 kb
Host smart-ed82a84d-3a78-4b98-ba98-1dd0b63ae190
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597898197 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din_no_pullu
p_pulldown.3597898197
Directory /workspace/39.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_random_long_reg_writes_reg_reads.2697718650
Short name T162
Test name
Test status
Simulation time 47626178 ps
CPU time 2.05 seconds
Started Jul 30 06:03:03 PM PDT 24
Finished Jul 30 06:03:05 PM PDT 24
Peak memory 198536 kb
Host smart-25d45fef-bde8-4d82-b448-133dbd3905b4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697718650 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_ra
ndom_long_reg_writes_reg_reads.2697718650
Directory /workspace/39.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/39.gpio_smoke.4168578780
Short name T702
Test name
Test status
Simulation time 232054683 ps
CPU time 1.12 seconds
Started Jul 30 06:02:54 PM PDT 24
Finished Jul 30 06:02:55 PM PDT 24
Peak memory 196256 kb
Host smart-acf6c7c8-b926-4992-8aed-9b59a1efd6b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4168578780 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke.4168578780
Directory /workspace/39.gpio_smoke/latest

Test location /workspace/coverage/default/39.gpio_smoke_no_pullup_pulldown.2641436538
Short name T202
Test name
Test status
Simulation time 77648957 ps
CPU time 1.43 seconds
Started Jul 30 06:02:51 PM PDT 24
Finished Jul 30 06:02:53 PM PDT 24
Peak memory 197320 kb
Host smart-d77e2bfb-b823-4ed8-be87-6a12c77cda28
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641436538 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown.2641436538
Directory /workspace/39.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_stress_all.1365439808
Short name T357
Test name
Test status
Simulation time 13713163060 ps
CPU time 140.6 seconds
Started Jul 30 06:02:50 PM PDT 24
Finished Jul 30 06:05:11 PM PDT 24
Peak memory 198704 kb
Host smart-a90918f1-f4c2-4480-ae67-ac00a85f00f6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365439808 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.
gpio_stress_all.1365439808
Directory /workspace/39.gpio_stress_all/latest

Test location /workspace/coverage/default/4.gpio_alert_test.1594990599
Short name T192
Test name
Test status
Simulation time 15301436 ps
CPU time 0.58 seconds
Started Jul 30 06:01:54 PM PDT 24
Finished Jul 30 06:01:54 PM PDT 24
Peak memory 195140 kb
Host smart-d8b891af-921c-4c7d-a46a-ccbb463629a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594990599 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_alert_test.1594990599
Directory /workspace/4.gpio_alert_test/latest

Test location /workspace/coverage/default/4.gpio_dout_din_regs_random_rw.705410289
Short name T416
Test name
Test status
Simulation time 25233220 ps
CPU time 0.84 seconds
Started Jul 30 06:01:54 PM PDT 24
Finished Jul 30 06:01:55 PM PDT 24
Peak memory 197108 kb
Host smart-1b53e691-0f2b-4ae9-9385-20b19d0be31f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=705410289 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_dout_din_regs_random_rw.705410289
Directory /workspace/4.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/4.gpio_filter_stress.215299152
Short name T267
Test name
Test status
Simulation time 945372456 ps
CPU time 15.74 seconds
Started Jul 30 06:01:52 PM PDT 24
Finished Jul 30 06:02:08 PM PDT 24
Peak memory 197564 kb
Host smart-24d9f686-4e0c-447f-86c0-67adfdae1d60
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215299152 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_filter_stress
.215299152
Directory /workspace/4.gpio_filter_stress/latest

Test location /workspace/coverage/default/4.gpio_full_random.2791551599
Short name T465
Test name
Test status
Simulation time 288050015 ps
CPU time 0.89 seconds
Started Jul 30 06:01:53 PM PDT 24
Finished Jul 30 06:01:54 PM PDT 24
Peak memory 196424 kb
Host smart-0d72f4d5-1a38-42a2-8cfb-399f3ae9bf27
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791551599 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_full_random.2791551599
Directory /workspace/4.gpio_full_random/latest

Test location /workspace/coverage/default/4.gpio_intr_rand_pgm.3833949346
Short name T585
Test name
Test status
Simulation time 198853602 ps
CPU time 1.55 seconds
Started Jul 30 06:02:00 PM PDT 24
Finished Jul 30 06:02:02 PM PDT 24
Peak memory 198640 kb
Host smart-a4b52188-78fb-46ff-b559-e2c76d0559e1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833949346 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_intr_rand_pgm.3833949346
Directory /workspace/4.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/4.gpio_intr_with_filter_rand_intr_event.2715510032
Short name T376
Test name
Test status
Simulation time 137593795 ps
CPU time 2.76 seconds
Started Jul 30 06:01:53 PM PDT 24
Finished Jul 30 06:01:56 PM PDT 24
Peak memory 198588 kb
Host smart-c1388f15-038e-4d1d-bacd-8de6df809efa
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715510032 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.gpio_intr_with_filter_rand_intr_event.2715510032
Directory /workspace/4.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/4.gpio_rand_intr_trigger.3335267079
Short name T214
Test name
Test status
Simulation time 110774330 ps
CPU time 3.04 seconds
Started Jul 30 06:01:55 PM PDT 24
Finished Jul 30 06:01:58 PM PDT 24
Peak memory 198636 kb
Host smart-a247f349-2df0-41b1-ba37-7efc638ece82
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335267079 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_rand_intr_trigger.
3335267079
Directory /workspace/4.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din.4279829321
Short name T609
Test name
Test status
Simulation time 35819494 ps
CPU time 1.26 seconds
Started Jul 30 06:01:43 PM PDT 24
Finished Jul 30 06:01:44 PM PDT 24
Peak memory 198608 kb
Host smart-fbafc503-d33c-4149-ab60-48ffb9fea54a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4279829321 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din.4279829321
Directory /workspace/4.gpio_random_dout_din/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din_no_pullup_pulldown.1033330107
Short name T526
Test name
Test status
Simulation time 27798437 ps
CPU time 1.09 seconds
Started Jul 30 06:01:58 PM PDT 24
Finished Jul 30 06:01:59 PM PDT 24
Peak memory 197340 kb
Host smart-5a0c55eb-ec9d-45e3-b3b3-8b881f91abb3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033330107 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din_no_pullup
_pulldown.1033330107
Directory /workspace/4.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_random_long_reg_writes_reg_reads.1769144733
Short name T328
Test name
Test status
Simulation time 171469544 ps
CPU time 2.17 seconds
Started Jul 30 06:02:01 PM PDT 24
Finished Jul 30 06:02:04 PM PDT 24
Peak memory 198548 kb
Host smart-a96c70f6-0d0b-49e2-9b96-c88951c07912
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769144733 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_ran
dom_long_reg_writes_reg_reads.1769144733
Directory /workspace/4.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/4.gpio_smoke.697775229
Short name T556
Test name
Test status
Simulation time 269357534 ps
CPU time 1.07 seconds
Started Jul 30 06:01:50 PM PDT 24
Finished Jul 30 06:01:51 PM PDT 24
Peak memory 196120 kb
Host smart-c999ad72-f2f6-47ba-ac56-06498c7b600b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=697775229 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke.697775229
Directory /workspace/4.gpio_smoke/latest

Test location /workspace/coverage/default/4.gpio_smoke_no_pullup_pulldown.2956477371
Short name T611
Test name
Test status
Simulation time 66170600 ps
CPU time 1.12 seconds
Started Jul 30 06:01:58 PM PDT 24
Finished Jul 30 06:02:00 PM PDT 24
Peak memory 196264 kb
Host smart-3dfc3387-e73f-4df9-a185-59c20d0bf114
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956477371 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown.2956477371
Directory /workspace/4.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_stress_all.2236494194
Short name T189
Test name
Test status
Simulation time 74824083160 ps
CPU time 223.54 seconds
Started Jul 30 06:01:48 PM PDT 24
Finished Jul 30 06:05:31 PM PDT 24
Peak memory 198736 kb
Host smart-b74bc2c2-5d6a-4b3a-a738-959801e035eb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236494194 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.g
pio_stress_all.2236494194
Directory /workspace/4.gpio_stress_all/latest

Test location /workspace/coverage/default/4.gpio_stress_all_with_rand_reset.2723775087
Short name T58
Test name
Test status
Simulation time 336725467900 ps
CPU time 2622.1 seconds
Started Jul 30 06:02:00 PM PDT 24
Finished Jul 30 06:45:42 PM PDT 24
Peak memory 198940 kb
Host smart-1993436a-b09c-4f93-b559-04d8a8c3c044
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2723775087 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_stress_all_with_rand_reset.2723775087
Directory /workspace/4.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.gpio_alert_test.3062419779
Short name T237
Test name
Test status
Simulation time 29936188 ps
CPU time 0.6 seconds
Started Jul 30 06:03:01 PM PDT 24
Finished Jul 30 06:03:01 PM PDT 24
Peak memory 194476 kb
Host smart-0cb83d01-bb69-4605-a343-b75b9d870196
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062419779 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_alert_test.3062419779
Directory /workspace/40.gpio_alert_test/latest

Test location /workspace/coverage/default/40.gpio_dout_din_regs_random_rw.2101808542
Short name T244
Test name
Test status
Simulation time 93254297 ps
CPU time 0.79 seconds
Started Jul 30 06:02:51 PM PDT 24
Finished Jul 30 06:02:52 PM PDT 24
Peak memory 195832 kb
Host smart-1dd1be1f-bb3b-4f0f-860d-2c27291a66b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2101808542 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_dout_din_regs_random_rw.2101808542
Directory /workspace/40.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/40.gpio_filter_stress.3017508254
Short name T241
Test name
Test status
Simulation time 7267803833 ps
CPU time 28.03 seconds
Started Jul 30 06:02:54 PM PDT 24
Finished Jul 30 06:03:23 PM PDT 24
Peak memory 197228 kb
Host smart-6170b4f9-dec6-4e6c-be74-61a0f110dce0
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017508254 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_filter_stre
ss.3017508254
Directory /workspace/40.gpio_filter_stress/latest

Test location /workspace/coverage/default/40.gpio_full_random.209060347
Short name T471
Test name
Test status
Simulation time 152278402 ps
CPU time 0.84 seconds
Started Jul 30 06:02:57 PM PDT 24
Finished Jul 30 06:02:58 PM PDT 24
Peak memory 197300 kb
Host smart-3a3481e8-a38b-47d9-9ca0-f3b033b911bd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209060347 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_full_random.209060347
Directory /workspace/40.gpio_full_random/latest

Test location /workspace/coverage/default/40.gpio_intr_rand_pgm.3406450209
Short name T254
Test name
Test status
Simulation time 272816023 ps
CPU time 1.22 seconds
Started Jul 30 06:02:53 PM PDT 24
Finished Jul 30 06:02:54 PM PDT 24
Peak memory 197780 kb
Host smart-8980922c-2cdc-4867-a612-5844fd826413
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406450209 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_intr_rand_pgm.3406450209
Directory /workspace/40.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/40.gpio_intr_with_filter_rand_intr_event.2171489025
Short name T23
Test name
Test status
Simulation time 201948226 ps
CPU time 1.49 seconds
Started Jul 30 06:02:57 PM PDT 24
Finished Jul 30 06:02:58 PM PDT 24
Peak memory 197044 kb
Host smart-b64c4edb-218b-4a98-a726-0f444ad2331f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171489025 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 40.gpio_intr_with_filter_rand_intr_event.2171489025
Directory /workspace/40.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/40.gpio_rand_intr_trigger.2000719661
Short name T696
Test name
Test status
Simulation time 118432817 ps
CPU time 3.46 seconds
Started Jul 30 06:03:01 PM PDT 24
Finished Jul 30 06:03:04 PM PDT 24
Peak memory 197744 kb
Host smart-cbfece21-42da-4fa0-93e3-bd66b5109229
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000719661 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_rand_intr_trigger
.2000719661
Directory /workspace/40.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din.3760767449
Short name T15
Test name
Test status
Simulation time 31249357 ps
CPU time 0.77 seconds
Started Jul 30 06:02:54 PM PDT 24
Finished Jul 30 06:02:55 PM PDT 24
Peak memory 196132 kb
Host smart-144bfa99-6ee1-428d-9be9-c48771775256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3760767449 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din.3760767449
Directory /workspace/40.gpio_random_dout_din/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din_no_pullup_pulldown.2203413556
Short name T158
Test name
Test status
Simulation time 703064987 ps
CPU time 1.21 seconds
Started Jul 30 06:02:54 PM PDT 24
Finished Jul 30 06:02:56 PM PDT 24
Peak memory 196420 kb
Host smart-262eb25b-a57b-466a-b0f5-586207f71f8f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203413556 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din_no_pullu
p_pulldown.2203413556
Directory /workspace/40.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_random_long_reg_writes_reg_reads.3518850265
Short name T652
Test name
Test status
Simulation time 110872146 ps
CPU time 5.17 seconds
Started Jul 30 06:02:57 PM PDT 24
Finished Jul 30 06:03:02 PM PDT 24
Peak memory 198572 kb
Host smart-78217eb6-2ada-4756-ba16-d00088c8018d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518850265 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_ra
ndom_long_reg_writes_reg_reads.3518850265
Directory /workspace/40.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/40.gpio_smoke.1722280835
Short name T52
Test name
Test status
Simulation time 84124663 ps
CPU time 1.24 seconds
Started Jul 30 06:02:53 PM PDT 24
Finished Jul 30 06:02:55 PM PDT 24
Peak memory 197156 kb
Host smart-6cc191b0-f0d2-4db0-8540-fa3c27c4b91b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1722280835 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke.1722280835
Directory /workspace/40.gpio_smoke/latest

Test location /workspace/coverage/default/40.gpio_smoke_no_pullup_pulldown.2239478916
Short name T169
Test name
Test status
Simulation time 73029374 ps
CPU time 1.02 seconds
Started Jul 30 06:02:54 PM PDT 24
Finished Jul 30 06:02:55 PM PDT 24
Peak memory 197116 kb
Host smart-23f107ea-6229-4c51-9fb0-b5874be727e1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239478916 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown.2239478916
Directory /workspace/40.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_stress_all.1561453524
Short name T1
Test name
Test status
Simulation time 17576416685 ps
CPU time 184.43 seconds
Started Jul 30 06:02:56 PM PDT 24
Finished Jul 30 06:06:01 PM PDT 24
Peak memory 198816 kb
Host smart-a808a0d3-9bbe-43e2-9355-a050c1496539
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561453524 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.
gpio_stress_all.1561453524
Directory /workspace/40.gpio_stress_all/latest

Test location /workspace/coverage/default/40.gpio_stress_all_with_rand_reset.364265908
Short name T61
Test name
Test status
Simulation time 111519503459 ps
CPU time 525.09 seconds
Started Jul 30 06:03:02 PM PDT 24
Finished Jul 30 06:11:47 PM PDT 24
Peak memory 198884 kb
Host smart-c2d2ad14-83ff-447a-b3fb-490d517f94b0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=364265908 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_stress_all_with_rand_reset.364265908
Directory /workspace/40.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.gpio_alert_test.3197148982
Short name T488
Test name
Test status
Simulation time 14548057 ps
CPU time 0.6 seconds
Started Jul 30 06:03:03 PM PDT 24
Finished Jul 30 06:03:03 PM PDT 24
Peak memory 195144 kb
Host smart-d183f567-1b38-42aa-98f8-5ec1372acea9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197148982 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_alert_test.3197148982
Directory /workspace/41.gpio_alert_test/latest

Test location /workspace/coverage/default/41.gpio_dout_din_regs_random_rw.2859923763
Short name T300
Test name
Test status
Simulation time 21811469 ps
CPU time 0.62 seconds
Started Jul 30 06:02:58 PM PDT 24
Finished Jul 30 06:02:59 PM PDT 24
Peak memory 194540 kb
Host smart-199581fe-4f9e-4994-9482-fe1baab2e09d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2859923763 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_dout_din_regs_random_rw.2859923763
Directory /workspace/41.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/41.gpio_filter_stress.4074927885
Short name T187
Test name
Test status
Simulation time 911768438 ps
CPU time 13.25 seconds
Started Jul 30 06:03:00 PM PDT 24
Finished Jul 30 06:03:13 PM PDT 24
Peak memory 197712 kb
Host smart-e126b2bd-b214-46c5-93ea-f4a2bcbd7b36
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074927885 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_filter_stre
ss.4074927885
Directory /workspace/41.gpio_filter_stress/latest

Test location /workspace/coverage/default/41.gpio_full_random.715754641
Short name T331
Test name
Test status
Simulation time 284640171 ps
CPU time 1.04 seconds
Started Jul 30 06:02:59 PM PDT 24
Finished Jul 30 06:03:01 PM PDT 24
Peak memory 197116 kb
Host smart-eebd1497-af46-44ac-b8d8-6a65e40ea136
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715754641 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_full_random.715754641
Directory /workspace/41.gpio_full_random/latest

Test location /workspace/coverage/default/41.gpio_intr_rand_pgm.671091806
Short name T527
Test name
Test status
Simulation time 65735549 ps
CPU time 1.35 seconds
Started Jul 30 06:02:56 PM PDT 24
Finished Jul 30 06:02:58 PM PDT 24
Peak memory 197408 kb
Host smart-78161114-a88f-472e-8ed6-50edc2da66db
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671091806 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_intr_rand_pgm.671091806
Directory /workspace/41.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/41.gpio_intr_with_filter_rand_intr_event.1809687043
Short name T273
Test name
Test status
Simulation time 44250328 ps
CPU time 1.54 seconds
Started Jul 30 06:03:02 PM PDT 24
Finished Jul 30 06:03:04 PM PDT 24
Peak memory 196876 kb
Host smart-818f1533-b142-45a2-86b9-c4b082e3b9ed
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809687043 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 41.gpio_intr_with_filter_rand_intr_event.1809687043
Directory /workspace/41.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/41.gpio_rand_intr_trigger.787480531
Short name T310
Test name
Test status
Simulation time 216687710 ps
CPU time 1.54 seconds
Started Jul 30 06:02:57 PM PDT 24
Finished Jul 30 06:02:59 PM PDT 24
Peak memory 196376 kb
Host smart-f4d84aaa-e330-4ea9-a33d-9f242a98f155
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787480531 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_rand_intr_trigger.
787480531
Directory /workspace/41.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din.632247199
Short name T508
Test name
Test status
Simulation time 107533268 ps
CPU time 1.32 seconds
Started Jul 30 06:03:00 PM PDT 24
Finished Jul 30 06:03:01 PM PDT 24
Peak memory 196448 kb
Host smart-db2598d8-f321-4fc7-a9c6-379e78c78431
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=632247199 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din.632247199
Directory /workspace/41.gpio_random_dout_din/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din_no_pullup_pulldown.2705157921
Short name T639
Test name
Test status
Simulation time 136979041 ps
CPU time 0.84 seconds
Started Jul 30 06:03:01 PM PDT 24
Finished Jul 30 06:03:02 PM PDT 24
Peak memory 197124 kb
Host smart-ef293fbc-3f71-4927-9f41-94a5da10d766
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705157921 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din_no_pullu
p_pulldown.2705157921
Directory /workspace/41.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_random_long_reg_writes_reg_reads.1285900698
Short name T251
Test name
Test status
Simulation time 837632770 ps
CPU time 4.56 seconds
Started Jul 30 06:03:00 PM PDT 24
Finished Jul 30 06:03:05 PM PDT 24
Peak memory 198596 kb
Host smart-804ad52c-4e55-404d-97ae-32af9a41f64e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285900698 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_ra
ndom_long_reg_writes_reg_reads.1285900698
Directory /workspace/41.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/41.gpio_smoke.3144345846
Short name T632
Test name
Test status
Simulation time 46677579 ps
CPU time 0.84 seconds
Started Jul 30 06:03:05 PM PDT 24
Finished Jul 30 06:03:06 PM PDT 24
Peak memory 196072 kb
Host smart-ed0ee688-3243-4b94-911c-45f1a8fc7a7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3144345846 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke.3144345846
Directory /workspace/41.gpio_smoke/latest

Test location /workspace/coverage/default/41.gpio_smoke_no_pullup_pulldown.856382318
Short name T533
Test name
Test status
Simulation time 34173219 ps
CPU time 1.12 seconds
Started Jul 30 06:02:59 PM PDT 24
Finished Jul 30 06:03:01 PM PDT 24
Peak memory 196156 kb
Host smart-21147c86-98df-403d-91c5-da572331f24e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856382318 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown.856382318
Directory /workspace/41.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_stress_all.4159356540
Short name T666
Test name
Test status
Simulation time 15559440786 ps
CPU time 43.38 seconds
Started Jul 30 06:03:03 PM PDT 24
Finished Jul 30 06:03:47 PM PDT 24
Peak memory 198768 kb
Host smart-1f3a6ac8-ee30-4b63-a4c3-c5b1f0782c08
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159356540 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.
gpio_stress_all.4159356540
Directory /workspace/41.gpio_stress_all/latest

Test location /workspace/coverage/default/42.gpio_alert_test.2701398824
Short name T513
Test name
Test status
Simulation time 24195695 ps
CPU time 0.61 seconds
Started Jul 30 06:03:05 PM PDT 24
Finished Jul 30 06:03:06 PM PDT 24
Peak memory 195172 kb
Host smart-76813abf-2d64-45c3-aa44-135c2101c8be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701398824 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_alert_test.2701398824
Directory /workspace/42.gpio_alert_test/latest

Test location /workspace/coverage/default/42.gpio_dout_din_regs_random_rw.3366406449
Short name T606
Test name
Test status
Simulation time 35568704 ps
CPU time 0.81 seconds
Started Jul 30 06:02:58 PM PDT 24
Finished Jul 30 06:02:59 PM PDT 24
Peak memory 195844 kb
Host smart-c54c545e-f5f2-43e4-9bd6-f88c9c26798f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3366406449 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_dout_din_regs_random_rw.3366406449
Directory /workspace/42.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/42.gpio_filter_stress.1348379322
Short name T681
Test name
Test status
Simulation time 438849108 ps
CPU time 23.1 seconds
Started Jul 30 06:03:01 PM PDT 24
Finished Jul 30 06:03:24 PM PDT 24
Peak memory 197412 kb
Host smart-4597c134-8377-4590-9476-35d687705905
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348379322 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_filter_stre
ss.1348379322
Directory /workspace/42.gpio_filter_stress/latest

Test location /workspace/coverage/default/42.gpio_full_random.3560213174
Short name T341
Test name
Test status
Simulation time 202582553 ps
CPU time 0.81 seconds
Started Jul 30 06:03:04 PM PDT 24
Finished Jul 30 06:03:05 PM PDT 24
Peak memory 197144 kb
Host smart-c0965731-94b2-45cb-af11-6e309c1a9fee
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560213174 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_full_random.3560213174
Directory /workspace/42.gpio_full_random/latest

Test location /workspace/coverage/default/42.gpio_intr_rand_pgm.3897721280
Short name T163
Test name
Test status
Simulation time 60259293 ps
CPU time 1.32 seconds
Started Jul 30 06:03:02 PM PDT 24
Finished Jul 30 06:03:03 PM PDT 24
Peak memory 196784 kb
Host smart-dd8dbfbb-bead-43ce-a17e-2ff88182d854
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897721280 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_intr_rand_pgm.3897721280
Directory /workspace/42.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/42.gpio_intr_with_filter_rand_intr_event.4016369430
Short name T487
Test name
Test status
Simulation time 20647358 ps
CPU time 1.06 seconds
Started Jul 30 06:03:00 PM PDT 24
Finished Jul 30 06:03:01 PM PDT 24
Peak memory 196708 kb
Host smart-9dda5c40-add7-43b4-bfd7-0da7905eccd4
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016369430 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 42.gpio_intr_with_filter_rand_intr_event.4016369430
Directory /workspace/42.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/42.gpio_rand_intr_trigger.3997425445
Short name T312
Test name
Test status
Simulation time 173656050 ps
CPU time 1.4 seconds
Started Jul 30 06:03:01 PM PDT 24
Finished Jul 30 06:03:02 PM PDT 24
Peak memory 196380 kb
Host smart-d30b64d0-eea6-42a0-8f73-e16a8d4e6951
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997425445 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_rand_intr_trigger
.3997425445
Directory /workspace/42.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din.620547519
Short name T173
Test name
Test status
Simulation time 63238008 ps
CPU time 1.03 seconds
Started Jul 30 06:03:01 PM PDT 24
Finished Jul 30 06:03:03 PM PDT 24
Peak memory 196576 kb
Host smart-bcbf2b0f-d266-4b06-819e-1d8a2a3b0363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620547519 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din.620547519
Directory /workspace/42.gpio_random_dout_din/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din_no_pullup_pulldown.2749951710
Short name T710
Test name
Test status
Simulation time 125011018 ps
CPU time 1.28 seconds
Started Jul 30 06:03:05 PM PDT 24
Finished Jul 30 06:03:07 PM PDT 24
Peak memory 197560 kb
Host smart-1243dbeb-d989-4d8c-bfa1-ea190b721390
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749951710 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din_no_pullu
p_pulldown.2749951710
Directory /workspace/42.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_random_long_reg_writes_reg_reads.439053154
Short name T123
Test name
Test status
Simulation time 151894477 ps
CPU time 1.7 seconds
Started Jul 30 06:02:57 PM PDT 24
Finished Jul 30 06:02:59 PM PDT 24
Peak memory 198616 kb
Host smart-2c5e158b-b043-4b8d-9f84-9895b8ee3885
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439053154 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_ran
dom_long_reg_writes_reg_reads.439053154
Directory /workspace/42.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/42.gpio_smoke.176376813
Short name T252
Test name
Test status
Simulation time 109914072 ps
CPU time 1.04 seconds
Started Jul 30 06:03:00 PM PDT 24
Finished Jul 30 06:03:01 PM PDT 24
Peak memory 196304 kb
Host smart-17dde1a9-e9c4-40fe-87cd-735cb905dfc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=176376813 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke.176376813
Directory /workspace/42.gpio_smoke/latest

Test location /workspace/coverage/default/42.gpio_smoke_no_pullup_pulldown.2666983518
Short name T515
Test name
Test status
Simulation time 242535800 ps
CPU time 1.26 seconds
Started Jul 30 06:03:02 PM PDT 24
Finished Jul 30 06:03:03 PM PDT 24
Peak memory 196960 kb
Host smart-83511a4b-3dbd-47c1-b5d1-cb825721f4ed
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666983518 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown.2666983518
Directory /workspace/42.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_stress_all.1155898235
Short name T394
Test name
Test status
Simulation time 19097235795 ps
CPU time 47.47 seconds
Started Jul 30 06:02:59 PM PDT 24
Finished Jul 30 06:03:47 PM PDT 24
Peak memory 198768 kb
Host smart-2cd2c1c8-121c-4daa-99d0-c7643c16a39e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155898235 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.
gpio_stress_all.1155898235
Directory /workspace/42.gpio_stress_all/latest

Test location /workspace/coverage/default/42.gpio_stress_all_with_rand_reset.2802387156
Short name T371
Test name
Test status
Simulation time 84059081542 ps
CPU time 1791.11 seconds
Started Jul 30 06:03:00 PM PDT 24
Finished Jul 30 06:32:51 PM PDT 24
Peak memory 198880 kb
Host smart-9a7eaaa5-e111-46fa-9d30-876b019c9c1e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2802387156 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_stress_all_with_rand_reset.2802387156
Directory /workspace/42.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.gpio_alert_test.76345436
Short name T206
Test name
Test status
Simulation time 36648573 ps
CPU time 0.6 seconds
Started Jul 30 06:03:06 PM PDT 24
Finished Jul 30 06:03:06 PM PDT 24
Peak memory 195140 kb
Host smart-e63de64d-afab-4e14-aa6f-c83863fc3260
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76345436 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_alert_test.76345436
Directory /workspace/43.gpio_alert_test/latest

Test location /workspace/coverage/default/43.gpio_dout_din_regs_random_rw.2563665151
Short name T605
Test name
Test status
Simulation time 69609182 ps
CPU time 0.74 seconds
Started Jul 30 06:03:03 PM PDT 24
Finished Jul 30 06:03:04 PM PDT 24
Peak memory 194592 kb
Host smart-be78a8d5-5df6-4b09-812d-5fa39c617646
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2563665151 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_dout_din_regs_random_rw.2563665151
Directory /workspace/43.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/43.gpio_filter_stress.1227606850
Short name T302
Test name
Test status
Simulation time 871837442 ps
CPU time 22.79 seconds
Started Jul 30 06:03:03 PM PDT 24
Finished Jul 30 06:03:26 PM PDT 24
Peak memory 198588 kb
Host smart-ca581a16-e53c-4d58-8cef-62df8609ea1d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227606850 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_filter_stre
ss.1227606850
Directory /workspace/43.gpio_filter_stress/latest

Test location /workspace/coverage/default/43.gpio_full_random.2721840265
Short name T4
Test name
Test status
Simulation time 113753731 ps
CPU time 0.89 seconds
Started Jul 30 06:02:59 PM PDT 24
Finished Jul 30 06:03:00 PM PDT 24
Peak memory 197608 kb
Host smart-f2e994b7-eacb-4e91-82aa-ad23cadbdcb2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721840265 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_full_random.2721840265
Directory /workspace/43.gpio_full_random/latest

Test location /workspace/coverage/default/43.gpio_intr_rand_pgm.3193956484
Short name T451
Test name
Test status
Simulation time 159226629 ps
CPU time 0.92 seconds
Started Jul 30 06:03:04 PM PDT 24
Finished Jul 30 06:03:05 PM PDT 24
Peak memory 196508 kb
Host smart-26a749c5-f7b1-429c-b8cb-3e4c7d577c03
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193956484 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_intr_rand_pgm.3193956484
Directory /workspace/43.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/43.gpio_intr_with_filter_rand_intr_event.3125641326
Short name T135
Test name
Test status
Simulation time 93934032 ps
CPU time 3.62 seconds
Started Jul 30 06:03:04 PM PDT 24
Finished Jul 30 06:03:07 PM PDT 24
Peak memory 198672 kb
Host smart-afe6c23b-a881-431d-a003-3ea9f7836882
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125641326 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 43.gpio_intr_with_filter_rand_intr_event.3125641326
Directory /workspace/43.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/43.gpio_rand_intr_trigger.1637213542
Short name T200
Test name
Test status
Simulation time 47340927 ps
CPU time 1.17 seconds
Started Jul 30 06:03:05 PM PDT 24
Finished Jul 30 06:03:06 PM PDT 24
Peak memory 196244 kb
Host smart-2efaa6aa-378e-4877-aa35-804a1561c4d9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637213542 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_rand_intr_trigger
.1637213542
Directory /workspace/43.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din.1178212905
Short name T224
Test name
Test status
Simulation time 307475749 ps
CPU time 1.37 seconds
Started Jul 30 06:03:02 PM PDT 24
Finished Jul 30 06:03:03 PM PDT 24
Peak memory 197548 kb
Host smart-7482b370-106e-454f-9901-23388ada9c2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1178212905 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din.1178212905
Directory /workspace/43.gpio_random_dout_din/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din_no_pullup_pulldown.1365266406
Short name T419
Test name
Test status
Simulation time 117566248 ps
CPU time 1.27 seconds
Started Jul 30 06:03:05 PM PDT 24
Finished Jul 30 06:03:06 PM PDT 24
Peak memory 196444 kb
Host smart-b42d1c54-b6f5-42fd-9065-d724e0f6201b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365266406 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din_no_pullu
p_pulldown.1365266406
Directory /workspace/43.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_random_long_reg_writes_reg_reads.2407775702
Short name T547
Test name
Test status
Simulation time 1621263716 ps
CPU time 2.74 seconds
Started Jul 30 06:03:03 PM PDT 24
Finished Jul 30 06:03:05 PM PDT 24
Peak memory 198644 kb
Host smart-78c9f4be-a06a-4ae9-a744-4c9710c43c53
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407775702 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_ra
ndom_long_reg_writes_reg_reads.2407775702
Directory /workspace/43.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/43.gpio_smoke.1847192770
Short name T289
Test name
Test status
Simulation time 69925341 ps
CPU time 0.99 seconds
Started Jul 30 06:03:07 PM PDT 24
Finished Jul 30 06:03:08 PM PDT 24
Peak memory 196136 kb
Host smart-c3a426bc-9a5a-44f1-a775-397adaf699fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1847192770 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke.1847192770
Directory /workspace/43.gpio_smoke/latest

Test location /workspace/coverage/default/43.gpio_smoke_no_pullup_pulldown.147540473
Short name T119
Test name
Test status
Simulation time 344856581 ps
CPU time 1.45 seconds
Started Jul 30 06:03:03 PM PDT 24
Finished Jul 30 06:03:05 PM PDT 24
Peak memory 196732 kb
Host smart-ab079695-6635-4cb1-b8a0-c37ba59123de
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147540473 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown.147540473
Directory /workspace/43.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_stress_all.2762743124
Short name T705
Test name
Test status
Simulation time 191957601285 ps
CPU time 114.12 seconds
Started Jul 30 06:03:03 PM PDT 24
Finished Jul 30 06:04:57 PM PDT 24
Peak memory 198804 kb
Host smart-51ce71db-6a1f-499b-9f1d-0bbc56400e78
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762743124 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.
gpio_stress_all.2762743124
Directory /workspace/43.gpio_stress_all/latest

Test location /workspace/coverage/default/43.gpio_stress_all_with_rand_reset.633433875
Short name T99
Test name
Test status
Simulation time 177026753357 ps
CPU time 1250.93 seconds
Started Jul 30 06:03:05 PM PDT 24
Finished Jul 30 06:23:56 PM PDT 24
Peak memory 198856 kb
Host smart-5c4cffb7-f844-4878-a546-98844a00d777
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=633433875 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_stress_all_with_rand_reset.633433875
Directory /workspace/43.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.gpio_alert_test.342315196
Short name T675
Test name
Test status
Simulation time 13001282 ps
CPU time 0.62 seconds
Started Jul 30 06:03:09 PM PDT 24
Finished Jul 30 06:03:09 PM PDT 24
Peak memory 195388 kb
Host smart-a29490d6-6982-4908-a8c4-a5c7f7bd02ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342315196 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_alert_test.342315196
Directory /workspace/44.gpio_alert_test/latest

Test location /workspace/coverage/default/44.gpio_dout_din_regs_random_rw.2186221789
Short name T506
Test name
Test status
Simulation time 14706951 ps
CPU time 0.62 seconds
Started Jul 30 06:03:04 PM PDT 24
Finished Jul 30 06:03:05 PM PDT 24
Peak memory 195216 kb
Host smart-75c8f539-1b5b-4027-aa5b-a7d558d4d708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2186221789 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_dout_din_regs_random_rw.2186221789
Directory /workspace/44.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/44.gpio_filter_stress.349828378
Short name T577
Test name
Test status
Simulation time 1551753627 ps
CPU time 21.84 seconds
Started Jul 30 06:03:07 PM PDT 24
Finished Jul 30 06:03:29 PM PDT 24
Peak memory 197576 kb
Host smart-95401b5c-45ec-4e80-a583-e0bbda8081e1
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349828378 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_filter_stres
s.349828378
Directory /workspace/44.gpio_filter_stress/latest

Test location /workspace/coverage/default/44.gpio_full_random.3267941533
Short name T360
Test name
Test status
Simulation time 21932853 ps
CPU time 0.66 seconds
Started Jul 30 06:03:06 PM PDT 24
Finished Jul 30 06:03:07 PM PDT 24
Peak memory 195828 kb
Host smart-aebeae85-d762-4542-a5bc-cda23b574c84
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267941533 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_full_random.3267941533
Directory /workspace/44.gpio_full_random/latest

Test location /workspace/coverage/default/44.gpio_intr_rand_pgm.4077256390
Short name T423
Test name
Test status
Simulation time 210477085 ps
CPU time 1.44 seconds
Started Jul 30 06:03:04 PM PDT 24
Finished Jul 30 06:03:06 PM PDT 24
Peak memory 197504 kb
Host smart-42a70528-ed57-4b05-90d9-47a88001af71
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077256390 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_intr_rand_pgm.4077256390
Directory /workspace/44.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/44.gpio_intr_with_filter_rand_intr_event.1972187774
Short name T352
Test name
Test status
Simulation time 51512712 ps
CPU time 2.21 seconds
Started Jul 30 06:03:05 PM PDT 24
Finished Jul 30 06:03:07 PM PDT 24
Peak memory 198628 kb
Host smart-874e44c5-9574-414b-84dc-291771dae1d3
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972187774 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 44.gpio_intr_with_filter_rand_intr_event.1972187774
Directory /workspace/44.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/44.gpio_rand_intr_trigger.599944651
Short name T700
Test name
Test status
Simulation time 430798055 ps
CPU time 1.67 seconds
Started Jul 30 06:03:04 PM PDT 24
Finished Jul 30 06:03:06 PM PDT 24
Peak memory 197272 kb
Host smart-8bdf8ac8-32fb-4ccb-8b7e-9907b5a41d31
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599944651 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_rand_intr_trigger.
599944651
Directory /workspace/44.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din.406086905
Short name T107
Test name
Test status
Simulation time 159993439 ps
CPU time 0.79 seconds
Started Jul 30 06:03:06 PM PDT 24
Finished Jul 30 06:03:07 PM PDT 24
Peak memory 195948 kb
Host smart-07e9b935-7afe-4806-80cc-b590cd225f3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=406086905 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din.406086905
Directory /workspace/44.gpio_random_dout_din/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din_no_pullup_pulldown.3629884163
Short name T265
Test name
Test status
Simulation time 49469792 ps
CPU time 0.79 seconds
Started Jul 30 06:03:04 PM PDT 24
Finished Jul 30 06:03:05 PM PDT 24
Peak memory 195948 kb
Host smart-35349fc5-5b10-4b04-af7a-e6d5923b5a83
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629884163 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din_no_pullu
p_pulldown.3629884163
Directory /workspace/44.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_random_long_reg_writes_reg_reads.2367678582
Short name T578
Test name
Test status
Simulation time 553834916 ps
CPU time 4.76 seconds
Started Jul 30 06:03:09 PM PDT 24
Finished Jul 30 06:03:14 PM PDT 24
Peak memory 198504 kb
Host smart-91e599d2-d437-4b00-bbf3-232ee42e7ad9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367678582 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_ra
ndom_long_reg_writes_reg_reads.2367678582
Directory /workspace/44.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/44.gpio_smoke.2137149477
Short name T414
Test name
Test status
Simulation time 112819553 ps
CPU time 1.06 seconds
Started Jul 30 06:03:02 PM PDT 24
Finished Jul 30 06:03:03 PM PDT 24
Peak memory 197116 kb
Host smart-ddccde01-cc20-4cd3-b024-5d04ba5ada1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137149477 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke.2137149477
Directory /workspace/44.gpio_smoke/latest

Test location /workspace/coverage/default/44.gpio_smoke_no_pullup_pulldown.906136230
Short name T572
Test name
Test status
Simulation time 67439569 ps
CPU time 1.23 seconds
Started Jul 30 06:03:08 PM PDT 24
Finished Jul 30 06:03:09 PM PDT 24
Peak memory 197392 kb
Host smart-0c6acd11-ac3c-42a7-b896-03ad94c72713
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906136230 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown.906136230
Directory /workspace/44.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_stress_all.964629336
Short name T571
Test name
Test status
Simulation time 8997367279 ps
CPU time 100.55 seconds
Started Jul 30 06:03:07 PM PDT 24
Finished Jul 30 06:04:48 PM PDT 24
Peak memory 198816 kb
Host smart-aa9d6462-f6eb-4560-909c-416e18c8b6ee
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964629336 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.g
pio_stress_all.964629336
Directory /workspace/44.gpio_stress_all/latest

Test location /workspace/coverage/default/44.gpio_stress_all_with_rand_reset.2993606550
Short name T697
Test name
Test status
Simulation time 90022014014 ps
CPU time 983.58 seconds
Started Jul 30 06:03:08 PM PDT 24
Finished Jul 30 06:19:31 PM PDT 24
Peak memory 198940 kb
Host smart-f56ab8c7-5a07-4dd5-8601-d0b3702da70f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2993606550 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_stress_all_with_rand_reset.2993606550
Directory /workspace/44.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.gpio_alert_test.1459921263
Short name T538
Test name
Test status
Simulation time 13143242 ps
CPU time 0.59 seconds
Started Jul 30 06:03:11 PM PDT 24
Finished Jul 30 06:03:12 PM PDT 24
Peak memory 194432 kb
Host smart-c0b4e1b6-c47a-45fe-903f-9f09b34c2cfd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459921263 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_alert_test.1459921263
Directory /workspace/45.gpio_alert_test/latest

Test location /workspace/coverage/default/45.gpio_dout_din_regs_random_rw.1077833958
Short name T393
Test name
Test status
Simulation time 86351185 ps
CPU time 0.83 seconds
Started Jul 30 06:03:15 PM PDT 24
Finished Jul 30 06:03:15 PM PDT 24
Peak memory 195540 kb
Host smart-61dc0474-bacd-4e0b-9c9c-41730821e888
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1077833958 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_dout_din_regs_random_rw.1077833958
Directory /workspace/45.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/45.gpio_filter_stress.762676065
Short name T129
Test name
Test status
Simulation time 761748796 ps
CPU time 21.27 seconds
Started Jul 30 06:03:05 PM PDT 24
Finished Jul 30 06:03:27 PM PDT 24
Peak memory 197504 kb
Host smart-b0e90468-00ce-42bc-bc0d-6240c620921e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762676065 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_filter_stres
s.762676065
Directory /workspace/45.gpio_filter_stress/latest

Test location /workspace/coverage/default/45.gpio_full_random.2478333633
Short name T562
Test name
Test status
Simulation time 310093151 ps
CPU time 0.91 seconds
Started Jul 30 06:03:06 PM PDT 24
Finished Jul 30 06:03:07 PM PDT 24
Peak memory 198356 kb
Host smart-0c0cf8f0-0e23-4939-8b8a-ad582f2c7917
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478333633 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_full_random.2478333633
Directory /workspace/45.gpio_full_random/latest

Test location /workspace/coverage/default/45.gpio_intr_rand_pgm.3393836528
Short name T281
Test name
Test status
Simulation time 139423315 ps
CPU time 1.01 seconds
Started Jul 30 06:03:07 PM PDT 24
Finished Jul 30 06:03:08 PM PDT 24
Peak memory 196652 kb
Host smart-05457080-88cb-47de-86f4-63f7cc984857
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393836528 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_intr_rand_pgm.3393836528
Directory /workspace/45.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/45.gpio_intr_with_filter_rand_intr_event.2850271159
Short name T698
Test name
Test status
Simulation time 24856579 ps
CPU time 1.01 seconds
Started Jul 30 06:03:06 PM PDT 24
Finished Jul 30 06:03:07 PM PDT 24
Peak memory 196932 kb
Host smart-6078b11f-34db-411e-b72c-df5b98317e08
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850271159 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 45.gpio_intr_with_filter_rand_intr_event.2850271159
Directory /workspace/45.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/45.gpio_rand_intr_trigger.1798426740
Short name T377
Test name
Test status
Simulation time 95592774 ps
CPU time 0.91 seconds
Started Jul 30 06:03:30 PM PDT 24
Finished Jul 30 06:03:32 PM PDT 24
Peak memory 195612 kb
Host smart-089f46e0-8e2f-4d77-b0de-a58fa1ceaa0d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798426740 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_rand_intr_trigger
.1798426740
Directory /workspace/45.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din.2123501601
Short name T373
Test name
Test status
Simulation time 37654925 ps
CPU time 0.86 seconds
Started Jul 30 06:03:09 PM PDT 24
Finished Jul 30 06:03:10 PM PDT 24
Peak memory 197152 kb
Host smart-03281f1b-2a6e-4c6c-b708-e861ccb02fca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2123501601 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din.2123501601
Directory /workspace/45.gpio_random_dout_din/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din_no_pullup_pulldown.3983679117
Short name T559
Test name
Test status
Simulation time 33895713 ps
CPU time 0.7 seconds
Started Jul 30 06:03:06 PM PDT 24
Finished Jul 30 06:03:06 PM PDT 24
Peak memory 195820 kb
Host smart-acb4766a-7804-4a41-a4d1-f699061cd128
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983679117 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din_no_pullu
p_pulldown.3983679117
Directory /workspace/45.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_random_long_reg_writes_reg_reads.1474217787
Short name T159
Test name
Test status
Simulation time 223868603 ps
CPU time 2.36 seconds
Started Jul 30 06:03:09 PM PDT 24
Finished Jul 30 06:03:11 PM PDT 24
Peak memory 198528 kb
Host smart-ef29cdf8-abe8-4b63-b271-b17ecb86d547
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474217787 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_ra
ndom_long_reg_writes_reg_reads.1474217787
Directory /workspace/45.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/45.gpio_smoke.474041371
Short name T561
Test name
Test status
Simulation time 216042767 ps
CPU time 1.01 seconds
Started Jul 30 06:03:09 PM PDT 24
Finished Jul 30 06:03:10 PM PDT 24
Peak memory 196448 kb
Host smart-44bf43fd-6775-4787-b60a-29dafd615870
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=474041371 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke.474041371
Directory /workspace/45.gpio_smoke/latest

Test location /workspace/coverage/default/45.gpio_smoke_no_pullup_pulldown.1105932162
Short name T65
Test name
Test status
Simulation time 168506113 ps
CPU time 1.21 seconds
Started Jul 30 06:03:05 PM PDT 24
Finished Jul 30 06:03:06 PM PDT 24
Peak memory 197000 kb
Host smart-601e6051-c04c-42f3-9222-09ff83e2b677
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105932162 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown.1105932162
Directory /workspace/45.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_stress_all.811739213
Short name T170
Test name
Test status
Simulation time 19062501733 ps
CPU time 65.01 seconds
Started Jul 30 06:03:25 PM PDT 24
Finished Jul 30 06:04:30 PM PDT 24
Peak memory 198728 kb
Host smart-a76bd0c2-6b9f-43c6-9783-c6f06402d4b7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811739213 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.g
pio_stress_all.811739213
Directory /workspace/45.gpio_stress_all/latest

Test location /workspace/coverage/default/46.gpio_alert_test.132201904
Short name T49
Test name
Test status
Simulation time 44452554 ps
CPU time 0.56 seconds
Started Jul 30 06:03:32 PM PDT 24
Finished Jul 30 06:03:32 PM PDT 24
Peak memory 194460 kb
Host smart-a13a72c7-1a85-4f2f-accc-73726b55c543
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132201904 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_alert_test.132201904
Directory /workspace/46.gpio_alert_test/latest

Test location /workspace/coverage/default/46.gpio_dout_din_regs_random_rw.4063413130
Short name T484
Test name
Test status
Simulation time 120850380 ps
CPU time 0.71 seconds
Started Jul 30 06:03:10 PM PDT 24
Finished Jul 30 06:03:10 PM PDT 24
Peak memory 194716 kb
Host smart-0c2b5f10-22d7-4b51-ace9-1d983a00c42c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4063413130 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_dout_din_regs_random_rw.4063413130
Directory /workspace/46.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/46.gpio_filter_stress.1214214178
Short name T636
Test name
Test status
Simulation time 312644047 ps
CPU time 16.14 seconds
Started Jul 30 06:03:14 PM PDT 24
Finished Jul 30 06:03:30 PM PDT 24
Peak memory 197536 kb
Host smart-e9a9bba4-0d02-4cbd-804a-b5661da09b66
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214214178 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_filter_stre
ss.1214214178
Directory /workspace/46.gpio_filter_stress/latest

Test location /workspace/coverage/default/46.gpio_full_random.3194335286
Short name T398
Test name
Test status
Simulation time 72062348 ps
CPU time 0.73 seconds
Started Jul 30 06:03:13 PM PDT 24
Finished Jul 30 06:03:14 PM PDT 24
Peak memory 195236 kb
Host smart-ad65009d-fe87-4aa8-b90a-a6660a00c982
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194335286 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_full_random.3194335286
Directory /workspace/46.gpio_full_random/latest

Test location /workspace/coverage/default/46.gpio_intr_rand_pgm.2795391978
Short name T105
Test name
Test status
Simulation time 72942306 ps
CPU time 1.07 seconds
Started Jul 30 06:03:12 PM PDT 24
Finished Jul 30 06:03:13 PM PDT 24
Peak memory 196640 kb
Host smart-86382c4e-9a71-4440-beae-b313a8662338
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795391978 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_intr_rand_pgm.2795391978
Directory /workspace/46.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/46.gpio_intr_with_filter_rand_intr_event.2620334695
Short name T703
Test name
Test status
Simulation time 116783488 ps
CPU time 2.46 seconds
Started Jul 30 06:03:20 PM PDT 24
Finished Jul 30 06:03:22 PM PDT 24
Peak memory 198788 kb
Host smart-f5b3f657-4341-471b-8fc8-5f1ccdcd6965
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620334695 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 46.gpio_intr_with_filter_rand_intr_event.2620334695
Directory /workspace/46.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/46.gpio_rand_intr_trigger.395281231
Short name T284
Test name
Test status
Simulation time 392820279 ps
CPU time 1.97 seconds
Started Jul 30 06:03:40 PM PDT 24
Finished Jul 30 06:03:42 PM PDT 24
Peak memory 197828 kb
Host smart-7abca950-f037-4c7e-9811-6332a2bf0e0c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395281231 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_rand_intr_trigger.
395281231
Directory /workspace/46.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din.2725430545
Short name T168
Test name
Test status
Simulation time 225466003 ps
CPU time 1.31 seconds
Started Jul 30 06:03:10 PM PDT 24
Finished Jul 30 06:03:12 PM PDT 24
Peak memory 197556 kb
Host smart-f32caf9a-8bfe-4d05-a040-958422119989
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2725430545 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din.2725430545
Directory /workspace/46.gpio_random_dout_din/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din_no_pullup_pulldown.3285262953
Short name T286
Test name
Test status
Simulation time 101056456 ps
CPU time 1.1 seconds
Started Jul 30 06:03:10 PM PDT 24
Finished Jul 30 06:03:11 PM PDT 24
Peak memory 197196 kb
Host smart-a15f2060-31b6-4787-9b06-f8eaeeae631b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285262953 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din_no_pullu
p_pulldown.3285262953
Directory /workspace/46.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_random_long_reg_writes_reg_reads.4119266384
Short name T172
Test name
Test status
Simulation time 935605564 ps
CPU time 5.9 seconds
Started Jul 30 06:03:30 PM PDT 24
Finished Jul 30 06:03:37 PM PDT 24
Peak memory 198652 kb
Host smart-7ee6d428-a88c-4827-9d86-ee32b4f67f78
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119266384 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_ra
ndom_long_reg_writes_reg_reads.4119266384
Directory /workspace/46.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/46.gpio_smoke.4225880895
Short name T485
Test name
Test status
Simulation time 158988072 ps
CPU time 1.31 seconds
Started Jul 30 06:03:22 PM PDT 24
Finished Jul 30 06:03:24 PM PDT 24
Peak memory 196348 kb
Host smart-74daf58a-6c31-49e3-b562-84d11aba4265
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4225880895 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke.4225880895
Directory /workspace/46.gpio_smoke/latest

Test location /workspace/coverage/default/46.gpio_smoke_no_pullup_pulldown.1251110222
Short name T124
Test name
Test status
Simulation time 40781949 ps
CPU time 1.16 seconds
Started Jul 30 06:03:09 PM PDT 24
Finished Jul 30 06:03:10 PM PDT 24
Peak memory 196380 kb
Host smart-8a2350c1-b570-4db9-ae6c-dbdaf8c90954
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251110222 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown.1251110222
Directory /workspace/46.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_stress_all.1811877818
Short name T295
Test name
Test status
Simulation time 7567636623 ps
CPU time 97.16 seconds
Started Jul 30 06:03:07 PM PDT 24
Finished Jul 30 06:04:45 PM PDT 24
Peak memory 198768 kb
Host smart-fd445a47-646b-40ce-88be-2f9d19b5da2a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811877818 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.
gpio_stress_all.1811877818
Directory /workspace/46.gpio_stress_all/latest

Test location /workspace/coverage/default/47.gpio_alert_test.2005563411
Short name T629
Test name
Test status
Simulation time 16514373 ps
CPU time 0.59 seconds
Started Jul 30 06:03:29 PM PDT 24
Finished Jul 30 06:03:30 PM PDT 24
Peak memory 195180 kb
Host smart-a4f3808a-c28c-4d80-850d-bc659fcfaba7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005563411 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_alert_test.2005563411
Directory /workspace/47.gpio_alert_test/latest

Test location /workspace/coverage/default/47.gpio_dout_din_regs_random_rw.3947856792
Short name T399
Test name
Test status
Simulation time 60109364 ps
CPU time 0.66 seconds
Started Jul 30 06:03:12 PM PDT 24
Finished Jul 30 06:03:12 PM PDT 24
Peak memory 195248 kb
Host smart-46f360bc-bccb-45d3-b447-8389f5c3530b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3947856792 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_dout_din_regs_random_rw.3947856792
Directory /workspace/47.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/47.gpio_filter_stress.384964534
Short name T645
Test name
Test status
Simulation time 110867838 ps
CPU time 5.46 seconds
Started Jul 30 06:03:24 PM PDT 24
Finished Jul 30 06:03:30 PM PDT 24
Peak memory 196136 kb
Host smart-04a5c51a-77b1-4318-bf01-37688b0a5ed0
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384964534 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_filter_stres
s.384964534
Directory /workspace/47.gpio_filter_stress/latest

Test location /workspace/coverage/default/47.gpio_full_random.2142982063
Short name T674
Test name
Test status
Simulation time 49269960 ps
CPU time 0.65 seconds
Started Jul 30 06:03:35 PM PDT 24
Finished Jul 30 06:03:36 PM PDT 24
Peak memory 195572 kb
Host smart-258c637c-7526-470e-bd60-5d76e4428914
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142982063 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_full_random.2142982063
Directory /workspace/47.gpio_full_random/latest

Test location /workspace/coverage/default/47.gpio_intr_rand_pgm.1226477935
Short name T109
Test name
Test status
Simulation time 34814485 ps
CPU time 0.9 seconds
Started Jul 30 06:03:11 PM PDT 24
Finished Jul 30 06:03:12 PM PDT 24
Peak memory 196188 kb
Host smart-5520732f-3ac5-4a8e-bd67-e4da8111e8a9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226477935 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_intr_rand_pgm.1226477935
Directory /workspace/47.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/47.gpio_intr_with_filter_rand_intr_event.3396648185
Short name T483
Test name
Test status
Simulation time 38774400 ps
CPU time 1.69 seconds
Started Jul 30 06:03:16 PM PDT 24
Finished Jul 30 06:03:17 PM PDT 24
Peak memory 197388 kb
Host smart-b81981f5-6220-43af-930f-bb83e2632a8f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396648185 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 47.gpio_intr_with_filter_rand_intr_event.3396648185
Directory /workspace/47.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/47.gpio_rand_intr_trigger.435438956
Short name T625
Test name
Test status
Simulation time 67978994 ps
CPU time 1.93 seconds
Started Jul 30 06:03:14 PM PDT 24
Finished Jul 30 06:03:16 PM PDT 24
Peak memory 196436 kb
Host smart-1920dc93-4765-4087-8996-ebcf6c334488
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435438956 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_rand_intr_trigger.
435438956
Directory /workspace/47.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din.4146816240
Short name T246
Test name
Test status
Simulation time 263072785 ps
CPU time 1.3 seconds
Started Jul 30 06:03:11 PM PDT 24
Finished Jul 30 06:03:12 PM PDT 24
Peak memory 197592 kb
Host smart-4789b8f8-ed2b-45dc-bf15-bcc60eb7d5ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4146816240 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din.4146816240
Directory /workspace/47.gpio_random_dout_din/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din_no_pullup_pulldown.3084314889
Short name T106
Test name
Test status
Simulation time 51532644 ps
CPU time 1.02 seconds
Started Jul 30 06:03:15 PM PDT 24
Finished Jul 30 06:03:16 PM PDT 24
Peak memory 196556 kb
Host smart-1d8041ec-6b71-4a1c-9100-56988df090c6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084314889 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din_no_pullu
p_pulldown.3084314889
Directory /workspace/47.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_random_long_reg_writes_reg_reads.754246910
Short name T390
Test name
Test status
Simulation time 148645831 ps
CPU time 4.74 seconds
Started Jul 30 06:03:16 PM PDT 24
Finished Jul 30 06:03:21 PM PDT 24
Peak memory 198588 kb
Host smart-6f00d2d2-a49f-4d1d-9f93-32119a4db022
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754246910 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_ran
dom_long_reg_writes_reg_reads.754246910
Directory /workspace/47.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/47.gpio_smoke.3077154828
Short name T525
Test name
Test status
Simulation time 297151051 ps
CPU time 1.3 seconds
Started Jul 30 06:03:16 PM PDT 24
Finished Jul 30 06:03:18 PM PDT 24
Peak memory 196096 kb
Host smart-d9ff9dc8-8b4c-4b55-826e-f1351932444b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3077154828 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke.3077154828
Directory /workspace/47.gpio_smoke/latest

Test location /workspace/coverage/default/47.gpio_smoke_no_pullup_pulldown.2872487599
Short name T57
Test name
Test status
Simulation time 61071690 ps
CPU time 1.4 seconds
Started Jul 30 06:03:12 PM PDT 24
Finished Jul 30 06:03:14 PM PDT 24
Peak memory 198592 kb
Host smart-c305d2ed-75f5-4ff5-8f65-052857b2dc67
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872487599 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown.2872487599
Directory /workspace/47.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_stress_all.2655214985
Short name T3
Test name
Test status
Simulation time 58418025964 ps
CPU time 147.87 seconds
Started Jul 30 06:03:34 PM PDT 24
Finished Jul 30 06:06:02 PM PDT 24
Peak memory 192600 kb
Host smart-088fcf22-1391-4df6-9d9b-b02282a822fa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655214985 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.
gpio_stress_all.2655214985
Directory /workspace/47.gpio_stress_all/latest

Test location /workspace/coverage/default/48.gpio_alert_test.1080688142
Short name T466
Test name
Test status
Simulation time 13806297 ps
CPU time 0.59 seconds
Started Jul 30 06:03:13 PM PDT 24
Finished Jul 30 06:03:14 PM PDT 24
Peak memory 195172 kb
Host smart-515483e5-e685-4026-a3fa-a84a442b5246
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080688142 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_alert_test.1080688142
Directory /workspace/48.gpio_alert_test/latest

Test location /workspace/coverage/default/48.gpio_dout_din_regs_random_rw.524293678
Short name T665
Test name
Test status
Simulation time 78213912 ps
CPU time 0.93 seconds
Started Jul 30 06:03:14 PM PDT 24
Finished Jul 30 06:03:15 PM PDT 24
Peak memory 196644 kb
Host smart-a5919c7f-2bd9-4e2d-858f-36bc528ab43d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524293678 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_dout_din_regs_random_rw.524293678
Directory /workspace/48.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/48.gpio_filter_stress.3559022209
Short name T212
Test name
Test status
Simulation time 490605439 ps
CPU time 15.62 seconds
Started Jul 30 06:03:21 PM PDT 24
Finished Jul 30 06:03:37 PM PDT 24
Peak memory 198564 kb
Host smart-b451fee7-ccf3-46ee-bddc-90feb1775f67
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559022209 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_filter_stre
ss.3559022209
Directory /workspace/48.gpio_filter_stress/latest

Test location /workspace/coverage/default/48.gpio_full_random.1139052303
Short name T291
Test name
Test status
Simulation time 55732173 ps
CPU time 0.72 seconds
Started Jul 30 06:03:30 PM PDT 24
Finished Jul 30 06:03:31 PM PDT 24
Peak memory 195152 kb
Host smart-5857a31b-2ccf-45d6-8f38-c902f3b5529b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139052303 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_full_random.1139052303
Directory /workspace/48.gpio_full_random/latest

Test location /workspace/coverage/default/48.gpio_intr_rand_pgm.3058955282
Short name T460
Test name
Test status
Simulation time 119333692 ps
CPU time 1.27 seconds
Started Jul 30 06:03:21 PM PDT 24
Finished Jul 30 06:03:22 PM PDT 24
Peak memory 197380 kb
Host smart-48fec699-14cc-4e3f-bc04-458e0fc61c23
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058955282 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_intr_rand_pgm.3058955282
Directory /workspace/48.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/48.gpio_intr_with_filter_rand_intr_event.4198603019
Short name T707
Test name
Test status
Simulation time 62706378 ps
CPU time 1.41 seconds
Started Jul 30 06:03:17 PM PDT 24
Finished Jul 30 06:03:18 PM PDT 24
Peak memory 197064 kb
Host smart-eb3a691b-ea2f-41f7-b830-783bf58e6ad3
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198603019 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 48.gpio_intr_with_filter_rand_intr_event.4198603019
Directory /workspace/48.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/48.gpio_rand_intr_trigger.2011398225
Short name T355
Test name
Test status
Simulation time 140713870 ps
CPU time 3.26 seconds
Started Jul 30 06:03:22 PM PDT 24
Finished Jul 30 06:03:25 PM PDT 24
Peak memory 197188 kb
Host smart-d64131e3-fd34-4214-8414-c4080be7a195
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011398225 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_rand_intr_trigger
.2011398225
Directory /workspace/48.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din.2113538950
Short name T664
Test name
Test status
Simulation time 112149017 ps
CPU time 1.09 seconds
Started Jul 30 06:03:40 PM PDT 24
Finished Jul 30 06:03:41 PM PDT 24
Peak memory 196544 kb
Host smart-7484bc66-ed63-4c87-9697-0c86cf688d0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2113538950 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din.2113538950
Directory /workspace/48.gpio_random_dout_din/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din_no_pullup_pulldown.1244263232
Short name T298
Test name
Test status
Simulation time 74447168 ps
CPU time 0.95 seconds
Started Jul 30 06:03:13 PM PDT 24
Finished Jul 30 06:03:14 PM PDT 24
Peak memory 197284 kb
Host smart-3548c374-a4aa-40e2-be15-a2ec956243bc
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244263232 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din_no_pullu
p_pulldown.1244263232
Directory /workspace/48.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_random_long_reg_writes_reg_reads.3661900914
Short name T227
Test name
Test status
Simulation time 2265340411 ps
CPU time 3.06 seconds
Started Jul 30 06:03:33 PM PDT 24
Finished Jul 30 06:03:37 PM PDT 24
Peak memory 198684 kb
Host smart-07d51bbf-c181-4a7d-8490-3060ac87fb8e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661900914 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_ra
ndom_long_reg_writes_reg_reads.3661900914
Directory /workspace/48.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/48.gpio_smoke.2445608077
Short name T563
Test name
Test status
Simulation time 119439938 ps
CPU time 1.25 seconds
Started Jul 30 06:03:34 PM PDT 24
Finished Jul 30 06:03:35 PM PDT 24
Peak memory 197024 kb
Host smart-1bd9eb57-11fe-4b40-b19d-b582a1bdce45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2445608077 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke.2445608077
Directory /workspace/48.gpio_smoke/latest

Test location /workspace/coverage/default/48.gpio_smoke_no_pullup_pulldown.1088854579
Short name T319
Test name
Test status
Simulation time 1145884823 ps
CPU time 1.09 seconds
Started Jul 30 06:03:28 PM PDT 24
Finished Jul 30 06:03:30 PM PDT 24
Peak memory 196284 kb
Host smart-3c3c9c73-d677-4d01-8773-9a569fe24777
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088854579 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown.1088854579
Directory /workspace/48.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_stress_all.3100569162
Short name T278
Test name
Test status
Simulation time 49281480601 ps
CPU time 160.32 seconds
Started Jul 30 06:03:17 PM PDT 24
Finished Jul 30 06:05:57 PM PDT 24
Peak memory 198844 kb
Host smart-163ab75d-5fbe-4f78-a85b-0e504b12df9e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100569162 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.
gpio_stress_all.3100569162
Directory /workspace/48.gpio_stress_all/latest

Test location /workspace/coverage/default/49.gpio_alert_test.910465655
Short name T40
Test name
Test status
Simulation time 33012402 ps
CPU time 0.58 seconds
Started Jul 30 06:03:22 PM PDT 24
Finished Jul 30 06:03:23 PM PDT 24
Peak memory 194476 kb
Host smart-df1e1a29-f256-445d-a27a-06e9b3c961e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910465655 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_alert_test.910465655
Directory /workspace/49.gpio_alert_test/latest

Test location /workspace/coverage/default/49.gpio_dout_din_regs_random_rw.3138475137
Short name T417
Test name
Test status
Simulation time 23954832 ps
CPU time 0.71 seconds
Started Jul 30 06:03:31 PM PDT 24
Finished Jul 30 06:03:32 PM PDT 24
Peak memory 194512 kb
Host smart-c4c0173a-2f74-49b6-bb87-a9e4110cd068
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3138475137 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_dout_din_regs_random_rw.3138475137
Directory /workspace/49.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/49.gpio_filter_stress.2427275843
Short name T684
Test name
Test status
Simulation time 949755242 ps
CPU time 14.77 seconds
Started Jul 30 06:03:33 PM PDT 24
Finished Jul 30 06:03:47 PM PDT 24
Peak memory 197432 kb
Host smart-5c9045de-a080-467e-b919-57849fda234c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427275843 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_filter_stre
ss.2427275843
Directory /workspace/49.gpio_filter_stress/latest

Test location /workspace/coverage/default/49.gpio_full_random.3295741672
Short name T250
Test name
Test status
Simulation time 46454053 ps
CPU time 0.92 seconds
Started Jul 30 06:03:28 PM PDT 24
Finished Jul 30 06:03:29 PM PDT 24
Peak memory 197512 kb
Host smart-273fe85e-b3e9-4c8f-9a81-09a3f7b51478
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295741672 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_full_random.3295741672
Directory /workspace/49.gpio_full_random/latest

Test location /workspace/coverage/default/49.gpio_intr_rand_pgm.2614622036
Short name T425
Test name
Test status
Simulation time 137959122 ps
CPU time 0.76 seconds
Started Jul 30 06:03:15 PM PDT 24
Finished Jul 30 06:03:16 PM PDT 24
Peak memory 194788 kb
Host smart-cc018545-0a6d-40a9-9ce7-b2e22c80bff5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614622036 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_intr_rand_pgm.2614622036
Directory /workspace/49.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/49.gpio_intr_with_filter_rand_intr_event.1581040259
Short name T375
Test name
Test status
Simulation time 189559099 ps
CPU time 2 seconds
Started Jul 30 06:03:33 PM PDT 24
Finished Jul 30 06:03:35 PM PDT 24
Peak memory 197096 kb
Host smart-2e9c1c4e-4285-4587-b459-4366a814a904
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581040259 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 49.gpio_intr_with_filter_rand_intr_event.1581040259
Directory /workspace/49.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/49.gpio_rand_intr_trigger.652945331
Short name T145
Test name
Test status
Simulation time 560853822 ps
CPU time 1.7 seconds
Started Jul 30 06:03:40 PM PDT 24
Finished Jul 30 06:03:41 PM PDT 24
Peak memory 197056 kb
Host smart-02b763c9-c37c-46c4-baf9-960d08f7558a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652945331 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_rand_intr_trigger.
652945331
Directory /workspace/49.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din.18550007
Short name T581
Test name
Test status
Simulation time 70764360 ps
CPU time 1.27 seconds
Started Jul 30 06:03:31 PM PDT 24
Finished Jul 30 06:03:32 PM PDT 24
Peak memory 198696 kb
Host smart-5fde2b30-2fbc-4e05-a41a-f94e0e561cdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18550007 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din.18550007
Directory /workspace/49.gpio_random_dout_din/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din_no_pullup_pulldown.1997871574
Short name T660
Test name
Test status
Simulation time 44562969 ps
CPU time 0.73 seconds
Started Jul 30 06:03:38 PM PDT 24
Finished Jul 30 06:03:39 PM PDT 24
Peak memory 195896 kb
Host smart-c994e571-a235-402e-af6a-cc83439d73ee
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997871574 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din_no_pullu
p_pulldown.1997871574
Directory /workspace/49.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_random_long_reg_writes_reg_reads.1574267722
Short name T464
Test name
Test status
Simulation time 1605441297 ps
CPU time 3.89 seconds
Started Jul 30 06:03:18 PM PDT 24
Finished Jul 30 06:03:22 PM PDT 24
Peak memory 198524 kb
Host smart-739439a9-d5d3-426d-a398-abcb5f5c4fb1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574267722 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_ra
ndom_long_reg_writes_reg_reads.1574267722
Directory /workspace/49.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/49.gpio_smoke.443929029
Short name T306
Test name
Test status
Simulation time 252398124 ps
CPU time 1.19 seconds
Started Jul 30 06:03:29 PM PDT 24
Finished Jul 30 06:03:31 PM PDT 24
Peak memory 197108 kb
Host smart-33d3fd6f-d1cf-4c9a-b5f5-e88f1df2e88d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=443929029 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke.443929029
Directory /workspace/49.gpio_smoke/latest

Test location /workspace/coverage/default/49.gpio_smoke_no_pullup_pulldown.3041570173
Short name T599
Test name
Test status
Simulation time 37882631 ps
CPU time 1.05 seconds
Started Jul 30 06:03:14 PM PDT 24
Finished Jul 30 06:03:15 PM PDT 24
Peak memory 196452 kb
Host smart-7665857a-d94a-4efe-831b-e5feb2753327
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041570173 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown.3041570173
Directory /workspace/49.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_stress_all.3945543956
Short name T620
Test name
Test status
Simulation time 27107508286 ps
CPU time 53.95 seconds
Started Jul 30 06:03:28 PM PDT 24
Finished Jul 30 06:04:22 PM PDT 24
Peak memory 198748 kb
Host smart-0eeed9b8-150f-4575-bf75-d4d1fc651e21
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945543956 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.
gpio_stress_all.3945543956
Directory /workspace/49.gpio_stress_all/latest

Test location /workspace/coverage/default/5.gpio_alert_test.2258922098
Short name T69
Test name
Test status
Simulation time 20793487 ps
CPU time 0.56 seconds
Started Jul 30 06:01:51 PM PDT 24
Finished Jul 30 06:01:52 PM PDT 24
Peak memory 194508 kb
Host smart-45aa91bb-3a87-42f4-a1a1-a60fa2a9bc8a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258922098 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_alert_test.2258922098
Directory /workspace/5.gpio_alert_test/latest

Test location /workspace/coverage/default/5.gpio_dout_din_regs_random_rw.2744910405
Short name T643
Test name
Test status
Simulation time 173702381 ps
CPU time 0.93 seconds
Started Jul 30 06:01:54 PM PDT 24
Finished Jul 30 06:01:55 PM PDT 24
Peak memory 197104 kb
Host smart-046bc37b-0a15-42b4-96ba-f7749815bce0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2744910405 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_dout_din_regs_random_rw.2744910405
Directory /workspace/5.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/5.gpio_filter_stress.937130463
Short name T692
Test name
Test status
Simulation time 4108778915 ps
CPU time 22.73 seconds
Started Jul 30 06:01:57 PM PDT 24
Finished Jul 30 06:02:20 PM PDT 24
Peak memory 197608 kb
Host smart-959f8006-e949-4993-9f1a-e73eb20a4ad3
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937130463 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_filter_stress
.937130463
Directory /workspace/5.gpio_filter_stress/latest

Test location /workspace/coverage/default/5.gpio_full_random.182416364
Short name T157
Test name
Test status
Simulation time 132050498 ps
CPU time 0.7 seconds
Started Jul 30 06:01:47 PM PDT 24
Finished Jul 30 06:01:48 PM PDT 24
Peak memory 195992 kb
Host smart-fb98315a-d201-4b5f-8e17-d343daa7d8a7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182416364 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_full_random.182416364
Directory /workspace/5.gpio_full_random/latest

Test location /workspace/coverage/default/5.gpio_intr_rand_pgm.1457677051
Short name T422
Test name
Test status
Simulation time 78508851 ps
CPU time 0.87 seconds
Started Jul 30 06:01:57 PM PDT 24
Finished Jul 30 06:01:58 PM PDT 24
Peak memory 196092 kb
Host smart-a69ac6bd-7f80-475b-8433-7d19f6f279c0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457677051 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_intr_rand_pgm.1457677051
Directory /workspace/5.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/5.gpio_intr_with_filter_rand_intr_event.2103106958
Short name T586
Test name
Test status
Simulation time 157463094 ps
CPU time 1.9 seconds
Started Jul 30 06:02:01 PM PDT 24
Finished Jul 30 06:02:03 PM PDT 24
Peak memory 198584 kb
Host smart-84cd674d-bc56-44cb-adde-60b5552c64ff
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103106958 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.gpio_intr_with_filter_rand_intr_event.2103106958
Directory /workspace/5.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/5.gpio_rand_intr_trigger.1789342078
Short name T574
Test name
Test status
Simulation time 120774384 ps
CPU time 3.22 seconds
Started Jul 30 06:01:44 PM PDT 24
Finished Jul 30 06:01:47 PM PDT 24
Peak memory 197916 kb
Host smart-dcecd10a-7d92-4289-9331-7a08b7979d3c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789342078 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_rand_intr_trigger.
1789342078
Directory /workspace/5.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din.2342889718
Short name T199
Test name
Test status
Simulation time 101567628 ps
CPU time 1.23 seconds
Started Jul 30 06:01:53 PM PDT 24
Finished Jul 30 06:01:55 PM PDT 24
Peak memory 196428 kb
Host smart-77737965-256a-44ee-a099-b98fba224c19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2342889718 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din.2342889718
Directory /workspace/5.gpio_random_dout_din/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din_no_pullup_pulldown.2324015363
Short name T305
Test name
Test status
Simulation time 220433718 ps
CPU time 1.29 seconds
Started Jul 30 06:02:00 PM PDT 24
Finished Jul 30 06:02:06 PM PDT 24
Peak memory 197460 kb
Host smart-a37e9d2d-728b-4613-baff-c4bf8f4e8f89
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324015363 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din_no_pullup
_pulldown.2324015363
Directory /workspace/5.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_random_long_reg_writes_reg_reads.3864794483
Short name T411
Test name
Test status
Simulation time 1112288296 ps
CPU time 4.23 seconds
Started Jul 30 06:01:54 PM PDT 24
Finished Jul 30 06:01:58 PM PDT 24
Peak memory 198588 kb
Host smart-ddb03afa-e291-4564-93ae-bdba9c8857a2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864794483 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_ran
dom_long_reg_writes_reg_reads.3864794483
Directory /workspace/5.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/5.gpio_smoke.211327063
Short name T203
Test name
Test status
Simulation time 201471251 ps
CPU time 1.06 seconds
Started Jul 30 06:01:49 PM PDT 24
Finished Jul 30 06:01:50 PM PDT 24
Peak memory 196056 kb
Host smart-3a4ffdf6-0269-473f-a7ff-29fecd4def53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=211327063 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke.211327063
Directory /workspace/5.gpio_smoke/latest

Test location /workspace/coverage/default/5.gpio_smoke_no_pullup_pulldown.2810452871
Short name T677
Test name
Test status
Simulation time 22223799 ps
CPU time 0.83 seconds
Started Jul 30 06:01:59 PM PDT 24
Finished Jul 30 06:02:00 PM PDT 24
Peak memory 195856 kb
Host smart-3e546282-8452-430e-84b3-8fec7a5470c1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810452871 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown.2810452871
Directory /workspace/5.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_stress_all.4070512111
Short name T384
Test name
Test status
Simulation time 11028374671 ps
CPU time 84.26 seconds
Started Jul 30 06:01:48 PM PDT 24
Finished Jul 30 06:03:13 PM PDT 24
Peak memory 198760 kb
Host smart-a6e32a98-ea3f-44eb-bcec-2376e1e4f1c1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070512111 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.g
pio_stress_all.4070512111
Directory /workspace/5.gpio_stress_all/latest

Test location /workspace/coverage/default/6.gpio_alert_test.4029700133
Short name T638
Test name
Test status
Simulation time 14317793 ps
CPU time 0.59 seconds
Started Jul 30 06:02:01 PM PDT 24
Finished Jul 30 06:02:02 PM PDT 24
Peak memory 194524 kb
Host smart-24a5d3bb-b81d-4736-84cc-04453b71fc83
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029700133 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_alert_test.4029700133
Directory /workspace/6.gpio_alert_test/latest

Test location /workspace/coverage/default/6.gpio_dout_din_regs_random_rw.980819380
Short name T391
Test name
Test status
Simulation time 208787371 ps
CPU time 0.8 seconds
Started Jul 30 06:02:00 PM PDT 24
Finished Jul 30 06:02:01 PM PDT 24
Peak memory 196480 kb
Host smart-b63d180d-8d7b-4fbe-96eb-7f10933c7153
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=980819380 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_dout_din_regs_random_rw.980819380
Directory /workspace/6.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/6.gpio_filter_stress.2440764558
Short name T441
Test name
Test status
Simulation time 710534849 ps
CPU time 19.78 seconds
Started Jul 30 06:01:58 PM PDT 24
Finished Jul 30 06:02:18 PM PDT 24
Peak memory 197544 kb
Host smart-d2f10875-211d-457f-ae72-4a35da66bf76
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440764558 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_filter_stres
s.2440764558
Directory /workspace/6.gpio_filter_stress/latest

Test location /workspace/coverage/default/6.gpio_full_random.995053278
Short name T347
Test name
Test status
Simulation time 83833884 ps
CPU time 1.03 seconds
Started Jul 30 06:01:57 PM PDT 24
Finished Jul 30 06:01:58 PM PDT 24
Peak memory 197144 kb
Host smart-70c3721c-40dd-4c11-9381-bf05ee4b2e04
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995053278 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_full_random.995053278
Directory /workspace/6.gpio_full_random/latest

Test location /workspace/coverage/default/6.gpio_intr_rand_pgm.70349629
Short name T503
Test name
Test status
Simulation time 50510728 ps
CPU time 0.75 seconds
Started Jul 30 06:01:49 PM PDT 24
Finished Jul 30 06:01:50 PM PDT 24
Peak memory 195964 kb
Host smart-4bf04412-89be-4876-8787-1eb6478bb670
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70349629 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_intr_rand_pgm.70349629
Directory /workspace/6.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/6.gpio_intr_with_filter_rand_intr_event.4254612890
Short name T418
Test name
Test status
Simulation time 49896787 ps
CPU time 1.92 seconds
Started Jul 30 06:01:49 PM PDT 24
Finished Jul 30 06:01:51 PM PDT 24
Peak memory 196872 kb
Host smart-5c1409ff-00c2-4232-9c61-cb53490d2352
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254612890 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 6.gpio_intr_with_filter_rand_intr_event.4254612890
Directory /workspace/6.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/6.gpio_rand_intr_trigger.3574733543
Short name T676
Test name
Test status
Simulation time 164232371 ps
CPU time 3.46 seconds
Started Jul 30 06:01:53 PM PDT 24
Finished Jul 30 06:01:57 PM PDT 24
Peak memory 197624 kb
Host smart-8ac14155-a4f5-4531-bdbc-861e02c5c35a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574733543 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_rand_intr_trigger.
3574733543
Directory /workspace/6.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din.1602660149
Short name T380
Test name
Test status
Simulation time 73552870 ps
CPU time 0.69 seconds
Started Jul 30 06:01:49 PM PDT 24
Finished Jul 30 06:01:50 PM PDT 24
Peak memory 195012 kb
Host smart-ab0c97dd-5734-4975-b0ee-dfb7192d0007
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1602660149 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din.1602660149
Directory /workspace/6.gpio_random_dout_din/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din_no_pullup_pulldown.4179437494
Short name T132
Test name
Test status
Simulation time 63980981 ps
CPU time 0.67 seconds
Started Jul 30 06:01:51 PM PDT 24
Finished Jul 30 06:01:51 PM PDT 24
Peak memory 194912 kb
Host smart-2b1a6c1e-ac38-4550-89ba-87386e6b5206
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179437494 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din_no_pullup
_pulldown.4179437494
Directory /workspace/6.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_random_long_reg_writes_reg_reads.1421315645
Short name T179
Test name
Test status
Simulation time 82142226 ps
CPU time 1.55 seconds
Started Jul 30 06:01:54 PM PDT 24
Finished Jul 30 06:01:55 PM PDT 24
Peak memory 198528 kb
Host smart-95d2977b-4eeb-4f78-8f45-100731e10264
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421315645 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_ran
dom_long_reg_writes_reg_reads.1421315645
Directory /workspace/6.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/6.gpio_smoke.1031001738
Short name T247
Test name
Test status
Simulation time 494489872 ps
CPU time 0.95 seconds
Started Jul 30 06:01:48 PM PDT 24
Finished Jul 30 06:01:50 PM PDT 24
Peak memory 197040 kb
Host smart-91c7e61a-d38d-4ba8-8948-5985cbf571e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1031001738 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke.1031001738
Directory /workspace/6.gpio_smoke/latest

Test location /workspace/coverage/default/6.gpio_smoke_no_pullup_pulldown.1435876312
Short name T713
Test name
Test status
Simulation time 85053369 ps
CPU time 1.46 seconds
Started Jul 30 06:02:00 PM PDT 24
Finished Jul 30 06:02:07 PM PDT 24
Peak memory 197560 kb
Host smart-82e95ca1-00e1-4d67-8f19-61ec1d6ba516
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435876312 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown.1435876312
Directory /workspace/6.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_stress_all.3561892649
Short name T467
Test name
Test status
Simulation time 28632170489 ps
CPU time 100.56 seconds
Started Jul 30 06:02:00 PM PDT 24
Finished Jul 30 06:03:40 PM PDT 24
Peak memory 198744 kb
Host smart-0fb7e75e-4870-49fb-8072-e6eb0ec2f449
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561892649 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.g
pio_stress_all.3561892649
Directory /workspace/6.gpio_stress_all/latest

Test location /workspace/coverage/default/7.gpio_alert_test.1313005650
Short name T160
Test name
Test status
Simulation time 14070365 ps
CPU time 0.61 seconds
Started Jul 30 06:01:55 PM PDT 24
Finished Jul 30 06:01:56 PM PDT 24
Peak memory 194484 kb
Host smart-f942f0f7-b616-4691-b6a8-6f84fac7a1c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313005650 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_alert_test.1313005650
Directory /workspace/7.gpio_alert_test/latest

Test location /workspace/coverage/default/7.gpio_dout_din_regs_random_rw.334980345
Short name T553
Test name
Test status
Simulation time 68505959 ps
CPU time 0.61 seconds
Started Jul 30 06:02:05 PM PDT 24
Finished Jul 30 06:02:06 PM PDT 24
Peak memory 194544 kb
Host smart-5b0f0f46-f647-431f-b5c9-06843e37a947
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=334980345 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_dout_din_regs_random_rw.334980345
Directory /workspace/7.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/7.gpio_filter_stress.304809887
Short name T529
Test name
Test status
Simulation time 91252531 ps
CPU time 4.57 seconds
Started Jul 30 06:01:57 PM PDT 24
Finished Jul 30 06:02:02 PM PDT 24
Peak memory 196404 kb
Host smart-011e39d1-72b0-4ecc-a925-531621aa308e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304809887 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_filter_stress
.304809887
Directory /workspace/7.gpio_filter_stress/latest

Test location /workspace/coverage/default/7.gpio_full_random.1701040897
Short name T379
Test name
Test status
Simulation time 63571426 ps
CPU time 1 seconds
Started Jul 30 06:01:58 PM PDT 24
Finished Jul 30 06:01:59 PM PDT 24
Peak memory 197044 kb
Host smart-dd32a677-ecc6-428a-b39c-85d9c4aceecd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701040897 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_full_random.1701040897
Directory /workspace/7.gpio_full_random/latest

Test location /workspace/coverage/default/7.gpio_intr_rand_pgm.2186503443
Short name T381
Test name
Test status
Simulation time 24851670 ps
CPU time 0.8 seconds
Started Jul 30 06:01:54 PM PDT 24
Finished Jul 30 06:01:55 PM PDT 24
Peak memory 196144 kb
Host smart-8c28f52e-cc98-407c-888b-af9bd7e0159f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186503443 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_intr_rand_pgm.2186503443
Directory /workspace/7.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/7.gpio_intr_with_filter_rand_intr_event.1369124586
Short name T714
Test name
Test status
Simulation time 1193539642 ps
CPU time 2.72 seconds
Started Jul 30 06:01:59 PM PDT 24
Finished Jul 30 06:02:01 PM PDT 24
Peak memory 198588 kb
Host smart-4914bc4f-72ba-4104-8283-abfb28db3ff8
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369124586 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.gpio_intr_with_filter_rand_intr_event.1369124586
Directory /workspace/7.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/7.gpio_rand_intr_trigger.3799452534
Short name T434
Test name
Test status
Simulation time 47830321 ps
CPU time 1.34 seconds
Started Jul 30 06:01:54 PM PDT 24
Finished Jul 30 06:01:56 PM PDT 24
Peak memory 197004 kb
Host smart-14039073-140e-4e86-97a3-f588538869b9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799452534 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_rand_intr_trigger.
3799452534
Directory /workspace/7.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din.1271691329
Short name T236
Test name
Test status
Simulation time 103595598 ps
CPU time 1.05 seconds
Started Jul 30 06:02:04 PM PDT 24
Finished Jul 30 06:02:05 PM PDT 24
Peak memory 196652 kb
Host smart-f147a8a7-0eae-4430-863f-fb3ce350aab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1271691329 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din.1271691329
Directory /workspace/7.gpio_random_dout_din/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din_no_pullup_pulldown.3769590363
Short name T541
Test name
Test status
Simulation time 87877879 ps
CPU time 0.72 seconds
Started Jul 30 06:01:55 PM PDT 24
Finished Jul 30 06:01:56 PM PDT 24
Peak memory 194856 kb
Host smart-c2679e92-64ee-4236-9152-0dfad63b75ef
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769590363 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din_no_pullup
_pulldown.3769590363
Directory /workspace/7.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_random_long_reg_writes_reg_reads.3008107004
Short name T255
Test name
Test status
Simulation time 537620226 ps
CPU time 4.88 seconds
Started Jul 30 06:01:57 PM PDT 24
Finished Jul 30 06:02:02 PM PDT 24
Peak memory 197684 kb
Host smart-133f014b-0987-4317-8beb-b6c2daf14551
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008107004 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_ran
dom_long_reg_writes_reg_reads.3008107004
Directory /workspace/7.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/7.gpio_smoke.1175051357
Short name T458
Test name
Test status
Simulation time 131487560 ps
CPU time 1.07 seconds
Started Jul 30 06:02:01 PM PDT 24
Finished Jul 30 06:02:02 PM PDT 24
Peak memory 196352 kb
Host smart-11a5735d-d1b9-4d96-877a-64067cc38b01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1175051357 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke.1175051357
Directory /workspace/7.gpio_smoke/latest

Test location /workspace/coverage/default/7.gpio_smoke_no_pullup_pulldown.310059262
Short name T117
Test name
Test status
Simulation time 164872279 ps
CPU time 1.47 seconds
Started Jul 30 06:01:56 PM PDT 24
Finished Jul 30 06:01:58 PM PDT 24
Peak memory 197356 kb
Host smart-d2cc379a-347d-4abd-9c21-95598524f45b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310059262 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown.310059262
Directory /workspace/7.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_stress_all.3088102553
Short name T395
Test name
Test status
Simulation time 4505047916 ps
CPU time 46.12 seconds
Started Jul 30 06:01:53 PM PDT 24
Finished Jul 30 06:02:40 PM PDT 24
Peak memory 198724 kb
Host smart-293e34b0-f109-41a2-976c-49dd4f6bddbc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088102553 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.g
pio_stress_all.3088102553
Directory /workspace/7.gpio_stress_all/latest

Test location /workspace/coverage/default/8.gpio_alert_test.4274139406
Short name T228
Test name
Test status
Simulation time 15059721 ps
CPU time 0.58 seconds
Started Jul 30 06:01:54 PM PDT 24
Finished Jul 30 06:01:54 PM PDT 24
Peak memory 194496 kb
Host smart-ccec6440-a64e-47b7-8b5b-a04587f097d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274139406 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_alert_test.4274139406
Directory /workspace/8.gpio_alert_test/latest

Test location /workspace/coverage/default/8.gpio_dout_din_regs_random_rw.3654542013
Short name T491
Test name
Test status
Simulation time 18646950 ps
CPU time 0.66 seconds
Started Jul 30 06:02:00 PM PDT 24
Finished Jul 30 06:02:01 PM PDT 24
Peak memory 195296 kb
Host smart-d0eebd09-ec8a-4883-836a-0e24be9ed977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3654542013 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_dout_din_regs_random_rw.3654542013
Directory /workspace/8.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/8.gpio_filter_stress.489051932
Short name T421
Test name
Test status
Simulation time 773183434 ps
CPU time 19.53 seconds
Started Jul 30 06:01:55 PM PDT 24
Finished Jul 30 06:02:14 PM PDT 24
Peak memory 198604 kb
Host smart-b68e7370-cf5b-49c3-b012-e010ea80fb46
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489051932 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_filter_stress
.489051932
Directory /workspace/8.gpio_filter_stress/latest

Test location /workspace/coverage/default/8.gpio_full_random.2287531967
Short name T627
Test name
Test status
Simulation time 94168856 ps
CPU time 0.92 seconds
Started Jul 30 06:01:59 PM PDT 24
Finished Jul 30 06:02:00 PM PDT 24
Peak memory 196436 kb
Host smart-b690114a-11ff-40eb-b3ef-6edf45f1671d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287531967 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_full_random.2287531967
Directory /workspace/8.gpio_full_random/latest

Test location /workspace/coverage/default/8.gpio_intr_rand_pgm.2258272882
Short name T473
Test name
Test status
Simulation time 21827855 ps
CPU time 0.76 seconds
Started Jul 30 06:01:57 PM PDT 24
Finished Jul 30 06:01:58 PM PDT 24
Peak memory 196024 kb
Host smart-0a148258-b4db-4ddc-9b2b-c8b6caef013b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258272882 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_intr_rand_pgm.2258272882
Directory /workspace/8.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/8.gpio_intr_with_filter_rand_intr_event.974741170
Short name T21
Test name
Test status
Simulation time 212911572 ps
CPU time 2.19 seconds
Started Jul 30 06:01:58 PM PDT 24
Finished Jul 30 06:02:01 PM PDT 24
Peak memory 198676 kb
Host smart-331f4bee-8373-4ad7-b9b7-5e9d25bf3c03
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974741170 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 8.gpio_intr_with_filter_rand_intr_event.974741170
Directory /workspace/8.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/8.gpio_rand_intr_trigger.3159967053
Short name T239
Test name
Test status
Simulation time 40280281 ps
CPU time 0.92 seconds
Started Jul 30 06:01:56 PM PDT 24
Finished Jul 30 06:01:57 PM PDT 24
Peak memory 195884 kb
Host smart-b0d37021-8a2e-455f-b809-c0915b36da0b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159967053 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_rand_intr_trigger.
3159967053
Directory /workspace/8.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din.3176380460
Short name T336
Test name
Test status
Simulation time 211325346 ps
CPU time 1.18 seconds
Started Jul 30 06:01:57 PM PDT 24
Finished Jul 30 06:01:59 PM PDT 24
Peak memory 197540 kb
Host smart-89027acf-ea97-4c32-abdc-9d2eeb2ac726
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3176380460 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din.3176380460
Directory /workspace/8.gpio_random_dout_din/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din_no_pullup_pulldown.1114059934
Short name T573
Test name
Test status
Simulation time 60517195 ps
CPU time 1.14 seconds
Started Jul 30 06:01:56 PM PDT 24
Finished Jul 30 06:01:57 PM PDT 24
Peak memory 196600 kb
Host smart-e67b76a4-805d-4a12-b48f-2447916a4957
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114059934 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din_no_pullup
_pulldown.1114059934
Directory /workspace/8.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_random_long_reg_writes_reg_reads.1251778763
Short name T406
Test name
Test status
Simulation time 2156253209 ps
CPU time 5.89 seconds
Started Jul 30 06:02:01 PM PDT 24
Finished Jul 30 06:02:07 PM PDT 24
Peak memory 198696 kb
Host smart-35168a93-a356-4e4c-9655-4e9e230173e1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251778763 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_ran
dom_long_reg_writes_reg_reads.1251778763
Directory /workspace/8.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/8.gpio_smoke.2656668026
Short name T534
Test name
Test status
Simulation time 78062089 ps
CPU time 1.29 seconds
Started Jul 30 06:01:59 PM PDT 24
Finished Jul 30 06:02:00 PM PDT 24
Peak memory 197420 kb
Host smart-71704f83-0118-47af-a96f-f801f2dc68af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2656668026 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke.2656668026
Directory /workspace/8.gpio_smoke/latest

Test location /workspace/coverage/default/8.gpio_smoke_no_pullup_pulldown.2325952009
Short name T171
Test name
Test status
Simulation time 474529096 ps
CPU time 1.28 seconds
Started Jul 30 06:01:57 PM PDT 24
Finished Jul 30 06:01:59 PM PDT 24
Peak memory 197280 kb
Host smart-e424ed0b-1f7a-48f1-a19f-539e5e3454a7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325952009 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown.2325952009
Directory /workspace/8.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_stress_all.2357012754
Short name T531
Test name
Test status
Simulation time 22828742683 ps
CPU time 157.74 seconds
Started Jul 30 06:01:51 PM PDT 24
Finished Jul 30 06:04:28 PM PDT 24
Peak memory 198760 kb
Host smart-11236571-a580-4ad7-982d-46ba5f0792c7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357012754 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.g
pio_stress_all.2357012754
Directory /workspace/8.gpio_stress_all/latest

Test location /workspace/coverage/default/9.gpio_alert_test.2638229807
Short name T647
Test name
Test status
Simulation time 44365378 ps
CPU time 0.6 seconds
Started Jul 30 06:02:01 PM PDT 24
Finished Jul 30 06:02:02 PM PDT 24
Peak memory 194700 kb
Host smart-5b7eb843-47b3-4265-8260-5b84e8042b10
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638229807 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_alert_test.2638229807
Directory /workspace/9.gpio_alert_test/latest

Test location /workspace/coverage/default/9.gpio_dout_din_regs_random_rw.673224654
Short name T566
Test name
Test status
Simulation time 24294846 ps
CPU time 0.74 seconds
Started Jul 30 06:01:58 PM PDT 24
Finished Jul 30 06:01:59 PM PDT 24
Peak memory 194708 kb
Host smart-3d37c74a-a7c8-459e-a595-316cd8abc0e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=673224654 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_dout_din_regs_random_rw.673224654
Directory /workspace/9.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/9.gpio_filter_stress.2693850936
Short name T427
Test name
Test status
Simulation time 5333107811 ps
CPU time 17.07 seconds
Started Jul 30 06:01:57 PM PDT 24
Finished Jul 30 06:02:14 PM PDT 24
Peak memory 197468 kb
Host smart-d4827291-4cfa-49b9-b1aa-75948ac80585
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693850936 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_filter_stres
s.2693850936
Directory /workspace/9.gpio_filter_stress/latest

Test location /workspace/coverage/default/9.gpio_full_random.3659062079
Short name T624
Test name
Test status
Simulation time 145199331 ps
CPU time 1.01 seconds
Started Jul 30 06:01:57 PM PDT 24
Finished Jul 30 06:01:58 PM PDT 24
Peak memory 197564 kb
Host smart-d7ef7f00-458e-468d-b32c-3536c1738c22
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659062079 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_full_random.3659062079
Directory /workspace/9.gpio_full_random/latest

Test location /workspace/coverage/default/9.gpio_intr_rand_pgm.3657363672
Short name T409
Test name
Test status
Simulation time 105550549 ps
CPU time 0.8 seconds
Started Jul 30 06:02:06 PM PDT 24
Finished Jul 30 06:02:06 PM PDT 24
Peak memory 196004 kb
Host smart-f4b8e72f-b984-4809-93fb-ea9c71cdda16
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657363672 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_intr_rand_pgm.3657363672
Directory /workspace/9.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/9.gpio_intr_with_filter_rand_intr_event.4014073220
Short name T261
Test name
Test status
Simulation time 54075358 ps
CPU time 1.09 seconds
Started Jul 30 06:01:51 PM PDT 24
Finished Jul 30 06:01:53 PM PDT 24
Peak memory 197756 kb
Host smart-41cdedd2-8446-4b8b-bea0-facf0e9707aa
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014073220 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.gpio_intr_with_filter_rand_intr_event.4014073220
Directory /workspace/9.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/9.gpio_rand_intr_trigger.2199724592
Short name T499
Test name
Test status
Simulation time 90766930 ps
CPU time 2.07 seconds
Started Jul 30 06:01:57 PM PDT 24
Finished Jul 30 06:02:00 PM PDT 24
Peak memory 196464 kb
Host smart-346931b6-3a76-4e1e-a6d7-3dd5959495b6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199724592 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_rand_intr_trigger.
2199724592
Directory /workspace/9.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din.839475033
Short name T358
Test name
Test status
Simulation time 341597204 ps
CPU time 0.99 seconds
Started Jul 30 06:01:58 PM PDT 24
Finished Jul 30 06:01:59 PM PDT 24
Peak memory 197116 kb
Host smart-bb0da596-90c2-4645-9981-bb68fa532683
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=839475033 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din.839475033
Directory /workspace/9.gpio_random_dout_din/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din_no_pullup_pulldown.1514585639
Short name T479
Test name
Test status
Simulation time 18992129 ps
CPU time 0.76 seconds
Started Jul 30 06:02:00 PM PDT 24
Finished Jul 30 06:02:01 PM PDT 24
Peak memory 195936 kb
Host smart-27d033cf-a31e-4db5-b1b0-ef81ca153237
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514585639 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din_no_pullup
_pulldown.1514585639
Directory /workspace/9.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_random_long_reg_writes_reg_reads.3654181886
Short name T139
Test name
Test status
Simulation time 58349161 ps
CPU time 2.76 seconds
Started Jul 30 06:02:01 PM PDT 24
Finished Jul 30 06:02:04 PM PDT 24
Peak memory 198520 kb
Host smart-a1a3cac5-a157-4e36-8896-16b16e964ee2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654181886 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_ran
dom_long_reg_writes_reg_reads.3654181886
Directory /workspace/9.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/9.gpio_smoke.1973634080
Short name T469
Test name
Test status
Simulation time 395248724 ps
CPU time 0.88 seconds
Started Jul 30 06:02:00 PM PDT 24
Finished Jul 30 06:02:02 PM PDT 24
Peak memory 195920 kb
Host smart-f0a53ffa-f34c-4084-b7f7-5da13fd1e301
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973634080 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke.1973634080
Directory /workspace/9.gpio_smoke/latest

Test location /workspace/coverage/default/9.gpio_smoke_no_pullup_pulldown.1270014121
Short name T149
Test name
Test status
Simulation time 170906693 ps
CPU time 1.08 seconds
Started Jul 30 06:02:01 PM PDT 24
Finished Jul 30 06:02:03 PM PDT 24
Peak memory 196976 kb
Host smart-ea4d65b5-9b5a-473d-8033-706966a8e200
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270014121 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown.1270014121
Directory /workspace/9.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_stress_all.2533391638
Short name T564
Test name
Test status
Simulation time 52190788790 ps
CPU time 157.5 seconds
Started Jul 30 06:01:55 PM PDT 24
Finished Jul 30 06:04:32 PM PDT 24
Peak memory 198788 kb
Host smart-a850d560-7889-437b-b4aa-7aff54456087
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533391638 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.g
pio_stress_all.2533391638
Directory /workspace/9.gpio_stress_all/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.1274350323
Short name T889
Test name
Test status
Simulation time 35334940 ps
CPU time 1 seconds
Started Jul 30 05:56:47 PM PDT 24
Finished Jul 30 05:56:48 PM PDT 24
Peak memory 196548 kb
Host smart-f824e25f-d5c2-430c-9434-1eb580cc241a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1274350323 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_en_cdc_prim.1274350323
Directory /workspace/0.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1106573347
Short name T939
Test name
Test status
Simulation time 131480834 ps
CPU time 0.9 seconds
Started Jul 30 05:56:46 PM PDT 24
Finished Jul 30 05:56:47 PM PDT 24
Peak memory 197296 kb
Host smart-4d7efb60-916c-4799-875d-68c3f54f1b14
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106573347 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1106573347
Directory /workspace/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.3380486269
Short name T870
Test name
Test status
Simulation time 77096361 ps
CPU time 1.17 seconds
Started Jul 30 05:56:43 PM PDT 24
Finished Jul 30 05:56:44 PM PDT 24
Peak memory 196636 kb
Host smart-1e97973c-fd84-46e6-91ba-ab2363000da0
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3380486269 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_en_cdc_prim.3380486269
Directory /workspace/1.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.636681607
Short name T848
Test name
Test status
Simulation time 685749599 ps
CPU time 1.14 seconds
Started Jul 30 05:56:48 PM PDT 24
Finished Jul 30 05:56:49 PM PDT 24
Peak memory 198088 kb
Host smart-a2d9636d-abe4-4405-94ab-8fda42347864
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636681607 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.636681607
Directory /workspace/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.2620555775
Short name T892
Test name
Test status
Simulation time 37432193 ps
CPU time 0.71 seconds
Started Jul 30 05:56:47 PM PDT 24
Finished Jul 30 05:56:48 PM PDT 24
Peak memory 194340 kb
Host smart-426869ef-6e6a-4c02-b14c-f30657441472
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2620555775 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_en_cdc_prim.2620555775
Directory /workspace/10.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2669949987
Short name T857
Test name
Test status
Simulation time 216345261 ps
CPU time 1.47 seconds
Started Jul 30 05:56:50 PM PDT 24
Finished Jul 30 05:56:51 PM PDT 24
Peak memory 198028 kb
Host smart-869118ce-44ea-498a-88bd-92b4bc318cb4
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669949987 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2669949987
Directory /workspace/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.1317492516
Short name T938
Test name
Test status
Simulation time 113548223 ps
CPU time 0.76 seconds
Started Jul 30 05:56:49 PM PDT 24
Finished Jul 30 05:56:50 PM PDT 24
Peak memory 195376 kb
Host smart-7d42107e-0cb5-4e1e-affa-e2407e6e77f5
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1317492516 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_en_cdc_prim.1317492516
Directory /workspace/11.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1866626902
Short name T918
Test name
Test status
Simulation time 342698639 ps
CPU time 1.41 seconds
Started Jul 30 05:56:53 PM PDT 24
Finished Jul 30 05:56:54 PM PDT 24
Peak memory 198032 kb
Host smart-74cb313f-fa8b-4470-b7f3-58f7ffd7cd8b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866626902 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1866626902
Directory /workspace/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.3551811351
Short name T891
Test name
Test status
Simulation time 30654373 ps
CPU time 0.79 seconds
Started Jul 30 05:56:50 PM PDT 24
Finished Jul 30 05:56:50 PM PDT 24
Peak memory 195344 kb
Host smart-b30a4770-d6d6-432e-adae-8ca05e00e81d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3551811351 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_en_cdc_prim.3551811351
Directory /workspace/12.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1994284627
Short name T864
Test name
Test status
Simulation time 49891526 ps
CPU time 0.88 seconds
Started Jul 30 05:56:50 PM PDT 24
Finished Jul 30 05:56:51 PM PDT 24
Peak memory 195528 kb
Host smart-9828b7bf-5ba4-407d-b947-1fc2de65d2c4
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994284627 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1994284627
Directory /workspace/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.3387752101
Short name T850
Test name
Test status
Simulation time 444149683 ps
CPU time 0.93 seconds
Started Jul 30 05:56:48 PM PDT 24
Finished Jul 30 05:56:49 PM PDT 24
Peak memory 195524 kb
Host smart-926f612e-d071-444c-a7fc-230caf5f7802
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3387752101 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_en_cdc_prim.3387752101
Directory /workspace/13.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.210327177
Short name T875
Test name
Test status
Simulation time 59202467 ps
CPU time 1.13 seconds
Started Jul 30 05:56:50 PM PDT 24
Finished Jul 30 05:56:51 PM PDT 24
Peak memory 195644 kb
Host smart-a151f124-211d-4b96-9e4b-813c63380d83
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210327177 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.210327177
Directory /workspace/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.1090954552
Short name T855
Test name
Test status
Simulation time 68336224 ps
CPU time 1.24 seconds
Started Jul 30 05:56:49 PM PDT 24
Finished Jul 30 05:56:50 PM PDT 24
Peak memory 196476 kb
Host smart-c84be1b8-a989-4fa1-8b02-b3dc4e9fd580
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1090954552 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_en_cdc_prim.1090954552
Directory /workspace/14.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2152471721
Short name T877
Test name
Test status
Simulation time 62390229 ps
CPU time 1.17 seconds
Started Jul 30 05:56:50 PM PDT 24
Finished Jul 30 05:56:52 PM PDT 24
Peak memory 196776 kb
Host smart-4dcd5c04-f509-429a-ab9a-985dbed47b94
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152471721 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2152471721
Directory /workspace/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.2167471372
Short name T941
Test name
Test status
Simulation time 103287034 ps
CPU time 0.93 seconds
Started Jul 30 05:56:51 PM PDT 24
Finished Jul 30 05:56:52 PM PDT 24
Peak memory 197988 kb
Host smart-76632124-33fa-4939-8aa4-84118e7c3afb
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2167471372 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_en_cdc_prim.2167471372
Directory /workspace/15.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1707777494
Short name T866
Test name
Test status
Simulation time 229168397 ps
CPU time 1.05 seconds
Started Jul 30 05:56:50 PM PDT 24
Finished Jul 30 05:56:51 PM PDT 24
Peak memory 197960 kb
Host smart-e1eba6a7-1cff-487a-8390-e6e0266118c4
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707777494 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1707777494
Directory /workspace/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.799254520
Short name T871
Test name
Test status
Simulation time 73908332 ps
CPU time 1.37 seconds
Started Jul 30 05:56:50 PM PDT 24
Finished Jul 30 05:56:51 PM PDT 24
Peak memory 196916 kb
Host smart-04c526e5-fde8-448f-8e72-3b49998fc3ce
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=799254520 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_en_cdc_prim.799254520
Directory /workspace/16.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2062824760
Short name T879
Test name
Test status
Simulation time 108157098 ps
CPU time 1.3 seconds
Started Jul 30 05:56:49 PM PDT 24
Finished Jul 30 05:56:50 PM PDT 24
Peak memory 197952 kb
Host smart-40644066-3ee5-4287-a1b9-a81aeaf706a1
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062824760 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2062824760
Directory /workspace/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.3479393754
Short name T862
Test name
Test status
Simulation time 59011440 ps
CPU time 1.08 seconds
Started Jul 30 05:56:50 PM PDT 24
Finished Jul 30 05:56:51 PM PDT 24
Peak memory 196680 kb
Host smart-1090f606-86e4-4237-a203-b547439699cd
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3479393754 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_en_cdc_prim.3479393754
Directory /workspace/17.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1082874401
Short name T843
Test name
Test status
Simulation time 63751158 ps
CPU time 1.29 seconds
Started Jul 30 05:56:50 PM PDT 24
Finished Jul 30 05:56:52 PM PDT 24
Peak memory 198080 kb
Host smart-a4b3ac64-a337-4b51-9427-dfcca28fafc9
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082874401 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1082874401
Directory /workspace/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.2225839401
Short name T904
Test name
Test status
Simulation time 27983283 ps
CPU time 0.96 seconds
Started Jul 30 05:56:55 PM PDT 24
Finished Jul 30 05:56:56 PM PDT 24
Peak memory 195360 kb
Host smart-8c7c37f7-83bc-4c67-988a-1cb7376e4e2b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2225839401 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_en_cdc_prim.2225839401
Directory /workspace/18.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3026809290
Short name T931
Test name
Test status
Simulation time 49241607 ps
CPU time 1.27 seconds
Started Jul 30 05:56:52 PM PDT 24
Finished Jul 30 05:56:53 PM PDT 24
Peak memory 196980 kb
Host smart-03c551ae-82a8-4ef0-9cc0-dba1c8e1aedd
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026809290 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3026809290
Directory /workspace/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.3539487225
Short name T884
Test name
Test status
Simulation time 67032952 ps
CPU time 1.11 seconds
Started Jul 30 05:56:54 PM PDT 24
Finished Jul 30 05:56:55 PM PDT 24
Peak memory 195696 kb
Host smart-a9ed8b7f-3f7b-4833-a394-5e293479acb2
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3539487225 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_en_cdc_prim.3539487225
Directory /workspace/19.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3159797779
Short name T897
Test name
Test status
Simulation time 58404185 ps
CPU time 1.2 seconds
Started Jul 30 05:56:53 PM PDT 24
Finished Jul 30 05:56:54 PM PDT 24
Peak memory 196676 kb
Host smart-0ce49838-c66c-4eef-94c3-fb93c40e3189
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159797779 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3159797779
Directory /workspace/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.1317228925
Short name T909
Test name
Test status
Simulation time 208298353 ps
CPU time 1.48 seconds
Started Jul 30 05:56:46 PM PDT 24
Finished Jul 30 05:56:48 PM PDT 24
Peak memory 198052 kb
Host smart-96231501-9a58-4389-a4bc-6dd5a97947ed
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1317228925 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_en_cdc_prim.1317228925
Directory /workspace/2.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.982486493
Short name T915
Test name
Test status
Simulation time 233749094 ps
CPU time 0.85 seconds
Started Jul 30 05:56:47 PM PDT 24
Finished Jul 30 05:56:48 PM PDT 24
Peak memory 196204 kb
Host smart-021c48bb-ca7a-4902-968e-4958048c6ec2
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982486493 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.982486493
Directory /workspace/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.3590233241
Short name T869
Test name
Test status
Simulation time 67871603 ps
CPU time 1.23 seconds
Started Jul 30 05:56:53 PM PDT 24
Finished Jul 30 05:56:54 PM PDT 24
Peak memory 198056 kb
Host smart-8338d9b7-0561-4a1b-b478-c20b12981fe4
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3590233241 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_en_cdc_prim.3590233241
Directory /workspace/20.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1600686538
Short name T900
Test name
Test status
Simulation time 436917583 ps
CPU time 1.37 seconds
Started Jul 30 05:56:54 PM PDT 24
Finished Jul 30 05:56:55 PM PDT 24
Peak memory 198028 kb
Host smart-d10e709f-019a-4c9c-b0eb-715b8c88b2a1
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600686538 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1600686538
Directory /workspace/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.2895609135
Short name T927
Test name
Test status
Simulation time 75938192 ps
CPU time 1.3 seconds
Started Jul 30 05:56:53 PM PDT 24
Finished Jul 30 05:56:55 PM PDT 24
Peak memory 196632 kb
Host smart-bef7651e-5f63-4f21-942a-bfc1e59ef0b2
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2895609135 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_en_cdc_prim.2895609135
Directory /workspace/21.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3661182814
Short name T930
Test name
Test status
Simulation time 69757834 ps
CPU time 1.42 seconds
Started Jul 30 05:56:53 PM PDT 24
Finished Jul 30 05:56:54 PM PDT 24
Peak memory 196552 kb
Host smart-d724ca67-774a-4ba7-b003-5f8618455e80
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661182814 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3661182814
Directory /workspace/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.1526257141
Short name T846
Test name
Test status
Simulation time 215835371 ps
CPU time 1.43 seconds
Started Jul 30 05:56:53 PM PDT 24
Finished Jul 30 05:56:55 PM PDT 24
Peak memory 196740 kb
Host smart-c3b50be9-c125-4a30-82cb-e4818d97730e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1526257141 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_en_cdc_prim.1526257141
Directory /workspace/22.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3361939665
Short name T901
Test name
Test status
Simulation time 854122614 ps
CPU time 1.43 seconds
Started Jul 30 05:56:52 PM PDT 24
Finished Jul 30 05:56:53 PM PDT 24
Peak memory 196820 kb
Host smart-f8098795-71d7-47c0-a385-d051bcd04a1f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361939665 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3361939665
Directory /workspace/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.41276533
Short name T908
Test name
Test status
Simulation time 162639161 ps
CPU time 1.22 seconds
Started Jul 30 05:56:54 PM PDT 24
Finished Jul 30 05:56:56 PM PDT 24
Peak memory 196640 kb
Host smart-a8c610a5-c351-42f3-a449-d950e8a3d3cb
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=41276533 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_en_cdc_prim.41276533
Directory /workspace/23.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3735260434
Short name T861
Test name
Test status
Simulation time 56641196 ps
CPU time 1.16 seconds
Started Jul 30 05:56:53 PM PDT 24
Finished Jul 30 05:56:54 PM PDT 24
Peak memory 195700 kb
Host smart-6e1f25ea-bbc2-40f7-808b-7d5300296ebd
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735260434 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3735260434
Directory /workspace/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.1507746623
Short name T937
Test name
Test status
Simulation time 325554791 ps
CPU time 1.35 seconds
Started Jul 30 05:56:53 PM PDT 24
Finished Jul 30 05:56:54 PM PDT 24
Peak memory 196768 kb
Host smart-0d7bdaba-3c42-40e5-bca1-a5ff0c240d58
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1507746623 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_en_cdc_prim.1507746623
Directory /workspace/24.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1268137427
Short name T854
Test name
Test status
Simulation time 88283683 ps
CPU time 0.98 seconds
Started Jul 30 05:56:55 PM PDT 24
Finished Jul 30 05:56:56 PM PDT 24
Peak memory 196452 kb
Host smart-9a229221-90ce-4c25-9bc4-f8157a856b2f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268137427 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1268137427
Directory /workspace/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.3558143620
Short name T894
Test name
Test status
Simulation time 324134139 ps
CPU time 1.46 seconds
Started Jul 30 05:56:52 PM PDT 24
Finished Jul 30 05:56:54 PM PDT 24
Peak memory 196836 kb
Host smart-dbb2ee3e-5840-4b34-9c0c-5b2862175ed2
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3558143620 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_en_cdc_prim.3558143620
Directory /workspace/25.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.615119372
Short name T859
Test name
Test status
Simulation time 205429245 ps
CPU time 1.53 seconds
Started Jul 30 05:56:55 PM PDT 24
Finished Jul 30 05:56:56 PM PDT 24
Peak memory 196680 kb
Host smart-ecc7e63b-92ac-4776-9781-5e0f16ebef20
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615119372 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.615119372
Directory /workspace/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.913711837
Short name T906
Test name
Test status
Simulation time 43980764 ps
CPU time 1.48 seconds
Started Jul 30 05:56:55 PM PDT 24
Finished Jul 30 05:56:57 PM PDT 24
Peak memory 196540 kb
Host smart-7526f46b-58b3-4989-9d1a-b2ab5d64ecc0
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=913711837 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_en_cdc_prim.913711837
Directory /workspace/26.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1020983260
Short name T898
Test name
Test status
Simulation time 93109722 ps
CPU time 0.99 seconds
Started Jul 30 05:56:55 PM PDT 24
Finished Jul 30 05:56:56 PM PDT 24
Peak memory 195712 kb
Host smart-e6eab161-a748-47b0-808b-c087beed80d5
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020983260 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1020983260
Directory /workspace/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.891440813
Short name T914
Test name
Test status
Simulation time 163464743 ps
CPU time 1.26 seconds
Started Jul 30 05:56:55 PM PDT 24
Finished Jul 30 05:56:56 PM PDT 24
Peak memory 196564 kb
Host smart-d2f785bc-6044-42db-a70b-55fca338762f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=891440813 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_en_cdc_prim.891440813
Directory /workspace/27.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1882940871
Short name T911
Test name
Test status
Simulation time 52540683 ps
CPU time 1.12 seconds
Started Jul 30 05:56:57 PM PDT 24
Finished Jul 30 05:56:58 PM PDT 24
Peak memory 196744 kb
Host smart-5caa6a3f-aef6-4eb4-b520-da5bf7d7c904
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882940871 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1882940871
Directory /workspace/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.306327594
Short name T888
Test name
Test status
Simulation time 188262472 ps
CPU time 1.02 seconds
Started Jul 30 05:56:59 PM PDT 24
Finished Jul 30 05:57:00 PM PDT 24
Peak memory 196608 kb
Host smart-3c9cab99-d021-424c-b527-bf450c1c4ff5
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=306327594 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_en_cdc_prim.306327594
Directory /workspace/28.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.316159915
Short name T852
Test name
Test status
Simulation time 156960109 ps
CPU time 1.34 seconds
Started Jul 30 05:56:58 PM PDT 24
Finished Jul 30 05:56:59 PM PDT 24
Peak memory 197232 kb
Host smart-c6a43bcb-20d3-47af-9468-bd5c7ae3b637
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316159915 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.316159915
Directory /workspace/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.643950557
Short name T902
Test name
Test status
Simulation time 28730066 ps
CPU time 0.97 seconds
Started Jul 30 05:56:54 PM PDT 24
Finished Jul 30 05:56:56 PM PDT 24
Peak memory 198032 kb
Host smart-3b393a2c-8238-4193-a415-0d59da682d99
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=643950557 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_en_cdc_prim.643950557
Directory /workspace/29.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1252311441
Short name T868
Test name
Test status
Simulation time 40134493 ps
CPU time 1.23 seconds
Started Jul 30 05:56:56 PM PDT 24
Finished Jul 30 05:56:58 PM PDT 24
Peak memory 196660 kb
Host smart-013919b8-a08e-461d-b968-1a65b9b586e7
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252311441 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1252311441
Directory /workspace/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.541852339
Short name T878
Test name
Test status
Simulation time 43648805 ps
CPU time 1.07 seconds
Started Jul 30 05:56:46 PM PDT 24
Finished Jul 30 05:56:47 PM PDT 24
Peak memory 196580 kb
Host smart-03139493-5b0c-4141-a5d9-25ac5d8aefde
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=541852339 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_en_cdc_prim.541852339
Directory /workspace/3.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4153665109
Short name T880
Test name
Test status
Simulation time 48179527 ps
CPU time 0.93 seconds
Started Jul 30 05:56:48 PM PDT 24
Finished Jul 30 05:56:49 PM PDT 24
Peak memory 197016 kb
Host smart-6a9ec8f9-1647-427d-97f8-bf2ea6564b99
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153665109 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.4153665109
Directory /workspace/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.1231807043
Short name T881
Test name
Test status
Simulation time 460596100 ps
CPU time 1.58 seconds
Started Jul 30 05:56:57 PM PDT 24
Finished Jul 30 05:56:59 PM PDT 24
Peak memory 198076 kb
Host smart-0e34c868-8ab5-4003-8c55-013c99b9ad7d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1231807043 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_en_cdc_prim.1231807043
Directory /workspace/30.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2536302791
Short name T876
Test name
Test status
Simulation time 258915019 ps
CPU time 1.24 seconds
Started Jul 30 05:57:01 PM PDT 24
Finished Jul 30 05:57:03 PM PDT 24
Peak memory 197992 kb
Host smart-237562ca-c940-47fd-9ea8-211eaf067361
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536302791 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2536302791
Directory /workspace/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.4250262948
Short name T913
Test name
Test status
Simulation time 28654837 ps
CPU time 0.81 seconds
Started Jul 30 05:56:57 PM PDT 24
Finished Jul 30 05:56:58 PM PDT 24
Peak memory 195396 kb
Host smart-a6982f27-2cd2-4bdf-9922-83289aef51f9
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4250262948 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_en_cdc_prim.4250262948
Directory /workspace/31.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1591375275
Short name T934
Test name
Test status
Simulation time 74218373 ps
CPU time 1.26 seconds
Started Jul 30 05:56:57 PM PDT 24
Finished Jul 30 05:56:59 PM PDT 24
Peak memory 195784 kb
Host smart-8987b8a2-8c07-4db7-9d01-55ecaa37b96b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591375275 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1591375275
Directory /workspace/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.2437284312
Short name T926
Test name
Test status
Simulation time 92764013 ps
CPU time 0.97 seconds
Started Jul 30 05:56:56 PM PDT 24
Finished Jul 30 05:56:57 PM PDT 24
Peak memory 196584 kb
Host smart-51ca6e89-4251-44e3-81ef-b67827374a92
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2437284312 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_en_cdc_prim.2437284312
Directory /workspace/32.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3753754867
Short name T933
Test name
Test status
Simulation time 196720346 ps
CPU time 0.83 seconds
Started Jul 30 05:56:55 PM PDT 24
Finished Jul 30 05:56:56 PM PDT 24
Peak memory 195320 kb
Host smart-d3b9cfb9-1ea8-48ec-958d-23b0895d2915
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753754867 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3753754867
Directory /workspace/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.928958284
Short name T863
Test name
Test status
Simulation time 77976654 ps
CPU time 1.41 seconds
Started Jul 30 05:56:59 PM PDT 24
Finished Jul 30 05:57:01 PM PDT 24
Peak memory 197028 kb
Host smart-63ad875b-a4d9-49b9-9e44-1d21b2bd1511
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=928958284 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_en_cdc_prim.928958284
Directory /workspace/33.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1073686671
Short name T899
Test name
Test status
Simulation time 262274396 ps
CPU time 1.27 seconds
Started Jul 30 05:56:57 PM PDT 24
Finished Jul 30 05:56:59 PM PDT 24
Peak memory 196920 kb
Host smart-742e60a4-bbe8-4432-8275-c37b732052bb
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073686671 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1073686671
Directory /workspace/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.1145644884
Short name T916
Test name
Test status
Simulation time 74347540 ps
CPU time 1.45 seconds
Started Jul 30 05:56:56 PM PDT 24
Finished Jul 30 05:56:58 PM PDT 24
Peak memory 196620 kb
Host smart-b8e8517f-f207-442b-9ca3-cd6eb9bff315
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1145644884 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_en_cdc_prim.1145644884
Directory /workspace/34.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.810782384
Short name T896
Test name
Test status
Simulation time 56438356 ps
CPU time 1.23 seconds
Started Jul 30 05:57:05 PM PDT 24
Finished Jul 30 05:57:06 PM PDT 24
Peak memory 198096 kb
Host smart-87a67bc3-10c7-4721-b69b-5fd180e1c141
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810782384 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.810782384
Directory /workspace/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.828846880
Short name T923
Test name
Test status
Simulation time 107633417 ps
CPU time 0.73 seconds
Started Jul 30 05:57:00 PM PDT 24
Finished Jul 30 05:57:01 PM PDT 24
Peak memory 195332 kb
Host smart-adf02983-1826-45c2-b596-219490d4080c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=828846880 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_en_cdc_prim.828846880
Directory /workspace/35.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3008531669
Short name T844
Test name
Test status
Simulation time 187250042 ps
CPU time 1.42 seconds
Started Jul 30 05:57:04 PM PDT 24
Finished Jul 30 05:57:05 PM PDT 24
Peak memory 196792 kb
Host smart-c1ed7b8e-b23a-42ad-ba8a-7229e97e688c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008531669 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3008531669
Directory /workspace/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.1731588392
Short name T865
Test name
Test status
Simulation time 55648661 ps
CPU time 0.91 seconds
Started Jul 30 05:57:03 PM PDT 24
Finished Jul 30 05:57:04 PM PDT 24
Peak memory 195484 kb
Host smart-01140e5e-1ff3-4635-a8d7-5fdd59a19fde
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1731588392 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_en_cdc_prim.1731588392
Directory /workspace/36.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4084719524
Short name T940
Test name
Test status
Simulation time 213034406 ps
CPU time 1.16 seconds
Started Jul 30 05:57:00 PM PDT 24
Finished Jul 30 05:57:01 PM PDT 24
Peak memory 195740 kb
Host smart-e781797f-92f3-4091-8a81-274ba4f8130f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084719524 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4084719524
Directory /workspace/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.2611974799
Short name T924
Test name
Test status
Simulation time 51062437 ps
CPU time 1.61 seconds
Started Jul 30 05:57:02 PM PDT 24
Finished Jul 30 05:57:03 PM PDT 24
Peak memory 198000 kb
Host smart-9a7fff12-20fc-414a-bec3-d0c274ab6d0e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2611974799 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_en_cdc_prim.2611974799
Directory /workspace/37.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1557815257
Short name T886
Test name
Test status
Simulation time 305121187 ps
CPU time 1.48 seconds
Started Jul 30 05:57:01 PM PDT 24
Finished Jul 30 05:57:03 PM PDT 24
Peak memory 195740 kb
Host smart-3a44d785-193e-4949-997f-d13e8def81ee
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557815257 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1557815257
Directory /workspace/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.351263303
Short name T905
Test name
Test status
Simulation time 57331764 ps
CPU time 1.02 seconds
Started Jul 30 05:57:01 PM PDT 24
Finished Jul 30 05:57:02 PM PDT 24
Peak memory 196340 kb
Host smart-752e4fcd-06fe-42aa-982f-38a17a2c50a5
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=351263303 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_en_cdc_prim.351263303
Directory /workspace/38.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1980008899
Short name T853
Test name
Test status
Simulation time 238551998 ps
CPU time 1.28 seconds
Started Jul 30 05:56:59 PM PDT 24
Finished Jul 30 05:57:00 PM PDT 24
Peak memory 197044 kb
Host smart-50161ce5-a8ab-46dc-a9d3-2669129344fe
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980008899 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1980008899
Directory /workspace/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.2886047413
Short name T842
Test name
Test status
Simulation time 100915920 ps
CPU time 1.02 seconds
Started Jul 30 05:57:05 PM PDT 24
Finished Jul 30 05:57:06 PM PDT 24
Peak memory 195648 kb
Host smart-60b82605-4967-46cc-afe1-7621e82bc4bf
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2886047413 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_en_cdc_prim.2886047413
Directory /workspace/39.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2571625817
Short name T851
Test name
Test status
Simulation time 124082256 ps
CPU time 0.93 seconds
Started Jul 30 05:57:05 PM PDT 24
Finished Jul 30 05:57:06 PM PDT 24
Peak memory 196368 kb
Host smart-98b15ebf-2f5f-4f1b-a476-74b8a9c7e52d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571625817 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2571625817
Directory /workspace/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.1012580448
Short name T919
Test name
Test status
Simulation time 106446873 ps
CPU time 1.25 seconds
Started Jul 30 05:56:45 PM PDT 24
Finished Jul 30 05:56:46 PM PDT 24
Peak memory 198132 kb
Host smart-42bfd79c-1fb4-4844-ab9b-65d28aec04f2
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1012580448 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_en_cdc_prim.1012580448
Directory /workspace/4.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3744104967
Short name T883
Test name
Test status
Simulation time 346250943 ps
CPU time 1.31 seconds
Started Jul 30 05:56:46 PM PDT 24
Finished Jul 30 05:56:48 PM PDT 24
Peak memory 196544 kb
Host smart-211ab0ce-ea58-4f2a-96a3-ae7a09022fd1
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744104967 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3744104967
Directory /workspace/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.3297322714
Short name T932
Test name
Test status
Simulation time 41021660 ps
CPU time 0.97 seconds
Started Jul 30 05:57:02 PM PDT 24
Finished Jul 30 05:57:03 PM PDT 24
Peak memory 198044 kb
Host smart-484fdc2d-85f1-40d9-94bf-549d1b386604
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3297322714 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_en_cdc_prim.3297322714
Directory /workspace/40.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1895582616
Short name T872
Test name
Test status
Simulation time 238028282 ps
CPU time 1.14 seconds
Started Jul 30 05:57:00 PM PDT 24
Finished Jul 30 05:57:01 PM PDT 24
Peak memory 196800 kb
Host smart-a889f9da-726f-4351-a6dd-80ea52322edf
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895582616 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1895582616
Directory /workspace/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.3511090752
Short name T874
Test name
Test status
Simulation time 113855598 ps
CPU time 1.28 seconds
Started Jul 30 05:57:01 PM PDT 24
Finished Jul 30 05:57:03 PM PDT 24
Peak memory 198024 kb
Host smart-d39807ec-2406-48c1-8d81-6c1b11dc56eb
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3511090752 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_en_cdc_prim.3511090752
Directory /workspace/41.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4225952990
Short name T922
Test name
Test status
Simulation time 42010419 ps
CPU time 1.14 seconds
Started Jul 30 05:57:04 PM PDT 24
Finished Jul 30 05:57:05 PM PDT 24
Peak memory 196820 kb
Host smart-a773537d-4251-4e64-9d63-e4a05614a66c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225952990 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4225952990
Directory /workspace/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.3923745926
Short name T847
Test name
Test status
Simulation time 603793067 ps
CPU time 0.98 seconds
Started Jul 30 05:57:02 PM PDT 24
Finished Jul 30 05:57:03 PM PDT 24
Peak memory 196532 kb
Host smart-997ac80f-0d3c-4928-8120-ae755ef0e503
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3923745926 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_en_cdc_prim.3923745926
Directory /workspace/42.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.228224999
Short name T867
Test name
Test status
Simulation time 30578894 ps
CPU time 0.96 seconds
Started Jul 30 05:57:01 PM PDT 24
Finished Jul 30 05:57:02 PM PDT 24
Peak memory 195724 kb
Host smart-a2136ae3-62db-4aef-84ef-f98338f19a5f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228224999 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.228224999
Directory /workspace/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.1146324084
Short name T903
Test name
Test status
Simulation time 27771046 ps
CPU time 1.04 seconds
Started Jul 30 05:56:59 PM PDT 24
Finished Jul 30 05:57:00 PM PDT 24
Peak memory 197520 kb
Host smart-35a924cf-f6ef-4d7b-8cec-82819306a620
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1146324084 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_en_cdc_prim.1146324084
Directory /workspace/43.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1878332845
Short name T907
Test name
Test status
Simulation time 137403055 ps
CPU time 1.29 seconds
Started Jul 30 05:57:02 PM PDT 24
Finished Jul 30 05:57:03 PM PDT 24
Peak memory 196676 kb
Host smart-5e00e0f4-870d-4ad2-a023-c26186256d55
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878332845 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1878332845
Directory /workspace/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.1119169357
Short name T887
Test name
Test status
Simulation time 108200204 ps
CPU time 1.04 seconds
Started Jul 30 05:57:01 PM PDT 24
Finished Jul 30 05:57:02 PM PDT 24
Peak memory 195484 kb
Host smart-6c3c7bf8-2e11-4ade-adf5-d3f0e0ea76ae
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1119169357 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_en_cdc_prim.1119169357
Directory /workspace/44.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.472147510
Short name T936
Test name
Test status
Simulation time 45081869 ps
CPU time 1.07 seconds
Started Jul 30 05:57:02 PM PDT 24
Finished Jul 30 05:57:03 PM PDT 24
Peak memory 196768 kb
Host smart-673bfdab-8f21-4273-9d3c-ff35531a9eaa
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472147510 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.472147510
Directory /workspace/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.2978264407
Short name T873
Test name
Test status
Simulation time 200251576 ps
CPU time 1.06 seconds
Started Jul 30 05:57:01 PM PDT 24
Finished Jul 30 05:57:02 PM PDT 24
Peak memory 196468 kb
Host smart-91836d07-56e2-4404-b6f4-30e34ec8ebc7
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2978264407 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_en_cdc_prim.2978264407
Directory /workspace/45.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.671428129
Short name T860
Test name
Test status
Simulation time 280606731 ps
CPU time 1.46 seconds
Started Jul 30 05:57:04 PM PDT 24
Finished Jul 30 05:57:05 PM PDT 24
Peak memory 198244 kb
Host smart-39202f6c-d2f0-4d0f-98f9-85d53548b17d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671428129 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.671428129
Directory /workspace/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.3505227599
Short name T858
Test name
Test status
Simulation time 146100491 ps
CPU time 1.21 seconds
Started Jul 30 05:57:02 PM PDT 24
Finished Jul 30 05:57:04 PM PDT 24
Peak memory 196576 kb
Host smart-bd090bb1-fb68-498b-849e-504b13d2083c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3505227599 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_en_cdc_prim.3505227599
Directory /workspace/46.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1912193394
Short name T935
Test name
Test status
Simulation time 35052182 ps
CPU time 0.74 seconds
Started Jul 30 05:57:02 PM PDT 24
Finished Jul 30 05:57:03 PM PDT 24
Peak memory 195016 kb
Host smart-f7292202-de65-4a38-b212-805506ba0d42
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912193394 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1912193394
Directory /workspace/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.4174806862
Short name T925
Test name
Test status
Simulation time 27912411 ps
CPU time 0.83 seconds
Started Jul 30 05:57:01 PM PDT 24
Finished Jul 30 05:57:02 PM PDT 24
Peak memory 195348 kb
Host smart-c8bc4126-b6eb-4e9f-8ca8-54c81150ce10
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4174806862 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_en_cdc_prim.4174806862
Directory /workspace/47.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2532156942
Short name T921
Test name
Test status
Simulation time 45276718 ps
CPU time 1.09 seconds
Started Jul 30 05:57:03 PM PDT 24
Finished Jul 30 05:57:04 PM PDT 24
Peak memory 196496 kb
Host smart-c13b2beb-4088-4973-95d1-fb775825aee9
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532156942 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2532156942
Directory /workspace/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.1391839659
Short name T929
Test name
Test status
Simulation time 466565361 ps
CPU time 1.24 seconds
Started Jul 30 05:57:05 PM PDT 24
Finished Jul 30 05:57:07 PM PDT 24
Peak memory 196580 kb
Host smart-f85b29ba-27ef-449b-9e51-d29873d2fdcd
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1391839659 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_en_cdc_prim.1391839659
Directory /workspace/48.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.153121096
Short name T893
Test name
Test status
Simulation time 74430567 ps
CPU time 1.18 seconds
Started Jul 30 05:57:03 PM PDT 24
Finished Jul 30 05:57:04 PM PDT 24
Peak memory 198120 kb
Host smart-8db0999d-290e-40ef-9996-fb8572d80969
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153121096 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.153121096
Directory /workspace/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.3783769248
Short name T849
Test name
Test status
Simulation time 132897274 ps
CPU time 1.16 seconds
Started Jul 30 05:57:06 PM PDT 24
Finished Jul 30 05:57:07 PM PDT 24
Peak memory 196616 kb
Host smart-3b8495a3-f342-496d-99d4-b76aa93f1407
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3783769248 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_en_cdc_prim.3783769248
Directory /workspace/49.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3609761614
Short name T912
Test name
Test status
Simulation time 213620242 ps
CPU time 1.24 seconds
Started Jul 30 05:57:05 PM PDT 24
Finished Jul 30 05:57:06 PM PDT 24
Peak memory 197436 kb
Host smart-22570b83-24eb-43e4-ad19-e6474f6e55a5
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609761614 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3609761614
Directory /workspace/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.3716444659
Short name T885
Test name
Test status
Simulation time 53085171 ps
CPU time 1.02 seconds
Started Jul 30 05:56:46 PM PDT 24
Finished Jul 30 05:56:47 PM PDT 24
Peak memory 196412 kb
Host smart-77dc6075-d895-4a92-ae31-2e633205ed9d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3716444659 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_en_cdc_prim.3716444659
Directory /workspace/5.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1811757904
Short name T928
Test name
Test status
Simulation time 59061912 ps
CPU time 1.5 seconds
Started Jul 30 05:56:50 PM PDT 24
Finished Jul 30 05:56:52 PM PDT 24
Peak memory 196832 kb
Host smart-dd877b9b-f907-4304-981f-263ff7ec73ba
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811757904 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1811757904
Directory /workspace/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.300796866
Short name T917
Test name
Test status
Simulation time 342554071 ps
CPU time 1.57 seconds
Started Jul 30 05:56:54 PM PDT 24
Finished Jul 30 05:56:56 PM PDT 24
Peak memory 198028 kb
Host smart-711efaed-bae7-4223-8668-7060cc625d77
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=300796866 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_en_cdc_prim.300796866
Directory /workspace/6.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.564771483
Short name T890
Test name
Test status
Simulation time 53258924 ps
CPU time 1.04 seconds
Started Jul 30 05:56:49 PM PDT 24
Finished Jul 30 05:56:50 PM PDT 24
Peak memory 198040 kb
Host smart-4b711d97-9f3a-4a0f-b6e2-061dae9ca8a0
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564771483 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.564771483
Directory /workspace/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.4058428993
Short name T895
Test name
Test status
Simulation time 95506998 ps
CPU time 1.41 seconds
Started Jul 30 05:56:54 PM PDT 24
Finished Jul 30 05:56:56 PM PDT 24
Peak memory 196592 kb
Host smart-614afd2b-f167-4d3c-974e-1b712bae086b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4058428993 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_en_cdc_prim.4058428993
Directory /workspace/7.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2529171976
Short name T910
Test name
Test status
Simulation time 35299204 ps
CPU time 0.89 seconds
Started Jul 30 05:56:56 PM PDT 24
Finished Jul 30 05:56:57 PM PDT 24
Peak memory 195368 kb
Host smart-c623f20e-3dc0-477a-b649-c1b97a3e9069
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529171976 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2529171976
Directory /workspace/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.3117677263
Short name T856
Test name
Test status
Simulation time 499887223 ps
CPU time 1.15 seconds
Started Jul 30 05:56:50 PM PDT 24
Finished Jul 30 05:56:51 PM PDT 24
Peak memory 196840 kb
Host smart-0021650a-2358-4fac-afee-236279d59f56
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3117677263 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_en_cdc_prim.3117677263
Directory /workspace/8.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2852004633
Short name T882
Test name
Test status
Simulation time 269593045 ps
CPU time 1.29 seconds
Started Jul 30 05:56:49 PM PDT 24
Finished Jul 30 05:56:50 PM PDT 24
Peak memory 196080 kb
Host smart-eacddc4b-6895-4496-b058-96ef4fceb346
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852004633 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2852004633
Directory /workspace/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.2204234751
Short name T920
Test name
Test status
Simulation time 83832419 ps
CPU time 0.86 seconds
Started Jul 30 05:56:50 PM PDT 24
Finished Jul 30 05:56:51 PM PDT 24
Peak memory 195456 kb
Host smart-2b1b1099-a8c2-4d8f-af70-ea77b93690e1
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2204234751 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_en_cdc_prim.2204234751
Directory /workspace/9.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3199730230
Short name T845
Test name
Test status
Simulation time 658474478 ps
CPU time 1.05 seconds
Started Jul 30 05:56:47 PM PDT 24
Finished Jul 30 05:56:48 PM PDT 24
Peak memory 196396 kb
Host smart-91b7fbbc-d38e-4460-84cd-599bb69f8462
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199730230 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3199730230
Directory /workspace/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%