Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	32	0	32	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	128	0	128	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	3328303	1			T21	250		T22	860		T23	1
all_pins[1]	3328303	1			T21	250		T22	860		T23	1
all_pins[2]	3328303	1			T21	250		T22	860		T23	1
all_pins[3]	3328303	1			T21	250		T22	860		T23	1
all_pins[4]	3328303	1			T21	250		T22	860		T23	1
all_pins[5]	3328303	1			T21	250		T22	860		T23	1
all_pins[6]	3328303	1			T21	250		T22	860		T23	1
all_pins[7]	3328303	1			T21	250		T22	860		T23	1
all_pins[8]	3328303	1			T21	250		T22	860		T23	1
all_pins[9]	3328303	1			T21	250		T22	860		T23	1
all_pins[10]	3328303	1			T21	250		T22	860		T23	1
all_pins[11]	3328303	1			T21	250		T22	860		T23	1
all_pins[12]	3328303	1			T21	250		T22	860		T23	1
all_pins[13]	3328303	1			T21	250		T22	860		T23	1
all_pins[14]	3328303	1			T21	250		T22	860		T23	1
all_pins[15]	3328303	1			T21	250		T22	860		T23	1
all_pins[16]	3328303	1			T21	250		T22	860		T23	1
all_pins[17]	3328303	1			T21	250		T22	860		T23	1
all_pins[18]	3328303	1			T21	250		T22	860		T23	1
all_pins[19]	3328303	1			T21	250		T22	860		T23	1
all_pins[20]	3328303	1			T21	250		T22	860		T23	1
all_pins[21]	3328303	1			T21	250		T22	860		T23	1
all_pins[22]	3328303	1			T21	250		T22	860		T23	1
all_pins[23]	3328303	1			T21	250		T22	860		T23	1
all_pins[24]	3328303	1			T21	250		T22	860		T23	1
all_pins[25]	3328303	1			T21	250		T22	860		T23	1
all_pins[26]	3328303	1			T21	250		T22	860		T23	1
all_pins[27]	3328303	1			T21	250		T22	860		T23	1
all_pins[28]	3328303	1			T21	250		T22	860		T23	1
all_pins[29]	3328303	1			T21	250		T22	860		T23	1
all_pins[30]	3328303	1			T21	250		T22	860		T23	1
all_pins[31]	3328303	1			T21	250		T22	860		T23	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	66168852	1			T21	5403		T22	17113		T23	32
values[0x1]	40336844	1			T21	2597		T22	10407		T25	526
transitions[0x0=>0x1]	24155725	1			T21	1596		T22	6110		T25	362
transitions[0x1=>0x0]	24155564	1			T21	1595		T22	6110		T25	362

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2069344	1			T21	157		T22	611		T23	1
all_pins[0]	values[0x1]	1258959	1			T21	93		T22	249		T25	11
all_pins[0]	transitions[0x0=>0x1]	776436	1			T21	34		T22	144		T25	11
all_pins[0]	transitions[0x1=>0x0]	783142	1			T21	48		T22	203		T25	18
all_pins[1]	values[0x0]	2069788	1			T21	111		T22	560		T23	1
all_pins[1]	values[0x1]	1258515	1			T21	139		T22	300		T25	23
all_pins[1]	transitions[0x0=>0x1]	753408	1			T21	104		T22	202		T25	17
all_pins[1]	transitions[0x1=>0x0]	753852	1			T21	58		T22	151		T25	5
all_pins[2]	values[0x0]	2064963	1			T21	209		T22	613		T23	1
all_pins[2]	values[0x1]	1263340	1			T21	41		T22	247		T25	31
all_pins[2]	transitions[0x0=>0x1]	756835	1			T21	9		T22	142		T25	13
all_pins[2]	transitions[0x1=>0x0]	752010	1			T21	107		T22	195		T25	5
all_pins[3]	values[0x0]	2070543	1			T21	210		T22	501		T23	1
all_pins[3]	values[0x1]	1257760	1			T21	40		T22	359		T25	14
all_pins[3]	transitions[0x0=>0x1]	752942	1			T21	40		T22	272		T25	5
all_pins[3]	transitions[0x1=>0x0]	758522	1			T21	41		T22	160		T25	22
all_pins[4]	values[0x0]	2067956	1			T21	173		T22	429		T23	1
all_pins[4]	values[0x1]	1260347	1			T21	77		T22	431		T25	24
all_pins[4]	transitions[0x0=>0x1]	754444	1			T21	69		T22	210		T25	23
all_pins[4]	transitions[0x1=>0x0]	751857	1			T21	32		T22	138		T25	13
all_pins[5]	values[0x0]	2073468	1			T21	199		T22	535		T23	1
all_pins[5]	values[0x1]	1254835	1			T21	51		T22	325		T25	11
all_pins[5]	transitions[0x0=>0x1]	752180	1			T21	34		T22	105		T25	5
all_pins[5]	transitions[0x1=>0x0]	757692	1			T21	60		T22	211		T25	18
all_pins[6]	values[0x0]	2066188	1			T21	188		T22	684		T23	1
all_pins[6]	values[0x1]	1262115	1			T21	62		T22	176		T25	17
all_pins[6]	transitions[0x0=>0x1]	756124	1			T21	57		T22	132		T25	14
all_pins[6]	transitions[0x1=>0x0]	748844	1			T21	46		T22	281		T25	8
all_pins[7]	values[0x0]	2066715	1			T21	119		T22	568		T23	1
all_pins[7]	values[0x1]	1261588	1			T21	131		T22	292		T25	9
all_pins[7]	transitions[0x0=>0x1]	753220	1			T21	88		T22	213		T25	3
all_pins[7]	transitions[0x1=>0x0]	753747	1			T21	19		T22	97		T25	11
all_pins[8]	values[0x0]	2067771	1			T21	168		T22	582		T23	1
all_pins[8]	values[0x1]	1260532	1			T21	82		T22	278		T25	12
all_pins[8]	transitions[0x0=>0x1]	752734	1			T21	25		T22	166		T25	9
all_pins[8]	transitions[0x1=>0x0]	753790	1			T21	74		T22	180		T25	6
all_pins[9]	values[0x0]	2067463	1			T21	103		T22	542		T23	1
all_pins[9]	values[0x1]	1260840	1			T21	147		T22	318		T25	18
all_pins[9]	transitions[0x0=>0x1]	753814	1			T21	100		T22	169		T25	14
all_pins[9]	transitions[0x1=>0x0]	753506	1			T21	35		T22	129		T25	8
all_pins[10]	values[0x0]	2067295	1			T21	182		T22	513		T23	1
all_pins[10]	values[0x1]	1261008	1			T21	68		T22	347		T25	7
all_pins[10]	transitions[0x0=>0x1]	753272	1			T21	37		T22	189		T25	6
all_pins[10]	transitions[0x1=>0x0]	753104	1			T21	116		T22	160		T25	17
all_pins[11]	values[0x0]	2065290	1			T21	188		T22	552		T23	1
all_pins[11]	values[0x1]	1263013	1			T21	62		T22	308		T25	11
all_pins[11]	transitions[0x0=>0x1]	754740	1			T21	33		T22	169		T25	9
all_pins[11]	transitions[0x1=>0x0]	752735	1			T21	39		T22	208		T25	5
all_pins[12]	values[0x0]	2066972	1			T21	191		T22	364		T23	1
all_pins[12]	values[0x1]	1261331	1			T21	59		T22	496		T25	16
all_pins[12]	transitions[0x0=>0x1]	753772	1			T21	43		T22	309		T25	13
all_pins[12]	transitions[0x1=>0x0]	755454	1			T21	46		T22	121		T25	8
all_pins[13]	values[0x0]	2070995	1			T21	202		T22	585		T23	1
all_pins[13]	values[0x1]	1257308	1			T21	48		T22	275		T25	22
all_pins[13]	transitions[0x0=>0x1]	751561	1			T21	48		T22	106		T25	19
all_pins[13]	transitions[0x1=>0x0]	755584	1			T21	59		T22	327		T25	13
all_pins[14]	values[0x0]	2063116	1			T21	218		T22	567		T23	1
all_pins[14]	values[0x1]	1265187	1			T21	32		T22	293		T25	23
all_pins[14]	transitions[0x0=>0x1]	757659	1			T21	32		T22	202		T25	14
all_pins[14]	transitions[0x1=>0x0]	749780	1			T21	48		T22	184		T25	13
all_pins[15]	values[0x0]	2065866	1			T21	209		T22	645		T23	1
all_pins[15]	values[0x1]	1262437	1			T21	41		T22	215		T25	12
all_pins[15]	transitions[0x0=>0x1]	753790	1			T21	31		T22	148		T25	3
all_pins[15]	transitions[0x1=>0x0]	756540	1			T21	22		T22	226		T25	14
all_pins[16]	values[0x0]	2067508	1			T21	167		T22	433		T23	1
all_pins[16]	values[0x1]	1260795	1			T21	83		T22	427		T25	19
all_pins[16]	transitions[0x0=>0x1]	754249	1			T21	77		T22	330		T25	18
all_pins[16]	transitions[0x1=>0x0]	755891	1			T21	35		T22	118		T25	11
all_pins[17]	values[0x0]	2065283	1			T21	188		T22	550		T23	1
all_pins[17]	values[0x1]	1263020	1			T21	62		T22	310		T25	19
all_pins[17]	transitions[0x0=>0x1]	756358	1			T21	54		T22	129		T25	13
all_pins[17]	transitions[0x1=>0x0]	754133	1			T21	75		T22	246		T25	13
all_pins[18]	values[0x0]	2070347	1			T21	118		T22	513		T23	1
all_pins[18]	values[0x1]	1257956	1			T21	132		T22	347		T25	23
all_pins[18]	transitions[0x0=>0x1]	752227	1			T21	87		T22	280		T25	13
all_pins[18]	transitions[0x1=>0x0]	757291	1			T21	17		T22	243		T25	9
all_pins[19]	values[0x0]	2064833	1			T21	130		T22	430		T23	1
all_pins[19]	values[0x1]	1263470	1			T21	120		T22	430		T25	23
all_pins[19]	transitions[0x0=>0x1]	755024	1			T21	64		T22	259		T25	13
all_pins[19]	transitions[0x1=>0x0]	749510	1			T21	76		T22	176		T25	13
all_pins[20]	values[0x0]	2068651	1			T21	133		T22	512		T23	1
all_pins[20]	values[0x1]	1259652	1			T21	117		T22	348		T25	20
all_pins[20]	transitions[0x0=>0x1]	750171	1			T21	32		T22	135		T25	14
all_pins[20]	transitions[0x1=>0x0]	753989	1			T21	35		T22	217		T25	17
all_pins[21]	values[0x0]	2071582	1			T21	187		T22	633		T23	1
all_pins[21]	values[0x1]	1256721	1			T21	63		T22	227		T25	14
all_pins[21]	transitions[0x0=>0x1]	751832	1			T21	30		T22	143		T25	12
all_pins[21]	transitions[0x1=>0x0]	754763	1			T21	84		T22	264		T25	18
all_pins[22]	values[0x0]	2075017	1			T21	192		T22	497		T23	1
all_pins[22]	values[0x1]	1253286	1			T21	58		T22	363		T25	21
all_pins[22]	transitions[0x0=>0x1]	751480	1			T21	58		T22	238		T25	15
all_pins[22]	transitions[0x1=>0x0]	754915	1			T21	63		T22	102		T25	8
all_pins[23]	values[0x0]	2065274	1			T21	204		T22	558		T23	1
all_pins[23]	values[0x1]	1263029	1			T21	46		T22	302		T25	21
all_pins[23]	transitions[0x0=>0x1]	759447	1			T21	24		T22	200		T25	9
all_pins[23]	transitions[0x1=>0x0]	749704	1			T21	36		T22	261		T25	9
all_pins[24]	values[0x0]	2066243	1			T21	224		T22	521		T23	1
all_pins[24]	values[0x1]	1262060	1			T21	26		T22	339		T25	2
all_pins[24]	transitions[0x0=>0x1]	754988	1			T21	15		T22	176		T25	2
all_pins[24]	transitions[0x1=>0x0]	755957	1			T21	35		T22	139		T25	21
all_pins[25]	values[0x0]	2065531	1			T21	203		T22	585		T23	1
all_pins[25]	values[0x1]	1262772	1			T21	47		T22	275		T25	4
all_pins[25]	transitions[0x0=>0x1]	755244	1			T21	47		T22	128		T25	4
all_pins[25]	transitions[0x1=>0x0]	754532	1			T21	26		T22	192		T25	2
all_pins[26]	values[0x0]	2070036	1			T21	119		T22	519		T23	1
all_pins[26]	values[0x1]	1258267	1			T21	131		T22	341		T25	21
all_pins[26]	transitions[0x0=>0x1]	752602	1			T21	122		T22	181		T25	17
all_pins[26]	transitions[0x1=>0x0]	757107	1			T21	38		T22	115		T26	2
all_pins[27]	values[0x0]	2071346	1			T21	188		T22	562		T23	1
all_pins[27]	values[0x1]	1256957	1			T21	62		T22	298		T25	9
all_pins[27]	transitions[0x0=>0x1]	752198	1			T21	16		T22	202		T25	3
all_pins[27]	transitions[0x1=>0x0]	753508	1			T21	85		T22	245		T25	15
all_pins[28]	values[0x0]	2066196	1			T21	136		T22	482		T23	1
all_pins[28]	values[0x1]	1262107	1			T21	114		T22	378		T25	10
all_pins[28]	transitions[0x0=>0x1]	756819	1			T21	62		T22	233		T25	7
all_pins[28]	transitions[0x1=>0x0]	751669	1			T21	10		T22	153		T25	6
all_pins[29]	values[0x0]	2067008	1			T21	145		T22	355		T23	1
all_pins[29]	values[0x1]	1261295	1			T21	105		T22	505		T25	10
all_pins[29]	transitions[0x0=>0x1]	754876	1			T21	51		T22	263		T25	8
all_pins[29]	transitions[0x1=>0x0]	755688	1			T21	60		T22	136		T25	8
all_pins[30]	values[0x0]	2067787	1			T21	100		T22	560		T23	1
all_pins[30]	values[0x1]	1260516	1			T21	150		T22	300		T25	31
all_pins[30]	transitions[0x0=>0x1]	755020	1			T21	62		T22	134		T25	25
all_pins[30]	transitions[0x1=>0x0]	755799	1			T21	17		T22	339		T25	4
all_pins[31]	values[0x0]	2062477	1			T21	142		T22	552		T23	1
all_pins[31]	values[0x1]	1265826	1			T21	108		T22	308		T25	18
all_pins[31]	transitions[0x0=>0x1]	756259	1			T21	11		T22	201		T25	11
all_pins[31]	transitions[0x1=>0x0]	750949	1			T21	53		T22	193		T25	24