Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
data_oe	2	0	2	100.00	100	1	1	2
data_out	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_all	192	0	192	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	11248667	1			T21	446		T22	1415		T23	56
bins_for_gpio_bits[1]	11248667	1			T21	446		T22	1415		T23	56
bins_for_gpio_bits[2]	11248667	1			T21	446		T22	1415		T23	56
bins_for_gpio_bits[3]	11248667	1			T21	446		T22	1415		T23	56
bins_for_gpio_bits[4]	11248667	1			T21	446		T22	1415		T23	56
bins_for_gpio_bits[5]	11248667	1			T21	446		T22	1415		T23	56
bins_for_gpio_bits[6]	11248667	1			T21	446		T22	1415		T23	56
bins_for_gpio_bits[7]	11248667	1			T21	446		T22	1415		T23	56
bins_for_gpio_bits[8]	11248667	1			T21	446		T22	1415		T23	56
bins_for_gpio_bits[9]	11248667	1			T21	446		T22	1415		T23	56
bins_for_gpio_bits[10]	11248667	1			T21	446		T22	1415		T23	56
bins_for_gpio_bits[11]	11248667	1			T21	446		T22	1415		T23	56
bins_for_gpio_bits[12]	11248667	1			T21	446		T22	1415		T23	56
bins_for_gpio_bits[13]	11248667	1			T21	446		T22	1415		T23	56
bins_for_gpio_bits[14]	11248667	1			T21	446		T22	1415		T23	56
bins_for_gpio_bits[15]	11248667	1			T21	446		T22	1415		T23	56
bins_for_gpio_bits[16]	11248667	1			T21	446		T22	1415		T23	56
bins_for_gpio_bits[17]	11248667	1			T21	446		T22	1415		T23	56
bins_for_gpio_bits[18]	11248667	1			T21	446		T22	1415		T23	56
bins_for_gpio_bits[19]	11248667	1			T21	446		T22	1415		T23	56
bins_for_gpio_bits[20]	11248667	1			T21	446		T22	1415		T23	56
bins_for_gpio_bits[21]	11248667	1			T21	446		T22	1415		T23	56
bins_for_gpio_bits[22]	11248667	1			T21	446		T22	1415		T23	56
bins_for_gpio_bits[23]	11248667	1			T21	446		T22	1415		T23	56
bins_for_gpio_bits[24]	11248667	1			T21	446		T22	1415		T23	56
bins_for_gpio_bits[25]	11248667	1			T21	446		T22	1415		T23	56
bins_for_gpio_bits[26]	11248667	1			T21	446		T22	1415		T23	56
bins_for_gpio_bits[27]	11248667	1			T21	446		T22	1415		T23	56
bins_for_gpio_bits[28]	11248667	1			T21	446		T22	1415		T23	56
bins_for_gpio_bits[29]	11248667	1			T21	446		T22	1415		T23	56
bins_for_gpio_bits[30]	11248667	1			T21	446		T22	1415		T23	56
bins_for_gpio_bits[31]	11248667	1			T21	446		T22	1415		T23	56

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

205922567

1

T21

7168

T22

22521

T23

1410

auto[1]

154034777

1

T21

7104

T22

22759

T23

382

---

Summary for Variable data_oe

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_oe

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

291457904

1

T21

14272

T22

45280

T23

1710

auto[1]

68499440

1

T23

82

T24

7327

T25

203

---

Summary for Variable data_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

271200489

1

T21

14272

T22

45280

T23

1242

auto[1]

88756855

1

T23

550

T24

12536

T25

747

---

Summary for Cross cp_cross_all

Samples crossed: cp_pin data_out data_oe data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_all

Bins

cp_pin	data_out	data_oe	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[0]	4100796	1			T21	192		T22	711		T23	6
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[1]	3292587	1			T21	254		T22	704		T24	33
bins_for_gpio_bits[0]	auto[0]	auto[1]	auto[0]	1076674	1			T23	2		T24	121		T25	5
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[0]	1254723	1			T23	38		T24	213		T25	6
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[1]	454887	1			T23	6		T24	22		T25	11
bins_for_gpio_bits[0]	auto[1]	auto[1]	auto[1]	1069000	1			T23	4		T24	118		T25	13
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[0]	4093921	1			T21	232		T22	725		T23	3
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[1]	3304454	1			T21	214		T22	690		T23	3
bins_for_gpio_bits[1]	auto[0]	auto[1]	auto[0]	1071987	1			T24	132		T25	4		T27	2
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[0]	1254861	1			T23	39		T24	276		T25	15
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[1]	456101	1			T23	11		T24	35		T25	7
bins_for_gpio_bits[1]	auto[1]	auto[1]	auto[1]	1067343	1			T24	129		T25	1		T26	3
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[0]	4108246	1			T21	230		T22	696		T23	50
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[1]	3290710	1			T21	216		T22	719		T23	6
bins_for_gpio_bits[2]	auto[0]	auto[1]	auto[0]	1073505	1			T24	126		T27	4		T29	6646
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[0]	1253044	1			T24	276		T25	27		T26	13
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[1]	458100	1			T24	38		T25	4		T27	13
bins_for_gpio_bits[2]	auto[1]	auto[1]	auto[1]	1065062	1			T24	120		T25	4		T27	11
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[0]	4103937	1			T21	197		T22	698		T23	27
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[1]	3293267	1			T21	249		T22	717		T23	15
bins_for_gpio_bits[3]	auto[0]	auto[1]	auto[0]	1078633	1			T23	7		T24	145		T25	3
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[0]	1252590	1			T23	5		T24	251		T25	15
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[1]	454400	1			T24	30		T25	3		T26	1
bins_for_gpio_bits[3]	auto[1]	auto[1]	auto[1]	1065840	1			T23	2		T24	86		T25	2
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[0]	4109974	1			T21	225		T22	710		T23	11
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[1]	3285562	1			T21	221		T22	705		T23	2
bins_for_gpio_bits[4]	auto[0]	auto[1]	auto[0]	1081735	1			T24	101		T27	6		T29	6485
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[0]	1249075	1			T23	38		T24	290		T25	14
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[1]	454527	1			T23	5		T24	34		T25	9
bins_for_gpio_bits[4]	auto[1]	auto[1]	auto[1]	1067794	1			T24	133		T26	6		T27	3
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[0]	4111400	1			T21	223		T22	679		T23	6
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[1]	3290986	1			T21	223		T22	736		T23	2
bins_for_gpio_bits[5]	auto[0]	auto[1]	auto[0]	1075286	1			T24	131		T25	7		T27	9
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[0]	1250108	1			T23	38		T24	237		T26	8
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[1]	456526	1			T23	7		T24	26		T25	9
bins_for_gpio_bits[5]	auto[1]	auto[1]	auto[1]	1064361	1			T23	3		T24	132		T25	8
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[0]	4105773	1			T21	223		T22	720		T23	32
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[1]	3290322	1			T21	223		T22	695		T23	13
bins_for_gpio_bits[6]	auto[0]	auto[1]	auto[0]	1075648	1			T23	4		T24	90		T25	4
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[0]	1253485	1			T23	5		T24	285		T25	3
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[1]	458685	1			T24	33		T25	5		T26	4
bins_for_gpio_bits[6]	auto[1]	auto[1]	auto[1]	1064754	1			T23	2		T24	109		T25	4
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[0]	4109478	1			T21	222		T22	718		T23	47
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[1]	3284276	1			T21	224		T22	697		T23	6
bins_for_gpio_bits[7]	auto[0]	auto[1]	auto[0]	1081000	1			T23	3		T24	171		T25	8
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[0]	1251737	1			T24	142		T25	12		T27	20
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[1]	457206	1			T24	29		T25	2		T26	7
bins_for_gpio_bits[7]	auto[1]	auto[1]	auto[1]	1064970	1			T24	78		T25	6		T26	16
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[0]	4101623	1			T21	227		T22	702		T23	8
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[1]	3293945	1			T21	219		T22	713		T24	26
bins_for_gpio_bits[8]	auto[0]	auto[1]	auto[0]	1080467	1			T24	129		T25	1		T29	6612
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[0]	1246790	1			T23	30		T24	271		T25	17
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[1]	455904	1			T23	15		T24	31		T25	6
bins_for_gpio_bits[8]	auto[1]	auto[1]	auto[1]	1069938	1			T23	3		T24	132		T25	2
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[0]	4103408	1			T21	228		T22	685		T23	6
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[1]	3288993	1			T21	218		T22	730		T23	3
bins_for_gpio_bits[9]	auto[0]	auto[1]	auto[0]	1075991	1			T24	169		T25	4		T27	6
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[0]	1253100	1			T23	36		T24	186		T25	9
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[1]	456653	1			T23	8		T24	22		T25	3
bins_for_gpio_bits[9]	auto[1]	auto[1]	auto[1]	1070522	1			T23	3		T24	89		T27	26
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[0]	4106039	1			T21	242		T22	708		T23	28
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[1]	3288416	1			T21	204		T22	707		T23	14
bins_for_gpio_bits[10]	auto[0]	auto[1]	auto[0]	1079123	1			T23	7		T24	87		T25	3
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[0]	1253120	1			T23	4		T24	335		T25	8
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[1]	455616	1			T23	1		T24	24		T25	7
bins_for_gpio_bits[10]	auto[1]	auto[1]	auto[1]	1066353	1			T23	2		T24	112		T27	16
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[0]	4100351	1			T21	222		T22	701		T23	5
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[1]	3294765	1			T21	224		T22	714		T23	3
bins_for_gpio_bits[11]	auto[0]	auto[1]	auto[0]	1078781	1			T24	109		T25	5		T27	7
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[0]	1252238	1			T23	37		T24	230		T25	11
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[1]	457821	1			T23	8		T24	33		T25	7
bins_for_gpio_bits[11]	auto[1]	auto[1]	auto[1]	1064711	1			T23	3		T24	140		T25	18
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[0]	4114490	1			T21	234		T22	711		T23	44
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[1]	3281862	1			T21	212		T22	704		T23	12
bins_for_gpio_bits[12]	auto[0]	auto[1]	auto[0]	1077368	1			T24	98		T27	9		T29	6451
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[0]	1250974	1			T24	251		T25	19		T26	10
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[1]	453561	1			T24	36		T25	8		T26	13
bins_for_gpio_bits[12]	auto[1]	auto[1]	auto[1]	1070412	1			T24	107		T26	6		T27	14
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[0]	4108561	1			T21	223		T22	711		T23	9
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[1]	3289630	1			T21	223		T22	704		T23	2
bins_for_gpio_bits[13]	auto[0]	auto[1]	auto[0]	1076833	1			T24	112		T25	3		T27	10
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[0]	1249239	1			T23	37		T24	307		T25	30
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[1]	456919	1			T23	8		T24	48		T25	10
bins_for_gpio_bits[13]	auto[1]	auto[1]	auto[1]	1067485	1			T24	90		T25	3		T26	13
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[0]	4113080	1			T21	217		T22	692		T23	44
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[1]	3280954	1			T21	229		T22	723		T23	6
bins_for_gpio_bits[14]	auto[0]	auto[1]	auto[0]	1075021	1			T24	122		T27	9		T29	6365
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[0]	1252979	1			T23	5		T24	199		T25	5
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[1]	455927	1			T23	1		T24	31		T25	9
bins_for_gpio_bits[14]	auto[1]	auto[1]	auto[1]	1070706	1			T24	67		T25	18		T26	7
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[0]	4106932	1			T21	228		T22	689		T23	30
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[1]	3296614	1			T21	218		T22	726		T23	14
bins_for_gpio_bits[15]	auto[0]	auto[1]	auto[0]	1076783	1			T23	3		T24	136		T25	4
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[0]	1244527	1			T23	8		T24	271		T25	8
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[1]	452666	1			T23	1		T24	39		T25	5
bins_for_gpio_bits[15]	auto[1]	auto[1]	auto[1]	1071145	1			T24	95		T25	6		T27	20
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[0]	4120097	1			T21	245		T22	694		T23	34
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[1]	3288745	1			T21	201		T22	721		T23	14
bins_for_gpio_bits[16]	auto[0]	auto[1]	auto[0]	1072182	1			T23	8		T24	117		T26	1
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[0]	1255372	1			T24	197		T25	2		T26	6
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[1]	455309	1			T24	30		T25	16		T26	5
bins_for_gpio_bits[16]	auto[1]	auto[1]	auto[1]	1056962	1			T24	159		T25	18		T26	9
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[0]	4114696	1			T21	219		T22	701		T23	39
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[1]	3288649	1			T21	227		T22	714		T23	10
bins_for_gpio_bits[17]	auto[0]	auto[1]	auto[0]	1075806	1			T24	71		T26	2		T27	2
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[0]	1254072	1			T23	6		T24	301		T25	4
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[1]	456594	1			T23	1		T24	50		T25	10
bins_for_gpio_bits[17]	auto[1]	auto[1]	auto[1]	1058850	1			T24	136		T25	2		T27	11
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[0]	4119996	1			T21	237		T22	703		T23	36
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[1]	3282111	1			T21	209		T22	712		T23	13
bins_for_gpio_bits[18]	auto[0]	auto[1]	auto[0]	1074604	1			T24	116		T25	1		T26	1
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[0]	1250134	1			T23	7		T24	264		T25	12
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[1]	456450	1			T24	30		T25	6		T26	4
bins_for_gpio_bits[18]	auto[1]	auto[1]	auto[1]	1065372	1			T24	70		T26	1		T27	19
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[0]	4099729	1			T21	223		T22	702		T23	16
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[1]	3305067	1			T21	223		T22	713		T23	6
bins_for_gpio_bits[19]	auto[0]	auto[1]	auto[0]	1072396	1			T24	74		T25	6		T26	2
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[0]	1253811	1			T23	30		T24	304		T25	9
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[1]	454500	1			T23	4		T24	38		T25	3
bins_for_gpio_bits[19]	auto[1]	auto[1]	auto[1]	1063164	1			T24	109		T26	2		T27	1
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[0]	4119482	1			T21	234		T22	705		T23	48
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[1]	3286443	1			T21	212		T22	710		T23	8
bins_for_gpio_bits[20]	auto[0]	auto[1]	auto[0]	1071977	1			T24	166		T26	1		T27	9
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[0]	1249541	1			T24	244		T25	1		T26	5
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[1]	457538	1			T24	30		T25	8		T26	8
bins_for_gpio_bits[20]	auto[1]	auto[1]	auto[1]	1063686	1			T24	104		T25	3		T26	2
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[0]	4102257	1			T21	224		T22	695		T23	32
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[1]	3298226	1			T21	222		T22	720		T23	11
bins_for_gpio_bits[21]	auto[0]	auto[1]	auto[0]	1072354	1			T24	76		T26	2		T27	4
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[0]	1252523	1			T23	10		T24	322		T25	6
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[1]	457379	1			T23	3		T24	25		T25	8
bins_for_gpio_bits[21]	auto[1]	auto[1]	auto[1]	1065928	1			T24	121		T26	1		T27	11
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[0]	4103652	1			T21	204		T22	696		T23	41
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[1]	3294403	1			T21	242		T22	719		T23	15
bins_for_gpio_bits[22]	auto[0]	auto[1]	auto[0]	1069770	1			T24	117		T25	2		T27	1
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[0]	1254284	1			T24	296		T25	13		T26	8
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[1]	458030	1			T24	38		T25	9		T27	13
bins_for_gpio_bits[22]	auto[1]	auto[1]	auto[1]	1068528	1			T24	118		T25	2		T27	1
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[0]	4110851	1			T21	226		T22	701		T23	34
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[1]	3294486	1			T21	220		T22	714		T23	10
bins_for_gpio_bits[23]	auto[0]	auto[1]	auto[0]	1075994	1			T23	5		T24	138		T26	10
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[0]	1248490	1			T23	6		T24	246		T25	1
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[1]	454852	1			T23	1		T24	25		T25	18
bins_for_gpio_bits[23]	auto[1]	auto[1]	auto[1]	1063994	1			T24	91		T25	2		T27	12
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[0]	4100825	1			T21	208		T22	696		T23	37
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[1]	3303035	1			T21	238		T22	719		T23	6
bins_for_gpio_bits[24]	auto[0]	auto[1]	auto[0]	1080195	1			T23	6		T24	155		T26	3
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[0]	1252166	1			T23	5		T24	187		T25	16
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[1]	454435	1			T24	39		T25	7		T27	25
bins_for_gpio_bits[24]	auto[1]	auto[1]	auto[1]	1058011	1			T23	2		T24	110		T27	23
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[0]	4123393	1			T21	224		T22	719		T23	42
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[1]	3279948	1			T21	222		T22	696		T23	14
bins_for_gpio_bits[25]	auto[0]	auto[1]	auto[0]	1070274	1			T24	82		T25	2		T26	2
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[0]	1253771	1			T24	276		T25	8		T26	10
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[1]	456478	1			T24	28		T25	7		T26	9
bins_for_gpio_bits[25]	auto[1]	auto[1]	auto[1]	1064803	1			T24	93		T26	3		T27	3
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[0]	4103331	1			T21	225		T22	725		T23	41
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[1]	3295105	1			T21	221		T22	690		T23	8
bins_for_gpio_bits[26]	auto[0]	auto[1]	auto[0]	1068758	1			T24	125		T26	4		T27	4
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[0]	1255528	1			T23	6		T24	267		T25	10
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[1]	457819	1			T23	1		T24	35		T25	7
bins_for_gpio_bits[26]	auto[1]	auto[1]	auto[1]	1068126	1			T24	105		T25	1		T26	1
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[0]	4111095	1			T21	228		T22	691		T23	15
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[1]	3291827	1			T21	218		T22	724		T23	7
bins_for_gpio_bits[27]	auto[0]	auto[1]	auto[0]	1072625	1			T24	156		T26	1		T27	8
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[0]	1251965	1			T23	30		T24	237		T25	25
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[1]	456882	1			T23	4		T24	24		T25	14
bins_for_gpio_bits[27]	auto[1]	auto[1]	auto[1]	1064273	1			T24	61		T25	11		T26	2
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[0]	4111491	1			T21	232		T22	683		T23	46
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[1]	3294876	1			T21	214		T22	732		T23	10
bins_for_gpio_bits[28]	auto[0]	auto[1]	auto[0]	1071153	1			T24	135		T26	3		T27	9
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[0]	1255941	1			T24	209		T25	17		T26	5
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[1]	458233	1			T24	20		T25	5		T26	1
bins_for_gpio_bits[28]	auto[1]	auto[1]	auto[1]	1056973	1			T24	119		T25	2		T26	5
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[0]	4108806	1			T21	223		T22	723		T23	32
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[1]	3296835	1			T21	223		T22	692		T23	12
bins_for_gpio_bits[29]	auto[0]	auto[1]	auto[0]	1077053	1			T23	5		T24	125		T26	2
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[0]	1249870	1			T23	7		T24	207		T25	8
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[1]	453546	1			T24	19		T25	24		T27	11
bins_for_gpio_bits[29]	auto[1]	auto[1]	auto[1]	1062557	1			T24	94		T25	10		T27	2
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[0]	4090926	1			T21	228		T22	721		T23	27
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[1]	3308825	1			T21	218		T22	694		T23	16
bins_for_gpio_bits[30]	auto[0]	auto[1]	auto[0]	1073062	1			T23	6		T24	157		T26	2
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[0]	1254779	1			T23	5		T24	238		T25	1
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[1]	455798	1			T24	37		T25	4		T26	8
bins_for_gpio_bits[30]	auto[1]	auto[1]	auto[1]	1065277	1			T23	2		T24	87		T25	1
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[0]	4110165	1			T21	223		T22	710		T23	39
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[1]	3288790	1			T21	223		T22	705		T23	10
bins_for_gpio_bits[31]	auto[0]	auto[1]	auto[0]	1073936	1			T24	118		T25	2		T26	1
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[0]	1251955	1			T23	7		T24	294		T25	17
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[1]	458255	1			T24	28		T25	8		T26	1
bins_for_gpio_bits[31]	auto[1]	auto[1]	auto[1]	1065566	1			T24	106		T25	2		T27	15

User Defined Cross Bins for cp_cross_all

Excluded/Illegal bins

NAME	COUNT	STATUS
data_oe_1_data_out_0_data_in_1	0	Illegal
data_oe_1_data_out_1_data_in_0	0	Illegal