Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
gpio_value	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_pins_data_in	128	0	128	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	11248667	1			T21	446		T22	1415		T23	56
bins_for_gpio_bits[1]	11248667	1			T21	446		T22	1415		T23	56
bins_for_gpio_bits[2]	11248667	1			T21	446		T22	1415		T23	56
bins_for_gpio_bits[3]	11248667	1			T21	446		T22	1415		T23	56
bins_for_gpio_bits[4]	11248667	1			T21	446		T22	1415		T23	56
bins_for_gpio_bits[5]	11248667	1			T21	446		T22	1415		T23	56
bins_for_gpio_bits[6]	11248667	1			T21	446		T22	1415		T23	56
bins_for_gpio_bits[7]	11248667	1			T21	446		T22	1415		T23	56
bins_for_gpio_bits[8]	11248667	1			T21	446		T22	1415		T23	56
bins_for_gpio_bits[9]	11248667	1			T21	446		T22	1415		T23	56
bins_for_gpio_bits[10]	11248667	1			T21	446		T22	1415		T23	56
bins_for_gpio_bits[11]	11248667	1			T21	446		T22	1415		T23	56
bins_for_gpio_bits[12]	11248667	1			T21	446		T22	1415		T23	56
bins_for_gpio_bits[13]	11248667	1			T21	446		T22	1415		T23	56
bins_for_gpio_bits[14]	11248667	1			T21	446		T22	1415		T23	56
bins_for_gpio_bits[15]	11248667	1			T21	446		T22	1415		T23	56
bins_for_gpio_bits[16]	11248667	1			T21	446		T22	1415		T23	56
bins_for_gpio_bits[17]	11248667	1			T21	446		T22	1415		T23	56
bins_for_gpio_bits[18]	11248667	1			T21	446		T22	1415		T23	56
bins_for_gpio_bits[19]	11248667	1			T21	446		T22	1415		T23	56
bins_for_gpio_bits[20]	11248667	1			T21	446		T22	1415		T23	56
bins_for_gpio_bits[21]	11248667	1			T21	446		T22	1415		T23	56
bins_for_gpio_bits[22]	11248667	1			T21	446		T22	1415		T23	56
bins_for_gpio_bits[23]	11248667	1			T21	446		T22	1415		T23	56
bins_for_gpio_bits[24]	11248667	1			T21	446		T22	1415		T23	56
bins_for_gpio_bits[25]	11248667	1			T21	446		T22	1415		T23	56
bins_for_gpio_bits[26]	11248667	1			T21	446		T22	1415		T23	56
bins_for_gpio_bits[27]	11248667	1			T21	446		T22	1415		T23	56
bins_for_gpio_bits[28]	11248667	1			T21	446		T22	1415		T23	56
bins_for_gpio_bits[29]	11248667	1			T21	446		T22	1415		T23	56
bins_for_gpio_bits[30]	11248667	1			T21	446		T22	1415		T23	56
bins_for_gpio_bits[31]	11248667	1			T21	446		T22	1415		T23	56

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

205922567

1

T21

7168

T22

22521

T23

1410

auto[1]

154034777

1

T21

7104

T22

22759

T23

382

---

Summary for Variable gpio_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for gpio_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

205917138

1

T21

7168

T22

22521

T23

1410

auto[1]

154040206

1

T21

7104

T22

22759

T23

382

---

Summary for Cross cp_cross_pins_data_in

Samples crossed: cp_pin gpio_value data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_cross_pins_data_in

Bins

cp_pin	gpio_value	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	6240843	1			T21	192		T22	711		T23	44
bins_for_gpio_bits[0]	auto[0]	auto[1]	191171	1			T23	2		T24	17		T25	1
bins_for_gpio_bits[0]	auto[1]	auto[0]	191350	1			T23	2		T24	17		T29	1215
bins_for_gpio_bits[0]	auto[1]	auto[1]	4625303	1			T21	254		T22	704		T23	8
bins_for_gpio_bits[1]	auto[0]	auto[0]	6229219	1			T21	232		T22	725		T23	42
bins_for_gpio_bits[1]	auto[0]	auto[1]	191392	1			T24	22		T29	1241		T30	34
bins_for_gpio_bits[1]	auto[1]	auto[0]	191550	1			T24	22		T29	1239		T30	35
bins_for_gpio_bits[1]	auto[1]	auto[1]	4636506	1			T21	214		T22	690		T23	14
bins_for_gpio_bits[2]	auto[0]	auto[0]	6243626	1			T21	230		T22	696		T23	50
bins_for_gpio_bits[2]	auto[0]	auto[1]	190963	1			T24	20		T29	1237		T30	40
bins_for_gpio_bits[2]	auto[1]	auto[0]	191169	1			T24	20		T29	1234		T30	41
bins_for_gpio_bits[2]	auto[1]	auto[1]	4622909	1			T21	216		T22	719		T23	6
bins_for_gpio_bits[3]	auto[0]	auto[0]	6244013	1			T21	197		T22	698		T23	38
bins_for_gpio_bits[3]	auto[0]	auto[1]	190972	1			T23	1		T24	16		T27	1
bins_for_gpio_bits[3]	auto[1]	auto[0]	191147	1			T23	1		T24	17		T29	1219
bins_for_gpio_bits[3]	auto[1]	auto[1]	4622535	1			T21	249		T22	717		T23	16
bins_for_gpio_bits[4]	auto[0]	auto[0]	6249361	1			T21	225		T22	710		T23	49
bins_for_gpio_bits[4]	auto[0]	auto[1]	191231	1			T24	18		T29	1234		T30	30
bins_for_gpio_bits[4]	auto[1]	auto[0]	191423	1			T24	18		T29	1232		T30	30
bins_for_gpio_bits[4]	auto[1]	auto[1]	4616652	1			T21	221		T22	705		T23	7
bins_for_gpio_bits[5]	auto[0]	auto[0]	6246022	1			T21	223		T22	679		T23	43
bins_for_gpio_bits[5]	auto[0]	auto[1]	190635	1			T23	1		T24	19		T25	1
bins_for_gpio_bits[5]	auto[1]	auto[0]	190772	1			T23	1		T24	19		T25	1
bins_for_gpio_bits[5]	auto[1]	auto[1]	4621238	1			T21	223		T22	736		T23	11
bins_for_gpio_bits[6]	auto[0]	auto[0]	6243966	1			T21	223		T22	720		T23	40
bins_for_gpio_bits[6]	auto[0]	auto[1]	190786	1			T23	1		T24	16		T27	1
bins_for_gpio_bits[6]	auto[1]	auto[0]	190940	1			T23	1		T24	16		T29	1259
bins_for_gpio_bits[6]	auto[1]	auto[1]	4622975	1			T21	223		T22	695		T23	14
bins_for_gpio_bits[7]	auto[0]	auto[0]	6250976	1			T21	222		T22	718		T23	50
bins_for_gpio_bits[7]	auto[0]	auto[1]	191061	1			T24	14		T25	1		T29	1180
bins_for_gpio_bits[7]	auto[1]	auto[0]	191239	1			T24	14		T25	1		T29	1176
bins_for_gpio_bits[7]	auto[1]	auto[1]	4615391	1			T21	224		T22	697		T23	6
bins_for_gpio_bits[8]	auto[0]	auto[0]	6237315	1			T21	227		T22	702		T23	37
bins_for_gpio_bits[8]	auto[0]	auto[1]	191448	1			T23	1		T24	22		T29	1249
bins_for_gpio_bits[8]	auto[1]	auto[0]	191565	1			T23	1		T24	22		T29	1246
bins_for_gpio_bits[8]	auto[1]	auto[1]	4628339	1			T21	219		T22	713		T23	17
bins_for_gpio_bits[9]	auto[0]	auto[0]	6240610	1			T21	228		T22	685		T23	41
bins_for_gpio_bits[9]	auto[0]	auto[1]	191728	1			T23	1		T24	13		T27	1
bins_for_gpio_bits[9]	auto[1]	auto[0]	191889	1			T23	1		T24	13		T27	1
bins_for_gpio_bits[9]	auto[1]	auto[1]	4624440	1			T21	218		T22	730		T23	13
bins_for_gpio_bits[10]	auto[0]	auto[0]	6247172	1			T21	242		T22	708		T23	38
bins_for_gpio_bits[10]	auto[0]	auto[1]	190965	1			T23	1		T24	19		T29	1242
bins_for_gpio_bits[10]	auto[1]	auto[0]	191110	1			T23	1		T24	19		T29	1238
bins_for_gpio_bits[10]	auto[1]	auto[1]	4619420	1			T21	204		T22	707		T23	16
bins_for_gpio_bits[11]	auto[0]	auto[0]	6240525	1			T21	222		T22	701		T23	41
bins_for_gpio_bits[11]	auto[0]	auto[1]	190679	1			T23	1		T24	23		T25	1
bins_for_gpio_bits[11]	auto[1]	auto[0]	190845	1			T23	1		T24	23		T25	1
bins_for_gpio_bits[11]	auto[1]	auto[1]	4626618	1			T21	224		T22	714		T23	13
bins_for_gpio_bits[12]	auto[0]	auto[0]	6251353	1			T21	234		T22	711		T23	44
bins_for_gpio_bits[12]	auto[0]	auto[1]	191296	1			T24	24		T27	1		T29	1212
bins_for_gpio_bits[12]	auto[1]	auto[0]	191479	1			T24	24		T29	1207		T30	42
bins_for_gpio_bits[12]	auto[1]	auto[1]	4614539	1			T21	212		T22	704		T23	12
bins_for_gpio_bits[13]	auto[0]	auto[0]	6243488	1			T21	223		T22	711		T23	46
bins_for_gpio_bits[13]	auto[0]	auto[1]	190989	1			T24	18		T26	1		T27	2
bins_for_gpio_bits[13]	auto[1]	auto[0]	191145	1			T24	18		T29	1243		T30	37
bins_for_gpio_bits[13]	auto[1]	auto[1]	4623045	1			T21	223		T22	704		T23	10
bins_for_gpio_bits[14]	auto[0]	auto[0]	6249631	1			T21	217		T22	692		T23	49
bins_for_gpio_bits[14]	auto[0]	auto[1]	191265	1			T24	11		T29	1155		T30	45
bins_for_gpio_bits[14]	auto[1]	auto[0]	191449	1			T24	11		T29	1152		T30	45
bins_for_gpio_bits[14]	auto[1]	auto[1]	4616322	1			T21	229		T22	723		T23	7
bins_for_gpio_bits[15]	auto[0]	auto[0]	6236436	1			T21	228		T22	689		T23	41
bins_for_gpio_bits[15]	auto[0]	auto[1]	191605	1			T24	17		T27	1		T29	1240
bins_for_gpio_bits[15]	auto[1]	auto[0]	191806	1			T24	17		T29	1238		T30	40
bins_for_gpio_bits[15]	auto[1]	auto[1]	4628820	1			T21	218		T22	726		T23	15
bins_for_gpio_bits[16]	auto[0]	auto[0]	6257290	1			T21	245		T22	694		T23	42
bins_for_gpio_bits[16]	auto[0]	auto[1]	190202	1			T24	20		T27	1		T29	1237
bins_for_gpio_bits[16]	auto[1]	auto[0]	190361	1			T24	20		T27	1		T29	1233
bins_for_gpio_bits[16]	auto[1]	auto[1]	4610814	1			T21	201		T22	721		T23	14
bins_for_gpio_bits[17]	auto[0]	auto[0]	6253626	1			T21	219		T22	701		T23	45
bins_for_gpio_bits[17]	auto[0]	auto[1]	190722	1			T24	22		T29	1215		T30	45
bins_for_gpio_bits[17]	auto[1]	auto[0]	190948	1			T24	22		T29	1215		T30	45
bins_for_gpio_bits[17]	auto[1]	auto[1]	4613371	1			T21	227		T22	714		T23	11
bins_for_gpio_bits[18]	auto[0]	auto[0]	6253510	1			T21	237		T22	703		T23	43
bins_for_gpio_bits[18]	auto[0]	auto[1]	191037	1			T24	18		T27	2		T29	1248
bins_for_gpio_bits[18]	auto[1]	auto[0]	191224	1			T24	18		T27	2		T29	1242
bins_for_gpio_bits[18]	auto[1]	auto[1]	4612896	1			T21	209		T22	712		T23	13
bins_for_gpio_bits[19]	auto[0]	auto[0]	6234756	1			T21	223		T22	702		T23	46
bins_for_gpio_bits[19]	auto[0]	auto[1]	191013	1			T24	20		T29	1257		T30	40
bins_for_gpio_bits[19]	auto[1]	auto[0]	191180	1			T24	20		T29	1256		T30	41
bins_for_gpio_bits[19]	auto[1]	auto[1]	4631718	1			T21	223		T22	713		T23	10
bins_for_gpio_bits[20]	auto[0]	auto[0]	6249615	1			T21	234		T22	705		T23	48
bins_for_gpio_bits[20]	auto[0]	auto[1]	191238	1			T24	14		T27	1		T29	1282
bins_for_gpio_bits[20]	auto[1]	auto[0]	191385	1			T24	14		T27	1		T29	1277
bins_for_gpio_bits[20]	auto[1]	auto[1]	4616429	1			T21	212		T22	710		T23	8
bins_for_gpio_bits[21]	auto[0]	auto[0]	6235853	1			T21	224		T22	695		T23	42
bins_for_gpio_bits[21]	auto[0]	auto[1]	191142	1			T24	19		T29	1251		T30	34
bins_for_gpio_bits[21]	auto[1]	auto[0]	191281	1			T24	19		T29	1245		T30	35
bins_for_gpio_bits[21]	auto[1]	auto[1]	4630391	1			T21	222		T22	720		T23	14
bins_for_gpio_bits[22]	auto[0]	auto[0]	6236398	1			T21	204		T22	696		T23	41
bins_for_gpio_bits[22]	auto[0]	auto[1]	191142	1			T24	22		T29	1231		T30	40
bins_for_gpio_bits[22]	auto[1]	auto[0]	191308	1			T24	22		T29	1228		T30	40
bins_for_gpio_bits[22]	auto[1]	auto[1]	4629819	1			T21	242		T22	719		T23	15
bins_for_gpio_bits[23]	auto[0]	auto[0]	6243753	1			T21	226		T22	701		T23	45
bins_for_gpio_bits[23]	auto[0]	auto[1]	191398	1			T24	18		T27	2		T29	1245
bins_for_gpio_bits[23]	auto[1]	auto[0]	191582	1			T24	18		T27	1		T29	1240
bins_for_gpio_bits[23]	auto[1]	auto[1]	4621934	1			T21	220		T22	714		T23	11
bins_for_gpio_bits[24]	auto[0]	auto[0]	6242103	1			T21	208		T22	696		T23	47
bins_for_gpio_bits[24]	auto[0]	auto[1]	190929	1			T23	1		T24	19		T27	1
bins_for_gpio_bits[24]	auto[1]	auto[0]	191083	1			T23	1		T24	19		T29	1260
bins_for_gpio_bits[24]	auto[1]	auto[1]	4624552	1			T21	238		T22	719		T23	7
bins_for_gpio_bits[25]	auto[0]	auto[0]	6257247	1			T21	224		T22	719		T23	42
bins_for_gpio_bits[25]	auto[0]	auto[1]	190061	1			T24	16		T29	1211		T30	46
bins_for_gpio_bits[25]	auto[1]	auto[0]	190191	1			T24	16		T29	1210		T30	46
bins_for_gpio_bits[25]	auto[1]	auto[1]	4611168	1			T21	222		T22	696		T23	14
bins_for_gpio_bits[26]	auto[0]	auto[0]	6236381	1			T21	225		T22	725		T23	47
bins_for_gpio_bits[26]	auto[0]	auto[1]	191045	1			T24	20		T27	1		T29	1213
bins_for_gpio_bits[26]	auto[1]	auto[0]	191236	1			T24	20		T29	1207		T30	40
bins_for_gpio_bits[26]	auto[1]	auto[1]	4630005	1			T21	221		T22	690		T23	9
bins_for_gpio_bits[27]	auto[0]	auto[0]	6244553	1			T21	228		T22	691		T23	45
bins_for_gpio_bits[27]	auto[0]	auto[1]	190940	1			T24	13		T29	1232		T30	39
bins_for_gpio_bits[27]	auto[1]	auto[0]	191132	1			T24	13		T29	1229		T30	39
bins_for_gpio_bits[27]	auto[1]	auto[1]	4622042	1			T21	218		T22	724		T23	11
bins_for_gpio_bits[28]	auto[0]	auto[0]	6247620	1			T21	232		T22	683		T23	46
bins_for_gpio_bits[28]	auto[0]	auto[1]	190800	1			T24	19		T29	1278		T30	39
bins_for_gpio_bits[28]	auto[1]	auto[0]	190965	1			T24	19		T29	1273		T30	39
bins_for_gpio_bits[28]	auto[1]	auto[1]	4619282	1			T21	214		T22	732		T23	10
bins_for_gpio_bits[29]	auto[0]	auto[0]	6244493	1			T21	223		T22	723		T23	44
bins_for_gpio_bits[29]	auto[0]	auto[1]	191077	1			T24	17		T29	1219		T30	40
bins_for_gpio_bits[29]	auto[1]	auto[0]	191236	1			T24	17		T29	1217		T30	40
bins_for_gpio_bits[29]	auto[1]	auto[1]	4621861	1			T21	223		T22	692		T23	12
bins_for_gpio_bits[30]	auto[0]	auto[0]	6227349	1			T21	228		T22	721		T23	37
bins_for_gpio_bits[30]	auto[0]	auto[1]	191214	1			T23	1		T24	17		T27	1
bins_for_gpio_bits[30]	auto[1]	auto[0]	191418	1			T23	1		T24	17		T27	1
bins_for_gpio_bits[30]	auto[1]	auto[1]	4638686	1			T21	218		T22	694		T23	17
bins_for_gpio_bits[31]	auto[0]	auto[0]	6245001	1			T21	223		T22	710		T23	46
bins_for_gpio_bits[31]	auto[0]	auto[1]	190888	1			T24	19		T29	1245		T30	36
bins_for_gpio_bits[31]	auto[1]	auto[0]	191055	1			T24	19		T29	1239		T30	36
bins_for_gpio_bits[31]	auto[1]	auto[1]	4621723	1			T21	223		T22	705		T23	10