Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6803172 |
1 |
|
|
T21 |
330 |
|
T22 |
1132 |
|
T23 |
28 |
| auto[1] |
4632201 |
1 |
|
|
T21 |
259 |
|
T22 |
726 |
|
T25 |
26 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10843790 |
1 |
|
|
T21 |
528 |
|
T22 |
1655 |
|
T23 |
28 |
| auto[1] |
591583 |
1 |
|
|
T21 |
61 |
|
T22 |
203 |
|
T25 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6795236 |
1 |
|
|
T21 |
245 |
|
T22 |
842 |
|
T23 |
28 |
| auto[1] |
4640137 |
1 |
|
|
T21 |
344 |
|
T22 |
1016 |
|
T25 |
41 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2025740 |
1 |
|
|
T21 |
194 |
|
T22 |
428 |
|
T25 |
29 |
| auto[1] |
auto[0] |
auto[1] |
296346 |
1 |
|
|
T21 |
40 |
|
T22 |
104 |
|
T25 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2022814 |
1 |
|
|
T21 |
89 |
|
T22 |
385 |
|
T25 |
11 |
| auto[1] |
auto[1] |
auto[1] |
295237 |
1 |
|
|
T21 |
21 |
|
T22 |
99 |
|
T29 |
1666 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6824050 |
1 |
|
|
T21 |
253 |
|
T22 |
1007 |
|
T23 |
28 |
| auto[1] |
4611323 |
1 |
|
|
T21 |
336 |
|
T22 |
851 |
|
T25 |
55 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10843356 |
1 |
|
|
T21 |
527 |
|
T22 |
1706 |
|
T23 |
28 |
| auto[1] |
592017 |
1 |
|
|
T21 |
62 |
|
T22 |
152 |
|
T25 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6806229 |
1 |
|
|
T21 |
302 |
|
T22 |
1074 |
|
T23 |
28 |
| auto[1] |
4629144 |
1 |
|
|
T21 |
287 |
|
T22 |
784 |
|
T25 |
25 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2029858 |
1 |
|
|
T21 |
99 |
|
T22 |
281 |
|
T25 |
16 |
| auto[1] |
auto[0] |
auto[1] |
297460 |
1 |
|
|
T21 |
31 |
|
T22 |
67 |
|
T27 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2007269 |
1 |
|
|
T21 |
126 |
|
T22 |
351 |
|
T25 |
8 |
| auto[1] |
auto[1] |
auto[1] |
294557 |
1 |
|
|
T21 |
31 |
|
T22 |
85 |
|
T25 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6812570 |
1 |
|
|
T21 |
381 |
|
T22 |
757 |
|
T23 |
28 |
| auto[1] |
4622803 |
1 |
|
|
T21 |
208 |
|
T22 |
1101 |
|
T25 |
12 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10850669 |
1 |
|
|
T21 |
539 |
|
T22 |
1707 |
|
T23 |
28 |
| auto[1] |
584704 |
1 |
|
|
T21 |
50 |
|
T22 |
151 |
|
T26 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6835996 |
1 |
|
|
T21 |
299 |
|
T22 |
1052 |
|
T23 |
28 |
| auto[1] |
4599377 |
1 |
|
|
T21 |
290 |
|
T22 |
806 |
|
T25 |
27 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2012272 |
1 |
|
|
T21 |
160 |
|
T22 |
274 |
|
T25 |
27 |
| auto[1] |
auto[0] |
auto[1] |
294160 |
1 |
|
|
T21 |
34 |
|
T22 |
61 |
|
T27 |
2 |
| auto[1] |
auto[1] |
auto[0] |
2002401 |
1 |
|
|
T21 |
80 |
|
T22 |
381 |
|
T26 |
8 |
| auto[1] |
auto[1] |
auto[1] |
290544 |
1 |
|
|
T21 |
16 |
|
T22 |
90 |
|
T26 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6789856 |
1 |
|
|
T21 |
414 |
|
T22 |
935 |
|
T23 |
28 |
| auto[1] |
4645517 |
1 |
|
|
T21 |
175 |
|
T22 |
923 |
|
T25 |
41 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10847729 |
1 |
|
|
T21 |
527 |
|
T22 |
1690 |
|
T23 |
28 |
| auto[1] |
587644 |
1 |
|
|
T21 |
62 |
|
T22 |
168 |
|
T25 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6831232 |
1 |
|
|
T21 |
255 |
|
T22 |
995 |
|
T23 |
28 |
| auto[1] |
4604141 |
1 |
|
|
T21 |
334 |
|
T22 |
863 |
|
T25 |
42 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2005533 |
1 |
|
|
T21 |
200 |
|
T22 |
297 |
|
T25 |
30 |
| auto[1] |
auto[0] |
auto[1] |
293009 |
1 |
|
|
T21 |
46 |
|
T22 |
65 |
|
T25 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2010964 |
1 |
|
|
T21 |
72 |
|
T22 |
398 |
|
T25 |
11 |
| auto[1] |
auto[1] |
auto[1] |
294635 |
1 |
|
|
T21 |
16 |
|
T22 |
103 |
|
T26 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6811364 |
1 |
|
|
T21 |
372 |
|
T22 |
541 |
|
T23 |
28 |
| auto[1] |
4624009 |
1 |
|
|
T21 |
217 |
|
T22 |
1317 |
|
T25 |
52 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10849856 |
1 |
|
|
T21 |
531 |
|
T22 |
1729 |
|
T23 |
28 |
| auto[1] |
585517 |
1 |
|
|
T21 |
58 |
|
T22 |
129 |
|
T25 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6842981 |
1 |
|
|
T21 |
255 |
|
T22 |
1150 |
|
T23 |
28 |
| auto[1] |
4592392 |
1 |
|
|
T21 |
334 |
|
T22 |
708 |
|
T25 |
56 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2006868 |
1 |
|
|
T21 |
206 |
|
T22 |
203 |
|
T25 |
25 |
| auto[1] |
auto[0] |
auto[1] |
294169 |
1 |
|
|
T21 |
44 |
|
T22 |
46 |
|
T25 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2000007 |
1 |
|
|
T21 |
70 |
|
T22 |
376 |
|
T25 |
30 |
| auto[1] |
auto[1] |
auto[1] |
291348 |
1 |
|
|
T21 |
14 |
|
T22 |
83 |
|
T29 |
1695 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6804640 |
1 |
|
|
T21 |
466 |
|
T22 |
1006 |
|
T23 |
28 |
| auto[1] |
4630733 |
1 |
|
|
T21 |
123 |
|
T22 |
852 |
|
T25 |
52 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10840535 |
1 |
|
|
T21 |
524 |
|
T22 |
1744 |
|
T23 |
28 |
| auto[1] |
594838 |
1 |
|
|
T21 |
65 |
|
T22 |
114 |
|
T29 |
3394 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6787032 |
1 |
|
|
T21 |
236 |
|
T22 |
1165 |
|
T23 |
28 |
| auto[1] |
4648341 |
1 |
|
|
T21 |
353 |
|
T22 |
693 |
|
T25 |
31 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2026748 |
1 |
|
|
T21 |
210 |
|
T22 |
262 |
|
T25 |
17 |
| auto[1] |
auto[0] |
auto[1] |
296910 |
1 |
|
|
T21 |
50 |
|
T22 |
52 |
|
T29 |
1638 |
| auto[1] |
auto[1] |
auto[0] |
2026755 |
1 |
|
|
T21 |
78 |
|
T22 |
317 |
|
T25 |
14 |
| auto[1] |
auto[1] |
auto[1] |
297928 |
1 |
|
|
T21 |
15 |
|
T22 |
62 |
|
T29 |
1756 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6799043 |
1 |
|
|
T21 |
442 |
|
T22 |
1041 |
|
T23 |
28 |
| auto[1] |
4636330 |
1 |
|
|
T21 |
147 |
|
T22 |
817 |
|
T25 |
51 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10844234 |
1 |
|
|
T21 |
526 |
|
T22 |
1658 |
|
T23 |
28 |
| auto[1] |
591139 |
1 |
|
|
T21 |
63 |
|
T22 |
200 |
|
T27 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6802804 |
1 |
|
|
T21 |
211 |
|
T22 |
773 |
|
T23 |
28 |
| auto[1] |
4632569 |
1 |
|
|
T21 |
378 |
|
T22 |
1085 |
|
T25 |
40 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2024569 |
1 |
|
|
T21 |
214 |
|
T22 |
563 |
|
T25 |
29 |
| auto[1] |
auto[0] |
auto[1] |
295531 |
1 |
|
|
T21 |
45 |
|
T22 |
124 |
|
T27 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2016861 |
1 |
|
|
T21 |
101 |
|
T22 |
322 |
|
T25 |
11 |
| auto[1] |
auto[1] |
auto[1] |
295608 |
1 |
|
|
T21 |
18 |
|
T22 |
76 |
|
T29 |
1523 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6824211 |
1 |
|
|
T21 |
484 |
|
T22 |
1160 |
|
T23 |
28 |
| auto[1] |
4611162 |
1 |
|
|
T21 |
105 |
|
T22 |
698 |
|
T25 |
59 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10847021 |
1 |
|
|
T21 |
546 |
|
T22 |
1738 |
|
T23 |
28 |
| auto[1] |
588352 |
1 |
|
|
T21 |
43 |
|
T22 |
120 |
|
T27 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6824783 |
1 |
|
|
T21 |
360 |
|
T22 |
1179 |
|
T23 |
28 |
| auto[1] |
4610590 |
1 |
|
|
T21 |
229 |
|
T22 |
679 |
|
T25 |
30 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2020728 |
1 |
|
|
T21 |
166 |
|
T22 |
348 |
|
T25 |
17 |
| auto[1] |
auto[0] |
auto[1] |
295556 |
1 |
|
|
T21 |
38 |
|
T22 |
75 |
|
T29 |
1822 |
| auto[1] |
auto[1] |
auto[0] |
2001510 |
1 |
|
|
T21 |
20 |
|
T22 |
211 |
|
T25 |
13 |
| auto[1] |
auto[1] |
auto[1] |
292796 |
1 |
|
|
T21 |
5 |
|
T22 |
45 |
|
T27 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6813662 |
1 |
|
|
T21 |
327 |
|
T22 |
863 |
|
T23 |
28 |
| auto[1] |
4621711 |
1 |
|
|
T21 |
262 |
|
T22 |
995 |
|
T25 |
51 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10849751 |
1 |
|
|
T21 |
531 |
|
T22 |
1706 |
|
T23 |
28 |
| auto[1] |
585622 |
1 |
|
|
T21 |
58 |
|
T22 |
152 |
|
T26 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6841508 |
1 |
|
|
T21 |
239 |
|
T22 |
1069 |
|
T23 |
28 |
| auto[1] |
4593865 |
1 |
|
|
T21 |
350 |
|
T22 |
789 |
|
T25 |
22 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2007640 |
1 |
|
|
T21 |
147 |
|
T22 |
270 |
|
T25 |
8 |
| auto[1] |
auto[0] |
auto[1] |
293478 |
1 |
|
|
T21 |
30 |
|
T22 |
67 |
|
T29 |
1575 |
| auto[1] |
auto[1] |
auto[0] |
2000603 |
1 |
|
|
T21 |
145 |
|
T22 |
367 |
|
T25 |
14 |
| auto[1] |
auto[1] |
auto[1] |
292144 |
1 |
|
|
T21 |
28 |
|
T22 |
85 |
|
T26 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6786846 |
1 |
|
|
T21 |
395 |
|
T22 |
974 |
|
T23 |
28 |
| auto[1] |
4648527 |
1 |
|
|
T21 |
194 |
|
T22 |
884 |
|
T25 |
45 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10844387 |
1 |
|
|
T21 |
534 |
|
T22 |
1687 |
|
T23 |
28 |
| auto[1] |
590986 |
1 |
|
|
T21 |
55 |
|
T22 |
171 |
|
T29 |
3076 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6805543 |
1 |
|
|
T21 |
289 |
|
T22 |
994 |
|
T23 |
28 |
| auto[1] |
4629830 |
1 |
|
|
T21 |
300 |
|
T22 |
864 |
|
T25 |
51 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2004306 |
1 |
|
|
T21 |
141 |
|
T22 |
313 |
|
T25 |
33 |
| auto[1] |
auto[0] |
auto[1] |
292085 |
1 |
|
|
T21 |
36 |
|
T22 |
76 |
|
T29 |
1491 |
| auto[1] |
auto[1] |
auto[0] |
2034538 |
1 |
|
|
T21 |
104 |
|
T22 |
380 |
|
T25 |
18 |
| auto[1] |
auto[1] |
auto[1] |
298901 |
1 |
|
|
T21 |
19 |
|
T22 |
95 |
|
T29 |
1585 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6849604 |
1 |
|
|
T21 |
149 |
|
T22 |
814 |
|
T23 |
28 |
| auto[1] |
4585769 |
1 |
|
|
T21 |
440 |
|
T22 |
1044 |
|
T25 |
40 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10844071 |
1 |
|
|
T21 |
539 |
|
T22 |
1632 |
|
T23 |
28 |
| auto[1] |
591302 |
1 |
|
|
T21 |
50 |
|
T22 |
226 |
|
T26 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6805066 |
1 |
|
|
T21 |
346 |
|
T22 |
685 |
|
T23 |
28 |
| auto[1] |
4630307 |
1 |
|
|
T21 |
243 |
|
T22 |
1173 |
|
T25 |
34 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2041408 |
1 |
|
|
T22 |
519 |
|
T25 |
20 |
|
T27 |
30 |
| auto[1] |
auto[0] |
auto[1] |
299845 |
1 |
|
|
T22 |
123 |
|
T27 |
1 |
|
T29 |
1434 |
| auto[1] |
auto[1] |
auto[0] |
1997597 |
1 |
|
|
T21 |
193 |
|
T22 |
428 |
|
T25 |
14 |
| auto[1] |
auto[1] |
auto[1] |
291457 |
1 |
|
|
T21 |
50 |
|
T22 |
103 |
|
T26 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6792510 |
1 |
|
|
T21 |
253 |
|
T22 |
785 |
|
T23 |
28 |
| auto[1] |
4642863 |
1 |
|
|
T21 |
336 |
|
T22 |
1073 |
|
T25 |
52 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10844438 |
1 |
|
|
T21 |
558 |
|
T22 |
1681 |
|
T23 |
28 |
| auto[1] |
590935 |
1 |
|
|
T21 |
31 |
|
T22 |
177 |
|
T26 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6809161 |
1 |
|
|
T21 |
385 |
|
T22 |
964 |
|
T23 |
28 |
| auto[1] |
4626212 |
1 |
|
|
T21 |
204 |
|
T22 |
894 |
|
T25 |
20 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2011600 |
1 |
|
|
T21 |
56 |
|
T22 |
235 |
|
T25 |
15 |
| auto[1] |
auto[0] |
auto[1] |
295154 |
1 |
|
|
T21 |
10 |
|
T22 |
65 |
|
T26 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2023677 |
1 |
|
|
T21 |
117 |
|
T22 |
482 |
|
T25 |
5 |
| auto[1] |
auto[1] |
auto[1] |
295781 |
1 |
|
|
T21 |
21 |
|
T22 |
112 |
|
T29 |
1430 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6797501 |
1 |
|
|
T21 |
482 |
|
T22 |
1124 |
|
T23 |
28 |
| auto[1] |
4637872 |
1 |
|
|
T21 |
107 |
|
T22 |
734 |
|
T25 |
58 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10845418 |
1 |
|
|
T21 |
540 |
|
T22 |
1678 |
|
T23 |
28 |
| auto[1] |
589955 |
1 |
|
|
T21 |
49 |
|
T22 |
180 |
|
T25 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6812921 |
1 |
|
|
T21 |
327 |
|
T22 |
887 |
|
T23 |
28 |
| auto[1] |
4622452 |
1 |
|
|
T21 |
262 |
|
T22 |
971 |
|
T25 |
42 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2004711 |
1 |
|
|
T21 |
164 |
|
T22 |
538 |
|
T25 |
26 |
| auto[1] |
auto[0] |
auto[1] |
293467 |
1 |
|
|
T21 |
36 |
|
T22 |
122 |
|
T25 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2027786 |
1 |
|
|
T21 |
49 |
|
T22 |
253 |
|
T25 |
15 |
| auto[1] |
auto[1] |
auto[1] |
296488 |
1 |
|
|
T21 |
13 |
|
T22 |
58 |
|
T26 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6823263 |
1 |
|
|
T21 |
268 |
|
T22 |
891 |
|
T23 |
28 |
| auto[1] |
4612110 |
1 |
|
|
T21 |
321 |
|
T22 |
967 |
|
T25 |
59 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10844804 |
1 |
|
|
T21 |
534 |
|
T22 |
1719 |
|
T23 |
28 |
| auto[1] |
590569 |
1 |
|
|
T21 |
55 |
|
T22 |
139 |
|
T25 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6804656 |
1 |
|
|
T21 |
305 |
|
T22 |
1176 |
|
T23 |
28 |
| auto[1] |
4630717 |
1 |
|
|
T21 |
284 |
|
T22 |
682 |
|
T25 |
44 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2017135 |
1 |
|
|
T21 |
92 |
|
T22 |
212 |
|
T25 |
23 |
| auto[1] |
auto[0] |
auto[1] |
294351 |
1 |
|
|
T21 |
22 |
|
T22 |
47 |
|
T25 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2023013 |
1 |
|
|
T21 |
137 |
|
T22 |
331 |
|
T25 |
20 |
| auto[1] |
auto[1] |
auto[1] |
296218 |
1 |
|
|
T21 |
33 |
|
T22 |
92 |
|
T26 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6822034 |
1 |
|
|
T21 |
412 |
|
T22 |
1179 |
|
T23 |
28 |
| auto[1] |
4613339 |
1 |
|
|
T21 |
177 |
|
T22 |
679 |
|
T25 |
30 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10846902 |
1 |
|
|
T21 |
550 |
|
T22 |
1718 |
|
T23 |
28 |
| auto[1] |
588471 |
1 |
|
|
T21 |
39 |
|
T22 |
140 |
|
T29 |
3291 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6830170 |
1 |
|
|
T21 |
369 |
|
T22 |
1111 |
|
T23 |
28 |
| auto[1] |
4605203 |
1 |
|
|
T21 |
220 |
|
T22 |
747 |
|
T25 |
11 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2016275 |
1 |
|
|
T21 |
106 |
|
T22 |
400 |
|
T25 |
6 |
| auto[1] |
auto[0] |
auto[1] |
295136 |
1 |
|
|
T21 |
19 |
|
T22 |
95 |
|
T29 |
1756 |
| auto[1] |
auto[1] |
auto[0] |
2000457 |
1 |
|
|
T21 |
75 |
|
T22 |
207 |
|
T25 |
5 |
| auto[1] |
auto[1] |
auto[1] |
293335 |
1 |
|
|
T21 |
20 |
|
T22 |
45 |
|
T29 |
1535 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6831422 |
1 |
|
|
T21 |
408 |
|
T22 |
925 |
|
T23 |
28 |
| auto[1] |
4603951 |
1 |
|
|
T21 |
181 |
|
T22 |
933 |
|
T25 |
44 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10842715 |
1 |
|
|
T21 |
540 |
|
T22 |
1643 |
|
T23 |
28 |
| auto[1] |
592658 |
1 |
|
|
T21 |
49 |
|
T22 |
215 |
|
T29 |
3228 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6800494 |
1 |
|
|
T21 |
364 |
|
T22 |
769 |
|
T23 |
28 |
| auto[1] |
4634879 |
1 |
|
|
T21 |
225 |
|
T22 |
1089 |
|
T25 |
60 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2028887 |
1 |
|
|
T21 |
100 |
|
T22 |
436 |
|
T25 |
36 |
| auto[1] |
auto[0] |
auto[1] |
297410 |
1 |
|
|
T21 |
30 |
|
T22 |
108 |
|
T29 |
1619 |
| auto[1] |
auto[1] |
auto[0] |
2013334 |
1 |
|
|
T21 |
76 |
|
T22 |
438 |
|
T25 |
24 |
| auto[1] |
auto[1] |
auto[1] |
295248 |
1 |
|
|
T21 |
19 |
|
T22 |
107 |
|
T29 |
1609 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6821722 |
1 |
|
|
T21 |
477 |
|
T22 |
898 |
|
T23 |
28 |
| auto[1] |
4613651 |
1 |
|
|
T21 |
112 |
|
T22 |
960 |
|
T25 |
51 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10844337 |
1 |
|
|
T21 |
517 |
|
T22 |
1672 |
|
T23 |
28 |
| auto[1] |
591036 |
1 |
|
|
T21 |
72 |
|
T22 |
186 |
|
T27 |
3 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6800829 |
1 |
|
|
T21 |
234 |
|
T22 |
894 |
|
T23 |
28 |
| auto[1] |
4634544 |
1 |
|
|
T21 |
355 |
|
T22 |
964 |
|
T25 |
60 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2026324 |
1 |
|
|
T21 |
234 |
|
T22 |
448 |
|
T25 |
25 |
| auto[1] |
auto[0] |
auto[1] |
295983 |
1 |
|
|
T21 |
61 |
|
T22 |
103 |
|
T27 |
3 |
| auto[1] |
auto[1] |
auto[0] |
2017184 |
1 |
|
|
T21 |
49 |
|
T22 |
330 |
|
T25 |
35 |
| auto[1] |
auto[1] |
auto[1] |
295053 |
1 |
|
|
T21 |
11 |
|
T22 |
83 |
|
T29 |
1428 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6823270 |
1 |
|
|
T21 |
515 |
|
T22 |
902 |
|
T23 |
28 |
| auto[1] |
4612103 |
1 |
|
|
T21 |
74 |
|
T22 |
956 |
|
T25 |
11 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10849473 |
1 |
|
|
T21 |
532 |
|
T22 |
1701 |
|
T23 |
28 |
| auto[1] |
585900 |
1 |
|
|
T21 |
57 |
|
T22 |
157 |
|
T27 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6840220 |
1 |
|
|
T21 |
295 |
|
T22 |
995 |
|
T23 |
28 |
| auto[1] |
4595153 |
1 |
|
|
T21 |
294 |
|
T22 |
863 |
|
T25 |
56 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2005180 |
1 |
|
|
T21 |
177 |
|
T22 |
392 |
|
T25 |
56 |
| auto[1] |
auto[0] |
auto[1] |
292541 |
1 |
|
|
T21 |
43 |
|
T22 |
93 |
|
T27 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2004073 |
1 |
|
|
T21 |
60 |
|
T22 |
314 |
|
T26 |
3 |
| auto[1] |
auto[1] |
auto[1] |
293359 |
1 |
|
|
T21 |
14 |
|
T22 |
64 |
|
T29 |
1576 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6817431 |
1 |
|
|
T21 |
435 |
|
T22 |
1032 |
|
T23 |
28 |
| auto[1] |
4617942 |
1 |
|
|
T21 |
154 |
|
T22 |
826 |
|
T25 |
30 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10847414 |
1 |
|
|
T21 |
560 |
|
T22 |
1666 |
|
T23 |
28 |
| auto[1] |
587959 |
1 |
|
|
T21 |
29 |
|
T22 |
192 |
|
T26 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6818716 |
1 |
|
|
T21 |
427 |
|
T22 |
854 |
|
T23 |
28 |
| auto[1] |
4616657 |
1 |
|
|
T21 |
162 |
|
T22 |
1004 |
|
T25 |
19 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2017770 |
1 |
|
|
T21 |
122 |
|
T22 |
446 |
|
T25 |
19 |
| auto[1] |
auto[0] |
auto[1] |
294369 |
1 |
|
|
T21 |
27 |
|
T22 |
107 |
|
T26 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2010928 |
1 |
|
|
T21 |
11 |
|
T22 |
366 |
|
T26 |
3 |
| auto[1] |
auto[1] |
auto[1] |
293590 |
1 |
|
|
T21 |
2 |
|
T22 |
85 |
|
T29 |
1560 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6809657 |
1 |
|
|
T21 |
241 |
|
T22 |
950 |
|
T23 |
28 |
| auto[1] |
4625716 |
1 |
|
|
T21 |
348 |
|
T22 |
908 |
|
T25 |
38 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10845748 |
1 |
|
|
T21 |
539 |
|
T22 |
1700 |
|
T23 |
28 |
| auto[1] |
589625 |
1 |
|
|
T21 |
50 |
|
T22 |
158 |
|
T25 |
2 |