Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6824050 |
1 |
|
|
T21 |
253 |
|
T22 |
1007 |
|
T23 |
28 |
| auto[1] |
4611323 |
1 |
|
|
T21 |
336 |
|
T22 |
851 |
|
T25 |
55 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9446237 |
1 |
|
|
T21 |
434 |
|
T22 |
1487 |
|
T23 |
28 |
| auto[1] |
1989136 |
1 |
|
|
T21 |
155 |
|
T22 |
371 |
|
T25 |
15 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6809758 |
1 |
|
|
T21 |
271 |
|
T22 |
1098 |
|
T23 |
28 |
| auto[1] |
4625615 |
1 |
|
|
T21 |
318 |
|
T22 |
760 |
|
T25 |
34 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1330222 |
1 |
|
|
T21 |
97 |
|
T22 |
237 |
|
T25 |
13 |
| auto[1] |
auto[0] |
auto[1] |
1002903 |
1 |
|
|
T21 |
101 |
|
T22 |
214 |
|
T25 |
9 |
| auto[1] |
auto[1] |
auto[0] |
1306257 |
1 |
|
|
T21 |
66 |
|
T22 |
152 |
|
T25 |
6 |
| auto[1] |
auto[1] |
auto[1] |
986233 |
1 |
|
|
T21 |
54 |
|
T22 |
157 |
|
T25 |
6 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |