Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6809218 |
1 |
|
|
T21 |
340 |
|
T22 |
964 |
|
T23 |
28 |
| auto[1] |
4626155 |
1 |
|
|
T21 |
249 |
|
T22 |
894 |
|
T25 |
49 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2022806 |
1 |
|
|
T21 |
54 |
|
T22 |
373 |
|
T25 |
36 |
| auto[1] |
auto[0] |
auto[1] |
295061 |
1 |
|
|
T21 |
15 |
|
T22 |
77 |
|
T25 |
2 |
| auto[1] |
auto[1] |
auto[0] |
2013724 |
1 |
|
|
T21 |
145 |
|
T22 |
363 |
|
T25 |
11 |
| auto[1] |
auto[1] |
auto[1] |
294564 |
1 |
|
|
T21 |
35 |
|
T22 |
81 |
|
T27 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |