Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6799043 |
1 |
|
|
T21 |
442 |
|
T22 |
1041 |
|
T23 |
28 |
| auto[1] |
4636330 |
1 |
|
|
T21 |
147 |
|
T22 |
817 |
|
T25 |
51 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9436645 |
1 |
|
|
T21 |
396 |
|
T22 |
1401 |
|
T23 |
28 |
| auto[1] |
1998728 |
1 |
|
|
T21 |
193 |
|
T22 |
457 |
|
T25 |
31 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6800330 |
1 |
|
|
T21 |
212 |
|
T22 |
1023 |
|
T23 |
28 |
| auto[1] |
4635043 |
1 |
|
|
T21 |
377 |
|
T22 |
835 |
|
T25 |
48 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1318267 |
1 |
|
|
T21 |
140 |
|
T22 |
197 |
|
T25 |
1 |
| auto[1] |
auto[0] |
auto[1] |
997075 |
1 |
|
|
T21 |
161 |
|
T22 |
241 |
|
T25 |
19 |
| auto[1] |
auto[1] |
auto[0] |
1318048 |
1 |
|
|
T21 |
44 |
|
T22 |
181 |
|
T25 |
16 |
| auto[1] |
auto[1] |
auto[1] |
1001653 |
1 |
|
|
T21 |
32 |
|
T22 |
216 |
|
T25 |
12 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |