Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6824211 |
1 |
|
|
T21 |
484 |
|
T22 |
1160 |
|
T23 |
28 |
| auto[1] |
4611162 |
1 |
|
|
T21 |
105 |
|
T22 |
698 |
|
T25 |
59 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9464291 |
1 |
|
|
T21 |
427 |
|
T22 |
1514 |
|
T23 |
28 |
| auto[1] |
1971082 |
1 |
|
|
T21 |
162 |
|
T22 |
344 |
|
T25 |
16 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6860934 |
1 |
|
|
T21 |
261 |
|
T22 |
1178 |
|
T23 |
28 |
| auto[1] |
4574439 |
1 |
|
|
T21 |
328 |
|
T22 |
680 |
|
T25 |
45 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1301251 |
1 |
|
|
T21 |
158 |
|
T22 |
262 |
|
T25 |
18 |
| auto[1] |
auto[0] |
auto[1] |
986358 |
1 |
|
|
T21 |
147 |
|
T22 |
282 |
|
T25 |
13 |
| auto[1] |
auto[1] |
auto[0] |
1302106 |
1 |
|
|
T21 |
8 |
|
T22 |
74 |
|
T25 |
11 |
| auto[1] |
auto[1] |
auto[1] |
984724 |
1 |
|
|
T21 |
15 |
|
T22 |
62 |
|
T25 |
3 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |