Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6823263 |
1 |
|
|
T21 |
268 |
|
T22 |
891 |
|
T23 |
28 |
| auto[1] |
4612110 |
1 |
|
|
T21 |
321 |
|
T22 |
967 |
|
T25 |
59 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9460399 |
1 |
|
|
T21 |
413 |
|
T22 |
1348 |
|
T23 |
28 |
| auto[1] |
1974974 |
1 |
|
|
T21 |
176 |
|
T22 |
510 |
|
T25 |
22 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6850980 |
1 |
|
|
T21 |
184 |
|
T22 |
815 |
|
T23 |
28 |
| auto[1] |
4584393 |
1 |
|
|
T21 |
405 |
|
T22 |
1043 |
|
T25 |
42 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1319030 |
1 |
|
|
T21 |
132 |
|
T22 |
245 |
|
T25 |
11 |
| auto[1] |
auto[0] |
auto[1] |
995537 |
1 |
|
|
T21 |
103 |
|
T22 |
247 |
|
T25 |
11 |
| auto[1] |
auto[1] |
auto[0] |
1290389 |
1 |
|
|
T21 |
97 |
|
T22 |
288 |
|
T25 |
9 |
| auto[1] |
auto[1] |
auto[1] |
979437 |
1 |
|
|
T21 |
73 |
|
T22 |
263 |
|
T25 |
11 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |