Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6821722 |
1 |
|
|
T21 |
477 |
|
T22 |
898 |
|
T23 |
28 |
| auto[1] |
4613651 |
1 |
|
|
T21 |
112 |
|
T22 |
960 |
|
T25 |
51 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9441962 |
1 |
|
|
T21 |
535 |
|
T22 |
1459 |
|
T23 |
28 |
| auto[1] |
1993411 |
1 |
|
|
T21 |
54 |
|
T22 |
399 |
|
T25 |
19 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6785770 |
1 |
|
|
T21 |
484 |
|
T22 |
1055 |
|
T23 |
28 |
| auto[1] |
4649603 |
1 |
|
|
T21 |
105 |
|
T22 |
803 |
|
T25 |
36 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1330770 |
1 |
|
|
T21 |
24 |
|
T22 |
230 |
|
T25 |
8 |
| auto[1] |
auto[0] |
auto[1] |
1002154 |
1 |
|
|
T21 |
34 |
|
T22 |
224 |
|
T25 |
15 |
| auto[1] |
auto[1] |
auto[0] |
1325422 |
1 |
|
|
T21 |
27 |
|
T22 |
174 |
|
T25 |
9 |
| auto[1] |
auto[1] |
auto[1] |
991257 |
1 |
|
|
T21 |
20 |
|
T22 |
175 |
|
T25 |
4 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |